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kv10.asm
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;;; Microcode for the KV10
;;;
;;; 0000
;; at startup or reset, we begin executing from location 0000
reset: aluSETZ,loadM clrPSW ; move 0 into M
clrPSW: mM,aluSETM,loadPSW initpc ; clear the PSW (could do this and the previous instruction in one step now!!!)
initpc: aINIT,loadPC fetch ; setup the initial PC
;; This is almost the only use of aPC and it could be implemented elsewise
;; (loading E and jumping there) !!!
fetch: aPC,readMEM,memIF fetchI ; a common point to start an instruction fetch from PC
halt
halt
halt
halt
;;; 0010
;; load the instruction. saveFLAGS has the effect here of clearing the saved flags.
;; loop until read_ack.
fetchI: mMEM,aluSETM,saveFLAGS,loadM,loadOPA,loadIX,loadY,brREAD .
;; this is also a jump destination when the instruction has already
;; been loaded
strtEA: brIX calcEA ; start the EA calculation
;; load an instruction from the PC
;fetchI: brREAD . ; loop, waiting for a response
;; load the instruction and start the EA calculation saveFLAGS has the effect here
;; of clearing the saved flags
; mMEM,aluSETM,saveFLAGS,loadM,loadOPA,loadIX,loadY,brIX calcEA
halt
halt
;; Read the Index Register. In some cases (using XCTR) this could actually be
;; reading from memory.
readX: aE,mMEM,aluADD,loadY,loadM,brREAD . ; E <- E+(X) does this need to load M with MEM rather than the sum? !!!
brI checkI
halt
halt
;;; 0020
;; 3-way branch on Index and Indirect (taken from write_data).
calcEA: aX,readMEM,memE1 readX ; read the Index Register
aE,readMEM,memE1 readI ; Indirect
brDISPATCH dispatch ; EAcalc done, dispatch on the OpCode
halt
;; do the read for an Indirect and loop back to calcEA
readI: mMEM,aluSETM,loadIX,loadY,loadM,brREAD .
brIX calcEA
halt
halt
;;; 0030
;; If there was a Index, now check if there's an Indirect too
checkI: brDISPATCH dispatch ; EAcalc done, dispatch on the OpCode
aE,readMEM,memE1 readI ; start the read for the Indirect
halt
halt
halt
halt
halt
halt
;;; 0040
;; conditional jump
jumpc: aPCnext,aluSETA,loadPC,readMEM,memIF fetchI
aE,mE,aluSETM,loadPC,readMEM,memIF fetchI
;; conditional skip
skipc: aPCnext,aluSETA,loadPC,readMEM,memIF fetchI
aPCskip,aluSETA,loadPC,readMEM,memIF fetchI
;; for SKIP and SOS instructions, write M to AC if AC not 0
wrskip: mM,aluSETM,brCOMP0 skipc
mM,aluSETM,writeAC,brCOMP0 skipc
halt
halt
;;; 0050
;; write M to memory
wrmem1: brWRITE .
aPCnext,aluSETA,setFLAGS,loadPC,readMEM,memIF fetchI
wrmem: aE,mM,aluSETM,writeMEM,memD1,brWRITE wrmem1
halt
;; write M to memory and then to AC if AC not 0
wrself1: brWRITE .
setFLAGS,brSELF wrselfA
wrself: aE,mM,aluSETM,writeMEM,memD1,brWRITE wrself1
halt
;;; 0060
;; write M to AC if AC is not 0
wrselfA: aPCnext,aluSETA,loadPC,readMEM,memIF fetchI
aPCnext,mM,aluSETM,writeAC,loadPC,readMEM,memIF fetchI
halt
halt
;; write M to memory and then to AC
wrboth1: brWRITE .
aPCnext,mM,aluSETM,setFLAGS,writeAC,loadPC,readMEM,memIF fetchI
wrboth: aE,mM,aluSETM,writeMEM,memD1,brWRITE wrboth1
;; finish up with a jump to E
jumpe: aE,aluSETA,loadPC,readMEM,memIF fetchI
;;; 0070
;; finish up the EXCH instruction
exch: brWRITE .
aPCnext,mM,aluSETM,writeAC,loadPC,readMEM,memIF fetchI ; write M to AC and we're done
halt
halt
;; Jump if any of the flags were cleared
jfcl: aPCnext,aluSETA,loadPC,readMEM,memIF fetchI ; no jump
aE,aluSETA,loadPC,readMEM,memIF fetchI ; jump
halt
halt
;;; 0100
;; finish up JSA
jsa: brWRITE .
aPCnext,mE,swapM,aluHLL,writeAC jsa1 ; AC <- E,PC
halt
jsa1: aE,aluSETA,loadPC next ; jump E+1
halt
halt
halt
halt
;;; 0110
;; Write to memory after SOS, then write to self and save flags
sosWR1: brWRITE . ; wait for the memory write to complete
mM,aluSETM,setFLAGS,brSELF wrskip ; now that the memory write completed, set flags
sosWR: aE,mM,aluSETM,writeMEM,memD1,brWRITE sosWR1 ; start write to memory
halt
;; finish up JSR
jsr1: brWRITE .
aE,aluSETA,loadPC,clrFPD next ; jump E+1
halt
jsr: aE,mM,aluSETM,writeMEM,memD1,brWRITE jsr1
;;; 0120
;; For the Test instructions
;; The next and skip labels are for general use when we need an unconditional next or skip operation
;; if the operands and'd together are 0, then skip
teste: aPCskip,loadPC,readMEM,memIF fetchI
next: aPCnext,loadPC,readMEM,memIF fetchI
;; if the operands and'd together are not 0, then skip
testn: aPCnext,loadPC,readMEM,memIF fetchI
skip: aPCskip,loadPC,readMEM,memIF fetchI
halt
halt
halt
halt
;;; 0130
;; finish up JRA
jra1: mMEM,aluSETM,writeAC,brREAD . ; AC now gets C(LEFT(AC))
aE,aluSETA,loadPC,readMEM,memIF fetchI ; jump E
halt
halt
jra: aA,readMEM,memD1 jra1 ; A has swapped AC
halt
halt
halt
;;; 0140
;; finish up PUSH
push1: brWRITE .
aA,aluSETA,writeAC next ; saved the increment AC in A into AC
halt
push: aA,mM,aluSETM,writeMEM,memD1,brWRITE push1
halt
halt
halt
halt
;;; 0150
;; finish up POP
pop: mMEM,aluSETM,loadM,brREAD .
aE,mM,aluSETM,writeMEM,memD1,brWRITE pop2
halt
halt
pop2: brWRITE .
aPCnext,mAC,aluSOB,writeAC,loadPC,setPDO,readMEM,memIF fetchI
halt
halt
;;; 0160
;; Finish up PUSHJ
pushj3: brWRITE .
aA,aluSETA,writeAC,clrFPD jumpe ; saved the incremented AC in A into AC
halt
pushj: mAC,aluAOB,loadA,setPDO pushj2 ; increment AC into A
pushj2: aA,mM,aluSETM,writeMEM,memD1,brWRITE pushj3 ; C(AC) <- PSW,PCnext (which is in M)
halt
halt
halt
;;; 0170
;; Finish up POPJ
popj: mMEM,aluSETM,loadM,brREAD .
;; writes M into PC and SOB(AC) into AC
aM,mAC,aluSOB,loadPC,setPDO,writeAC,readMEM,memIF,brWRITE fetch ; decrement AC
halt
halt
halt
halt
halt
halt
;;; 0200
ashc: aAC,mE,aluASHC,loadB,writeAC,saveFLAGS,setFLAGS wrb
rotc: aAC,mE,aluROTC,loadB,writeAC wrb
lshc: aAC,mE,aluLSHC,loadB,writeAC wrb
wrb: aPCnext,aluSETB,ACnext,writeAC,loadPC,readMEM,memIF fetchI ; write B into A+1
halt
halt
halt
halt
;;; 0210
;; MULx and IMULx
mul0: aA,mM,aluMULADD,loadA,loadB mul1
mul1: aA,mM,aluMULADD,loadA,loadB mul2
mul2: aA,mM,aluMULADD,loadA,loadB mul3
mul3: aA,mM,aluMULADD,loadA,loadB mul4
mul4: aA,mM,aluMULADD,loadA,loadB mul5
mul5: aA,mM,aluMULADD,loadA,loadB mul6
mul6: aA,mM,aluMULADD,loadA,loadB mul7
mul7: aA,mM,aluMULADD,loadA,loadB mul10
;;; 0220
mul10: aA,mM,aluMULADD,loadA,loadB mul11
mul11: aA,mM,aluMULADD,loadA,loadB mul12
mul12: aA,mM,aluMULADD,loadA,loadB mul13
mul13: aA,mM,aluMULADD,loadA,loadB mul14
mul14: aA,mM,aluMULADD,loadA,loadB mul15
mul15: aA,mM,aluMULADD,loadA,loadB mul16
mul16: aA,mM,aluMULADD,loadA,loadB mul17
mul17: aA,mM,aluMULADD,loadA,loadB mul20
;;; 0230
mul20: aA,mM,aluMULADD,loadA,loadB mul21
mul21: aA,mM,aluMULADD,loadA,loadB mul22
mul22: aA,mM,aluMULADD,loadA,loadB mul23
mul23: aA,mM,aluMULADD,loadA,loadB mul24
mul24: aA,mM,aluMULADD,loadA,loadB mul25
mul25: aA,mM,aluMULADD,loadA,loadB mul26
mul26: aA,mM,aluMULADD,loadA,loadB mul27
mul27: aA,mM,aluMULADD,loadA,loadB mul30
;;; 0240
mul30: aA,mM,aluMULADD,loadA,loadB mul31
mul31: aA,mM,aluMULADD,loadA,loadB mul32
mul32: aA,mM,aluMULADD,loadA,loadB mul33
mul33: aA,mM,aluMULADD,loadA,loadB mul34
mul34: aA,mM,aluMULADD,loadA,loadB mul35
mul35: aA,mM,aluMULADD,loadA,loadB mul36
mul36: aA,mM,aluMULADD,loadA,loadB mul37
mul37: aA,mM,aluMULADD,loadA,loadB mul40
;;; 0250
mul40: aA,mM,aluMULADD,loadA,loadB mul41
mul41: aA,mM,aluMULADD,loadA,loadB mul42
mul42: aA,mM,aluMULADD,loadA,loadB,brMUL imulwr
halt
;; writing to memory for IMULB
imulb1: brWRITE .
aPCnext,mM,aluSETM,loadPC,setFLAGS,writeAC,readMEM,memIF fetchI ; write to AC
halt
imulb: aE,mM,aluSETM,writeMEM,memD1,brWRITE imulb1 ; start the write to memory
;;; 0260
;; Do final operation to finish the multiply and then write answer where it needs to go
imulwr: aA,mM,aluIMULSUB,saveFLAGS,setFLAGS,writeAC,loadB next ; MUL : write to AC
aA,mM,aluIMULSUB,saveFLAGS,setFLAGS,writeAC,loadB next ; IMUL : write to AC
aA,mM,aluIMULSUB,saveFLAGS,loadM,loadA,loadB mulm ; MULM : put answer in M also
aA,mM,aluIMULSUB,saveFLAGS,loadM,loadA,loadB imulb ; MULB : put answer in M also
mulwr: aA,mM,aluMULSUB,saveFLAGS,setFLAGS,writeAC,loadB wrb ; MUL : write to AC and then AC+1
aA,mM,aluMULSUB,saveFLAGS,setFLAGS,writeAC,loadB wrb ; IMUL : write to AC and then AC+1
aA,mM,aluMULSUB,saveFLAGS,loadM,loadA,loadB mulm ; MULM : put answer in M also
aA,mM,aluMULSUB,saveFLAGS,loadM,loadA,loadB mulb ; MULB : put answer in M also
;;; 0270
;; writing to memory for MULM and IMULM
mulm1: brWRITE .
aPCnext,setFLAGS,loadPC,readMEM,memIF fetchI ; set flags and move on
halt
mulm: aE,mM,aluSETM,writeMEM,memD1,brWRITE mulm1 ; start the write to memory
;; writing to memory for MULB
mulb1: brWRITE .
mM,aluSETM,setFLAGS,writeAC wrb ; write to AC and then AC+1
halt
mulb: aE,mM,aluSETM,writeMEM,memD1,brWRITE mulb1 ; start the write to memory
;;; 0300
;; IDIVx and DIVx
;; div01 is a little different because it's where the check for overflow happens
div00: aA,mM,aluDIVOP,loadA,loadB,brOVR div01
halt
div02: aA,mM,aluDIVOP,loadA,loadB div03
div03: aA,mM,aluDIVOP,loadA,loadB div04
div04: aA,mM,aluDIVOP,loadA,loadB div05
div05: aA,mM,aluDIVOP,loadA,loadB div06
div06: aA,mM,aluDIVOP,loadA,loadB div07
div07: aA,mM,aluDIVOP,loadA,loadB div10
;;; 0310
div10: aA,mM,aluDIVOP,loadA,loadB div11
div11: aA,mM,aluDIVOP,loadA,loadB div12
div12: aA,mM,aluDIVOP,loadA,loadB div13
div13: aA,mM,aluDIVOP,loadA,loadB div14
div14: aA,mM,aluDIVOP,loadA,loadB div15
div15: aA,mM,aluDIVOP,loadA,loadB div16
div16: aA,mM,aluDIVOP,loadA,loadB div17
div17: aA,mM,aluDIVOP,loadA,loadB div20
;;; 0320
div20: aA,mM,aluDIVOP,loadA,loadB div21
div21: aA,mM,aluDIVOP,loadA,loadB div22
div22: aA,mM,aluDIVOP,loadA,loadB div23
div23: aA,mM,aluDIVOP,loadA,loadB div24
div24: aA,mM,aluDIVOP,loadA,loadB div25
div25: aA,mM,aluDIVOP,loadA,loadB div26
div26: aA,mM,aluDIVOP,loadA,loadB div27
div27: aA,mM,aluDIVOP,loadA,loadB div30
;;; 0330
div30: aA,mM,aluDIVOP,loadA,loadB div31
div31: aA,mM,aluDIVOP,loadA,loadB div32
div32: aA,mM,aluDIVOP,loadA,loadB div33
div33: aA,mM,aluDIVOP,loadA,loadB div34
div34: aA,mM,aluDIVOP,loadA,loadB div35
div35: aA,mM,aluDIVOP,loadA,loadB div36
div36: aA,mM,aluDIVOP,loadA,loadB div37
div37: aA,mM,aluDIVOP,loadA,loadB div40
;;; 0340
div40: aA,mM,aluDIVOP,loadA,loadB div41
div41: aA,mM,aluDIVOP,loadA,loadB div42
div42: aA,mM,aluDIVOP,loadA,loadB div43
div43: aA,mM,aluDIVOP,loadA,loadB fixr
fixr: aA,mM,aluDIVFIXR,loadA,loadB,brMUL idivwr
;; loads A,B <- |AC,B|
divhi: aAC,aluDIVMAG72,loadA,loadB div00
;; check for overflow
div01: aA,mM,aluDIVOP,loadA,loadB div02
aPCnext,aluSETA,loadPC,setOVF,setNODIV,readMEM,memIF fetchI
;;; 0350
;; Do final fixup for DIV and write answer where it needs to go
idivwr: aA,mM,aluDIVFIXUP,loadA,loadB,writeAC wrb ; IDIV : AC <- A (quotient)
aA,mM,aluDIVFIXUP,loadA,loadB,writeAC wrb ; IDIVI : AC <- A (quotient)
aA,mM,aluDIVFIXUP,loadA,loadB,loadM divm ; IDIVM : move quotient to M
aA,mM,aluDIVFIXUP,loadA,loadB,loadM divb ; IDIVB : move quotient to M
aA,mM,aluDIVFIXUP,loadA,loadB,writeAC wrb ; DIV : AC <- A (quotient)
aA,mM,aluDIVFIXUP,loadA,loadB,writeAC wrb ; DIVI : AC <- A (quotient)
aA,mM,aluDIVFIXUP,loadA,loadB,loadM divm ; DIVM : move quotient to M
aA,mM,aluDIVFIXUP,loadA,loadB,loadM divb ; DIVB : move quotient to M
;;; 0360
;; write to memory for IDIVM and DIVM
divm1: brWRITE .
aPCnext,aluSETA,loadPC,readMEM,memIF fetchI
halt
divm: aE,mM,aluSETM,writeMEM,memD1,brWRITE divm1
;; write to memory for IDIVB and DIVB
divb1: brWRITE .
mM,aluSETM,writeAC wrb ; AC <- quotient
halt
divb: aE,mM,aluSETM,writeMEM,memD1,brWRITE divb1
;;; 0370
;; EA Calculation for Byte instructions
byteEA: aX,readMEM,memE2 readXBP ; Index
aE,readMEM,memE2 readIBP ; Indirect
aE,readMEM,memD2 bpREAD ; EAcalc done, read in byte
halt
;; do the read for an Indirect and loop back to byteEA
readIBP: mMEM,aluSETM,loadIX,loadY,brREAD .
byteEAx: brIX byteEA
;; Read Index Register for Byte Instructions
readXBP: aE,mMEM,aluADD,loadY,brREAD . ; E <- E+(X)
brI checkIBP
;;; 0400
;; If there was a Index, now check if there's an Indirect too
checkIBP: aE,readMEM,memD2 bpREAD ; EAcalc done, read in byte
aE,readMEM,memE2 readIBP ; start the read for the Indirect
halt
halt
;; finish writing the incremented Byte Pointer back to memory
wrBP: brWRITE .
mM,aluSETM,setFPD,loadBP,loadIX,loadY byteEAx ; First-Part done, now BP EA calc
halt
ldb: aBPMASK,mM,aluAND,writeAC next ; AC <- M & BPmask
;;; 0410
bpREAD: mMEM,aluSETM,loadM,brREAD . ; store the byte word in M
brBPDISP bpdisp
halt
halt
bpdisp: aM,mBPPNEG,aluLSH,loadM,clrFPD ldb ; ILDB : M <- M >> P
aM,mBPPNEG,aluLSH,loadM ldb ; LDB : M <- M >> P
aBPMASK,mBPP,aluLSH,loadB idpb1 ; IDPB : B <- BPmask << P
aBPMASK,mBPP,aluLSH,loadB dpb1 ; DPB : B <- BPmask << P
;;; 0420
;; Finish up DPB
dpbwr: brWRITE .
aPCnext,loadPC,readMEM,memIF fetchI
halt
dpb1: aAC,mBPP,aluLSH,loadA dpb2 ; A <- AC << P
dpb2: aA,mM,aluDPB,loadM dpb3 ; M <- A | M (masked by B)
dpb3: aE,mM,aluSETM,writeMEM,memD2,brWRITE dpbwr ; C(E) <- M
halt
halt
;;; 0430
;; Finish up IDPB. This is identical to DPB except for clearing FPD at the end
idpbwr: brWRITE .
clrFPD,aPCnext,loadPC,readMEM,memIF fetchI ; clear FPD and done
halt
idpb1: aAC,mBPP,aluLSH,loadA idpb2 ; A <- AC << P
idpb2: aA,mM,aluDPB,loadM idpb3 ; M <- A | M (masked by B)
idpb3: aE,mM,aluSETM,writeMEM,memD2,brWRITE idpbwr ; C(E) <- M
;; Either ILDP or IDPB, skip incrementing the byte pointer if FPD is set
fpd: aE,mM,aluIBP,loadM,writeMEM,memD1,brWRITE wrBP
mM,aluSETM,setFPD,loadBP,loadIX,loadY byteEAx ; First-Part done, now BP EA calc
;;; 0440
;; Read from AC left for BLT
;; Might be able to speed up BLT by making brBLTDONE into a 3-way branch that
;; combines brWRITE and brBLTDONE !!!
bltrd: mMEM,aluSETM,loadM,brREAD .
aAC,mM,aluSETM,writeMEM,memD1,brWRITE bltwr ; start write.
bltwr: brWRITE .
brBLTDONE bltfin
;; check if we're done with the BLT (if the last write was to E)
bltfin: mAC,aluAOB,writeAC blt
aPCnext,aluSETA,loadPC,readMEM,memIF fetchI
;; start the BLT read here
bltst: aA,readMEM,memD2 bltrd ; BLT : start read from AC left
halt
;;; 0450
halt
halt
halt
halt
;; Write the JFFO result into AC+1 and either jump or not
jffo: aPCnext,mM,aluSETM,ACnext,writeAC,loadPC,readMEM,memIF fetchI
mM,aluSETM,ACnext,writeAC jumpe
halt
halt
;;; 0460
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0470
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0500
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0510
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0520
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0530
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0540
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0550
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0560
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0570
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0600
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0610
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0620
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0630
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0640
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0650
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0660
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0670
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0700
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0710
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0720
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0730
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0740
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0750
halt
halt
halt
halt
halt
halt
halt
halt
;;; 0760
;; Read the trap instruction for a UUO
uuord: mMEM,aluSETM,saveFLAGS,loadOPA,loadIX,loadY,loadM,brREAD .
brIX calcEA ; execute the instruction
halt
halt
;; write the faulting instruction into memory
uuowr: brWRITE .
aONE,mM,aluADD,loadM uuofetch ; increment the address in M
halt
uuofetch: aM,readMEM,memD1 uuord ; start reading the trap instruction
;;; 0770
halt
UUO: aVECTOR,aluSETA,loadM uuo1 ; move the trap address into M
uuo1: aM,mINST,aluSETM,writeMEM,memD1,brWRITE uuowr ; start the write
MUUO: setMUUO UUO
unass: setMUUO UUO ; unassigned code - same as MUUO for now
;; This Page Fault handler address is known to the micro-engine. Don't move this
;; without changing the other.
FAULT: jump fetch
;; This interrupt handler is as an address known by the micro-engine. Don't
;; change one without changing the other. It spends a cycle, saving the vector in
;; A, to let the memory read where this interrupt was recognized clear before
;; trying to read the interrupt vector.
int1: aA,readMEM,memIF fetchI
INTRPT: aVECTOR,aluSETA,loadA int1
;;; 1000
;; The instruction dispatch table starts here
dispatch: jump MUUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
;;; 1010
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
;;; 1020
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
;;; 1030
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
jump UUO
;;; 1040
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
;;; 1050
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
;;; 1060
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
;;; 1070
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
jump MUUO
;;; 1100
jump unass ; UJEN
jump unass ; UNK101
jump unass ; GFAD
jump unass ; GFSB
jump unass ; JSYS
jump unass ; ADJSP
jump unass ; GFMP
jump unass ; GFDV
;;; 1110
jump unass ; DFAD
jump unass ; DFSB
jump unass ; DFMP
jump unass ; DFDV
jump unass ; DADD
jump unass ; DSUB
jump unass ; DMUL
jump unass ; DDIV
;;; 1120
jump unass ; DMOVE
jump unass ; DMOVN
jump unass ; FIX
jump unass ; EXTEND
jump unass ; DMOVEM
jump unass ; DMOVNM
jump unass ; FIXR
jump unass ; FLTR
;;; 1130
jump unass ; UFA
jump unass ; DFN
jump unass ; FSC
;; The Byte Instructions
aE,mM,aluIBP,loadM,writeMEM,memD1,brWRITE wrmem1 ; IBP - Do I need to clearFPD here !!!
brFPD fpd ; ILDB - Could make the FPD check part of DISPATCH !!!
mM,aluSETM,loadBP,loadIX,loadY byteEAx ; LDB - move M over to BP, I, X, and Y
brFPD fpd ; IDBP - Could make the FPD check part of DISPATCH !!!
mM,aluSETM,loadBP,loadIX,loadY byteEAx ; DPB - move M over to BP, I, X, and Y
;;; 1140
jump unass ; FAD
jump unass ; FADL
jump unass ; FADM
jump unass ; FADB
jump unass ; FADR
jump unass ; FADRL
jump unass ; FADRM
jump unass ; FADRB
;;; 1150
jump unass ; FSB
jump unass ; FSBL
jump unass ; FSBM
jump unass ; FSBB
jump unass ; FSBR
jump unass ; FSBRL
jump unass ; FSBRM
jump unass ; FSBRB
;;; 1160
jump unass ; FMP
jump unass ; FMPL
jump unass ; FMPM
jump unass ; FMPB
jump unass ; FMPR
jump unass ; FMPRL
jump unass ; FMPRM
jump unass ; FMPRB
;;; 1170
jump unass ; FDV
jump unass ; FDVL
jump unass ; FDVM
jump unass ; FDVB
jump unass ; FDVR
jump unass ; FDVRL
jump unass ; FDVRM
jump unass ; FDVRB
;;; 1200
aPCnext,mM,aluSETM,writeAC,loadPC,readMEM,memIF fetchI ; MOVE - AC <- C(E)
aPCnext,mE,aluSETM,writeAC,loadPC,readMEM,memIF fetchI ; MOVEI - AC <- 0,E
aE,mAC,aluSETM,loadM,writeMEM,memD1,brWRITE wrmem1 ; MOVEM - C(E) <- AC
aE,mM,aluSETM,writeMEM,memD1,brWRITE wrself1 ; MOVES - C(E) and AC (if not 0) <- C(E)
aPCnext,mM,swapM,aluSETM,writeAC,loadPC,readMEM,memIF fetchI ; MOVS - AC <- swap(C(E))
aPCnext,mE,swapM,aluSETM,writeAC,loadPC,readMEM,memIF fetchI ; MOVSI - AC <- E,0
aE,mAC,swapM,aluSETM,loadM,writeMEM,memD1,brWRITE wrmem1 ; MOVSM - C(E) <- swap(AC)
aE,mM,swapM,aluSETM,loadM,writeMEM,memD1,brWRITE wrself1 ; MOVSS - C(E) and AC (if not 0) <- swap(C(E))
;;; 1210
aPCnext,mM,aluNEGATE,saveFLAGS,setFLAGS,writeAC,loadPC,readMEM,memIF fetchI ; MOVN - AC <- C(E)
aPCnext,mE,aluNEGATE,saveFLAGS,setFLAGS,writeAC,loadPC,readMEM,memIF fetchI ; MOVNI - AC <- 0,E
aE,mAC,aluNEGATE,saveFLAGS,loadM,writeMEM,memD1,brWRITE wrmem1 ; MOVNM - C(E) <- AC
aE,mM,aluNEGATE,saveFLAGS,loadM,writeMEM,memD1,brWRITE wrself1 ; MOVNS - C(E) and AC (if not 0) <- C(E)
aPCnext,mM,aluMAGNITUDE,saveFLAGS,setFLAGS,writeAC,loadPC,readMEM,memIF fetchI ; MOVM - AC <- C(E)
aPCnext,mE,aluMAGNITUDE,saveFLAGS,setFLAGS,writeAC,loadPC,readMEM,memIF fetchI ; MOVMI - AC <- 0,E
aE,mAC,aluMAGNITUDE,saveFLAGS,loadM,writeMEM,memD1,brWRITE wrmem1 ; MOVMM - C(E) <- AC
aE,mM,aluMAGNITUDE,saveFLAGS,loadM,writeMEM,memD1,brWRITE wrself1 ; MOVMS - C(E) and AC (if not 0) <- C(E)
;;; 1220
imul: aAC,aluSETB,loadB,mulstart mul0 ; IMUL : move AC to B, mulstart also clears A
mE,aluSETM,loadM imul ; IMULI : move E into M and then proceed as MUL
;; the same as IMUL until it's time to write the answer
aAC,aluSETB,loadB,mulstart mul0 ; IMULM
aAC,aluSETB,loadB,mulstart mul0 ; IMULB
mul: aAC,aluSETB,loadB,mulstart mul0 ; MUL : move AC to B, mulstart also clears A
mE,aluSETM,loadM mul ; MULI : move E into M and then proceed as MUL
;; the same as IMUL until it's time to write the answer
aAC,aluSETB,loadB,mulstart mul0 ; MULM
aAC,aluSETB,loadB,mulstart mul0 ; MULB
;;; 1230
idiv: aAC,aluDIVMAG36,loadA,loadB div00 ; IDIV : A,B <- |AC| << 1
mE,aluSETM,loadM idiv ; IDIVI : move E to M
;; the same as IDIV until it's time to write the answer
aAC,aluDIVMAG36,loadA,loadB div00 ; IDIVM
aAC,aluDIVMAG36,loadA,loadB div00 ; IDIVB
div: aAC,ACnext,aluSETB,loadB divhi ; DIV : B <- AC+1
mE,aluSETM,loadM div ; DIVI : move E to M
;; the same as DIV until it's time to write the answer
aAC,ACnext,aluSETB,loadB divhi ; DIVM : B <- AC+1
aAC,ACnext,aluSETB,loadB divhi ; DIVB : B <- AC+1
;;; 1240
aAC,mE,aluASH,saveFLAGS,setFLAGS,writeAC next ; ASH
aAC,mE,aluROT,writeAC next ; ROT
aAC,mE,aluLSH,writeAC next ; LSH
mAC,aluJFFO,loadM,brOVR jffo ; JFFO : M <- JFFO(AC)
aAC,ACnext,aluSETB,loadB ashc ; ASHC
aAC,ACnext,aluSETB,loadB rotc ; ROTC
aAC,ACnext,aluSETB,loadB lshc ; LSHC
jump unass ; CIRC
;;; 1250
aE,mAC,aluSETM,writeMEM,memD1,brWRITE exch ; EXCH : start writing AC here
blt: mAC,swapM,aluSETM,loadA bltst ; BLT : move LEFT(AC) to A
mAC,aluAOB,writeAC,loadM,brCOMP0 jumpc ; AOBJP
mAC,aluAOB,writeAC,loadM,brCOMP0 jumpc ; AOBJN
;; Most of the JRST variants are dispatched to 1720. If the
;; instruction is disallowed, it comes here for the MUUO.
jump MUUO
clrFLAGS,brJFCL jfcl ; JFCL
;; If we need to read the instruction with memIF, will have to change this as
;; well as changing the entry in decode.v !!!
aE,mM,aluSETM,saveFLAGS,loadOPA,loadIX,loadY strtEA ; XCT
jump unass ; MAP
;;; 1260
aPCnext,aluSETA,loadM pushj ; PUSHJ
mAC,aluAOB,loadA,setPDO push ; PUSH
aAC,readMEM,memD1 pop ; POP
aAC,readMEM,memD1 popj ; POPJ
aPCnext,aluSETA,loadM jsr ; JSR : C(E) <- PSW,PC, jump E+1
aPCnext,aluSETA,writeAC,clrFPD jumpe ; JSP : AC <- PSW,PC, jump E
aE,mAC,aluSETM,writeMEM,memD1,brWRITE jsa ; JSA : C(E) <- AC, AC <- E,PC, jump E+1
mAC,swapM,aluSETM,loadA jra ; JRA : AC <- C(LEFT(AC)), jump E
;;; 1270
aAC,mM,aluADD,saveFLAGS,setFLAGS,writeAC next ; ADD
aAC,mE,aluADD,saveFLAGS,setFLAGS,writeAC next ; ADDI
aAC,mM,aluADD,saveFLAGS,loadM wrmem ; ADDM
aAC,mM,aluADD,saveFLAGS,loadM wrboth ; ADDB
aAC,mM,aluSUB,saveFLAGS,setFLAGS,writeAC next ; SUB
aAC,mE,aluSUB,saveFLAGS,setFLAGS,writeAC next ; SUBI
aAC,mM,aluSUB,saveFLAGS,loadM wrmem ; SUBM
aAC,mM,aluSUB,saveFLAGS,loadM wrboth ; SUBB
;;; 1300
;; Compare AC with 0,E and Skip
aAC,mE,aluSUB,brCOMP skipc ; CAI -- could optimize!!!
aAC,mE,aluSUB,brCOMP skipc ; CAIL
aAC,mE,aluSUB,brCOMP skipc ; CAIE
aAC,mE,aluSUB,brCOMP skipc ; CAILE
aAC,mE,aluSUB,brCOMP skipc ; CAIA -- could optimize!!!
aAC,mE,aluSUB,brCOMP skipc ; CAIGE
aAC,mE,aluSUB,brCOMP skipc ; CAIN
aAC,mE,aluSUB,brCOMP skipc ; CAIG
;;; 1310
;; Compare AC with Memory and Skip
aAC,mM,aluSUB,brCOMP skipc ; CAM -- could optimize!!!
aAC,mM,aluSUB,brCOMP skipc ; CAML
aAC,mM,aluSUB,brCOMP skipc ; CAME
aAC,mM,aluSUB,brCOMP skipc ; CAMLE
aAC,mM,aluSUB,brCOMP skipc ; CAMA -- could optimize!!!
aAC,mM,aluSUB,brCOMP skipc ; CAMGE
aAC,mM,aluSUB,brCOMP skipc ; CAMN
aAC,mM,aluSUB,brCOMP skipc ; CAMG
;;; 1320
;; Compare AC with 0 and Jump
mAC,aluSETM,brCOMP0 jumpc ; JUMP -- could optimize!!!
mAC,aluSETM,brCOMP0 jumpc ; JUMPL
mAC,aluSETM,brCOMP0 jumpc ; JUMPE
mAC,aluSETM,brCOMP0 jumpc ; JUMPLE
mAC,aluSETM,brCOMP0 jumpc ; JUMPA -- could optimize!!!
mAC,aluSETM,brCOMP0 jumpc ; JUMPGE
mAC,aluSETM,brCOMP0 jumpc ; JUMPN
mAC,aluSETM,brCOMP0 jumpc ; JUMPG
;;; 1330
;; Compare Memory wih 0 and Skip, write Memory to AC if AC not 0
brSELF wrskip ; SKIP
brSELF wrskip ; SKIPL
brSELF wrskip ; SKIPE
brSELF wrskip ; SKIPLE
brSELF wrskip ; SKIPA
brSELF wrskip ; SKIPGE
brSELF wrskip ; SKIPN
brSELF wrskip ; SKIPG
;;; 1340
;; Add 1 to AC and Jump
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJ
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJL
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJE
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJLE
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJA
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJGE
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJN
aONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; AOJG
;;; 1350
;; Add 1 to Memory and Skip, write back to Memory and also AC if AC not 0
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOS
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSL
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSE
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSLE
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSA
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSGE
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSN
aONE,mM,aluADD,saveFLAGS,loadM sosWR ; AOSG
;;; 1360
;; Subtract 1 from AC and Jump
;; Adding -1 makes the condition codes come out right
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJ
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJL
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJE
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJLE
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJA
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJGE
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJN
aMONE,mAC,aluADD,saveFLAGS,setFLAGS,writeAC,brCOMP0 jumpc ; SOJG
;;; 1370
;; Subtract 1 from Memory and Skip, write back to Memory and also AC if AC not 0
;; Adding -1 makes the condition codes come out right
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOS
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSL
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSE
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSLE
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSA
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSGE
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSN
aMONE,mM,aluADD,saveFLAGS,loadM sosWR ; SOSG
;;; 1400
;; The logic instructions
aAC,mM,aluSETZ,writeAC next ; SETZ
aAC,mE,aluSETZ,writeAC next ; SETZI
aAC,mM,aluSETZ,loadM wrmem ; SETZM
aAC,mM,aluSETZ,loadM wrboth ; SETZB
aAC,mM,aluAND,writeAC next ; AND
aAC,mE,aluAND,writeAC next ; ANDI
aAC,mM,aluAND,loadM wrmem ; ANDM
aAC,mM,aluAND,loadM wrboth ; ANDB
;;; 1410
aAC,mM,aluANDCA,writeAC next ; ANDCA
aAC,mE,aluANDCA,writeAC next ; ANDCAI
aAC,mM,aluANDCA,loadM wrmem ; ANDCAM
aAC,mM,aluANDCA,loadM wrboth ; ANDCAB
aAC,mM,aluSETM,writeAC next ; SETM
aAC,mE,aluSETM,writeAC next ; SETMI
aAC,mM,aluSETM,loadM wrmem ; SETMM
aAC,mM,aluSETM,loadM wrboth ; SETMB
;;; 1420
aAC,mM,aluANDCM,writeAC next ; ANDCM
aAC,mE,aluANDCM,writeAC next ; ANDCMI
aAC,mM,aluANDCM,loadM wrmem ; ANDCMM
aAC,mM,aluANDCM,loadM wrboth ; ANDCMB
aAC,mM,aluSETA,writeAC next ; SETA
aAC,mE,aluSETA,writeAC next ; SETAI
aAC,mM,aluSETA,loadM wrmem ; SETAM
aAC,mM,aluSETA,loadM wrboth ; SETAB
;;; 1430
aAC,mM,aluXOR,writeAC next ; XOR
aAC,mE,aluXOR,writeAC next ; XORI
aAC,mM,aluXOR,loadM wrmem ; XORM
aAC,mM,aluXOR,loadM wrboth ; XORB
aAC,mM,aluIOR,writeAC next ; IOR