From 828d72b263a2e62431b317d155d5347d1112e623 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 14 Oct 2024 09:59:26 +0100 Subject: [PATCH] [GlobalISel] Add an assert for the DemandedElts APInt size. (#112150) Similar to the other implementations in DAG/ValueTracking, this adds an assert that the size of the DemandedElts is what we expect it to be - the size of a fixed length vector or APInt(1,1) otherwise. The G_BUILDVECTOR is fixed as it was passing an original DemandedElts for the scalar operands. --- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp index 35ee85b474d04..52f5d408c8edd 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -148,6 +148,17 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known, unsigned Opcode = MI.getOpcode(); LLT DstTy = MRI.getType(R); +#ifndef NDEBUG + if (DstTy.isFixedVector()) { + assert( + DstTy.getNumElements() == DemandedElts.getBitWidth() && + "DemandedElt width should equal the fixed vector number of elements"); + } else { + assert(DemandedElts.getBitWidth() == 1 && DemandedElts == APInt(1, 1) && + "DemandedElt width should be 1 for scalars or scalable vectors"); + } +#endif + // Handle the case where this is called on a register that does not have a // type constraint (i.e. it has a register class constraint instead). This is // unlikely to occur except by looking through copies but it is possible for @@ -196,7 +207,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known, if (!DemandedElts[i]) continue; - computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, + computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, APInt(1, 1), Depth + 1); // Known bits are the values that are shared by every demanded element.