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devanlaidevanlai
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Add DAP42DC target for Derek's debugger hardware
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Lines changed: 332 additions & 1 deletion

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‎Makefile‎

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@@ -24,7 +24,7 @@ export V
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BUILD_DIR ?= ./build
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all: DAP42.bin KITCHEN42.bin \
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all: DAP42.bin DAP42DC.bin KITCHEN42.bin \
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DAP103.bin DAP103-DFU.bin \
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DAP103-NUCLEO-STBOOT.bin \
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BRAINv3.3.bin \
@@ -44,6 +44,12 @@ DAP42.bin: | $(BUILD_DIR)
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$(Q)$(MAKE) TARGET=STM32F042 -C src/
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$(Q)cp src/DAP42.bin $(BUILD_DIR)/$(@)
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DAP42DC.bin: | $(BUILD_DIR)
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@printf " BUILD $(@)\n"
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$(Q)$(MAKE) TARGET=DAP42DC -C src/ clean
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$(Q)$(MAKE) TARGET=DAP42DC -C src/
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$(Q)cp src/DAP42.bin $(BUILD_DIR)/$(@)
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KITCHEN42.bin: | $(BUILD_DIR)
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@printf " BUILD $(@)\n"
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$(Q)$(MAKE) TARGET=KITCHEN42 -C src/ clean

‎src/stm32f042/dap42dc/DAP/CMSIS_DAP_config.h‎

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/*
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* Copyright (c) 2015, Devan Lai
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*
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* Permission to use, copy, modify, and/or distribute this software
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* for any purpose with or without fee is hereby granted, provided
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* that the above copyright notice and this permission notice
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* appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
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* NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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Portions of this file are derived from:
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Dapper Mime - an open-source CMSIS-DAP implementation
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HAL for STM32F0xx2
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this file is used by the mbed CMSIS-DAP routines
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Copyright (C) 2014 Peter Lawrence
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __DAP_CONFIG_H__
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#define __DAP_CONFIG_H__
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//**************************************************************************************************
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/**
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\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
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\ingroup DAP_ConfigIO_gr
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@{
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Provides definitions about:
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- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
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- Debug Unit communication packet size.
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- Debug Access Port communication mode (JTAG or SWD).
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- Optional information about a connected Target Device (for Evaluation Boards).
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*/
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#include "config.h"
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// Board configuration options
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/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
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/// This value is used to calculate the SWD/JTAG clock speed.
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#define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz
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/// Number of processor cycles for I/O Port write operations.
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/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
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/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
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/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
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/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
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/// required.
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#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
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/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
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/// Indicate that JTAG communication mode is available at the Debug Port.
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/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
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#if defined(CONF_JTAG)
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#define DAP_JTAG 1 ///< JTAG Mode: 1 = available
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#else
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#define DAP_JTAG 0 ///< JTAG Mode: 0 = not available
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#endif
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/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
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/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
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#define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
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/// Default communication mode on the Debug Access Port.
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/// Used for the command \ref DAP_Connect when Port Default mode is selected.
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#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
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/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
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/// Used to initialize the default SWD/JTAG clock frequency.
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/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
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#define DAP_DEFAULT_SWJ_CLOCK 10000000 ///< Default SWD/JTAG clock frequency in Hz.
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/// Maximum Package Size for Command and Response data.
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/// This configuration settings is used to optimized the communication performance with the
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/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
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#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
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/// Maximum Package Buffers for Command and Response data.
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/// This configuration settings is used to optimized the communication performance with the
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/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
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/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
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#define DAP_PACKET_COUNT 12 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
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#define DAP_PACKET_QUEUE_SIZE (DAP_PACKET_COUNT+8)
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/// Debug Unit is connected to fixed Target Device.
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/// The Debug Unit may be part of an evaluation board and always connected to a fixed
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/// known device. In this case a Device Vendor and Device Name string is stored which
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/// may be used by the debugger or IDE to configure device parameters.
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#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
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#if TARGET_DEVICE_FIXED
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#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
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#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
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#endif
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///@}
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#define SWCLK_GPIO_PORT GPIOA
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#define SWCLK_GPIO_PIN GPIO1
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#define SWDIO_GPIO_PORT GPIOA
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#define SWDIO_GPIO_PIN GPIO0
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#define nRESET_GPIO_PORT GPIOA
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#define nRESET_GPIO_PIN GPIO4
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#define LED_CON_GPIO_PORT GPIOA
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#define LED_CON_GPIO_PIN GPIO5
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#define LED_RUN_GPIO_PORT GPIOA
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#define LED_RUN_GPIO_PIN GPIO6
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#define LED_ACT_GPIO_PORT GPIOA
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#define LED_ACT_GPIO_PIN GPIO7
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#define SWDIO_GPIO_PIN_NUM 0
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#endif

‎src/stm32f042/dap42dc/config.h‎

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/*
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* Copyright (c) 2016, Devan Lai
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*
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* Permission to use, copy, modify, and/or distribute this software
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* for any purpose with or without fee is hereby granted, provided
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* that the above copyright notice and this permission notice
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* appear in all copies.
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*
9+
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
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* NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef CONFIG_H_INCLUDED
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#define CONFIG_H_INCLUDED
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#define PRODUCT_NAME "DAP42dc"
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#define REMAP_USB 1
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#define CAN_RX_AVAILABLE 1
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#define CAN_TX_AVAILABLE 0
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#define CAN_NVIC_LINE NVIC_CEC_CAN_IRQ
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#define VCDC_AVAILABLE 0
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#define VCDC_TX_BUFFER_SIZE 256
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#define VCDC_RX_BUFFER_SIZE 256
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#define CDC_AVAILABLE 1
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#define DEFAULT_BAUDRATE 115200
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#define CONSOLE_USART USART2
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#define CONSOLE_TX_BUFFER_SIZE 128
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#define CONSOLE_RX_BUFFER_SIZE 1024
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#define CONSOLE_USART_GPIO_PORT GPIOA
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#define CONSOLE_USART_GPIO_PINS (GPIO2|GPIO3)
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#define CONSOLE_USART_GPIO_AF GPIO_AF1
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#define CONSOLE_USART_MODE USART_MODE_TX_RX
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#define CONSOLE_USART_CLOCK RCC_USART2
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#define CONSOLE_USART_IRQ_NAME usart2_isr
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#define CONSOLE_USART_NVIC_LINE NVIC_USART2_IRQ
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#define CONSOLE_RX_DMA_CONTROLLER DMA1
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#define CONSOLE_RX_DMA_CLOCK RCC_DMA
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#define CONSOLE_RX_DMA_CHANNEL DMA_CHANNEL5
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#define DFU_AVAILABLE 1
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#define nBOOT0_GPIO_CLOCK RCC_GPIOB
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#define nBOOT0_GPIO_PORT GPIOB
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#define nBOOT0_GPIO_PIN GPIO8
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/* Word size for usart_recv and usart_send */
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typedef uint8_t usart_word_t;
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#define LED_OPEN_DRAIN 1
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#endif

‎src/stm32f042/dap42dc/target.c‎

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/*
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* Copyright (c) 2016, Devan Lai
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*
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* Permission to use, copy, modify, and/or distribute this software
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* for any purpose with or without fee is hereby granted, provided
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* that the above copyright notice and this permission notice
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* appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11+
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
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* NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/crs.h>
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#include <libopencm3/stm32/gpio.h>
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#include "target.h"
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#include "config.h"
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/* Reconfigure processor settings */
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void cpu_setup(void) {
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}
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/* Set STM32 to 48 MHz. */
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void clock_setup(void) {
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rcc_clock_setup_in_hsi48_out_48mhz();
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// Trim from USB sync frame
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crs_autotrim_usb_enable();
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rcc_set_usbclk_source(RCC_HSI48);
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}
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static void button_setup(void) {
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/* Enable GPIOB clock. */
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rcc_periph_clock_enable(RCC_GPIOB);
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/* Set PB8 to an input */
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gpio_mode_setup(GPIOB, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO8);
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}
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void gpio_setup(void) {
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/*
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LED0 (R), 1 (G), 2 (B) on PA5, PA6, PA7, open drain
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TX, RX (MCU-side) on PA2, PA3
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TGT_RST on PA4
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TGT_SWDIO, TGT_SWCLK on PA0, PA1
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*/
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/* Enable GPIOA and GPIOB clocks. */
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rcc_periph_clock_enable(RCC_GPIOA);
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/* Setup LEDs as open-drain outputs */
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gpio_set_output_options(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_LOW,
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GPIO5 | GPIO6 | GPIO7);
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gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,
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GPIO5 | GPIO6 | GPIO7);
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button_setup();
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}
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void target_console_init(void) {
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/* Enable UART clock */
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rcc_periph_clock_enable(CONSOLE_USART_CLOCK);
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/* Setup GPIO pins for UART2 */
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gpio_mode_setup(CONSOLE_USART_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, CONSOLE_USART_GPIO_PINS);
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gpio_set_af(CONSOLE_USART_GPIO_PORT, CONSOLE_USART_GPIO_AF, CONSOLE_USART_GPIO_PINS);
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}
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void led_bit(uint8_t position, bool state) {
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uint32_t gpio = 0xFFFFFFFFU;
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if (position == 0) {
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gpio = GPIO5;
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} else if (position == 1) {
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gpio = GPIO6;
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} else if (position == 2) {
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gpio = GPIO7;
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}
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if (gpio != 0xFFFFFFFFU) {
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if (state) {
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gpio_clear(GPIOA, gpio);
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} else {
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gpio_set(GPIOA, gpio);
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}
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}
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}
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void led_num(uint8_t value) {
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if (value & 0x4) {
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gpio_clear(GPIOA, GPIO5);
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} else {
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gpio_set(GPIOA, GPIO5);
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}
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if (value & 0x2) {
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gpio_clear(GPIOA, GPIO6);
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} else {
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gpio_set(GPIOA, GPIO6);
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}
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if (value & 0x1) {
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gpio_clear(GPIOA, GPIO7);
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} else {
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gpio_set(GPIOA, GPIO7);
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}
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}

‎src/targets.mk‎

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LDSCRIPT ?= ./stm32f042/stm32f042x6.ld
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ARCH = STM32F0
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endif
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ifeq ($(TARGET),DAP42DC)
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TARGET_COMMON_DIR := ./stm32f042
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TARGET_SPEC_DIR := ./stm32f042/dap42dc
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LDSCRIPT ?= ./stm32f042/stm32f042x6.ld
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ARCH = STM32F0
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endif
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ifeq ($(TARGET),STM32F103)
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TARGET_COMMON_DIR := ./stm32f103
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TARGET_SPEC_DIR := ./stm32f103/stlinkv2-dongle

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