Verilog: KNOWNBUG test for port connection that has typedef name

Author: kroening

regression/verilog/modules/port_connection1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+port_connection1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.

regression/verilog/modules/port_connection1.sv

@@ -0,0 +1,16 @@
+module M(input [31:0] some_name);
+
+  initial assert (some_name == 123);
+
+endmodule
+
+module main;
+
+  // typedef with the same name as a port
+  typedef bit [31:0] some_name;
+
+  // This fails to parse with Icarus Verilog,
+  // but works with VCS, Questa, Xcelium, Riviera
+  M my_instance(.some_name(123));
+
+endmodule