Skip to content

Commit 5906108

Browse files
authored
Merge pull request #1131 from diffblue/buechi-sva-s_always
SVA-to-Buechi: `s_always`
2 parents e565db7 + 4352610 commit 5906108

File tree

6 files changed

+63
-1
lines changed

6 files changed

+63
-1
lines changed
Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
CORE
2+
../../verilog/SVA/nexttime1.sv
3+
--buechi --bdd
4+
^\[main\.p1\] s_nexttime\[0\] main\.counter == 0: PROVED$
5+
^\[main\.p2\] s_nexttime\[1\] main\.counter == 1: PROVED$
6+
^\[main\.p3\] nexttime\[8\] main\.counter == 8: PROVED$
7+
^EXIT=0$
8+
^SIGNAL=0$
9+
--
10+
^warning: ignoring
11+
--
Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
CORE
2+
../../verilog/SVA/nexttime1.sv
3+
--buechi --module main --bound 10
4+
^\[main\.p1\] s_nexttime\[0\] main\.counter == 0: PROVED up to bound 10$
5+
^\[main\.p2\] s_nexttime\[1\] main\.counter == 1: PROVED up to bound 10$
6+
^\[main\.p3\] nexttime\[8\] main\.counter == 8: PROVED up to bound 10$
7+
^EXIT=0$
8+
^SIGNAL=0$
9+
--
10+
^warning: ignoring
11+
--
12+
Backend support missing.
Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
KNOWNBUG
2+
../../verilog/SVA/s_always1.sv
3+
--buechi --bound 20
4+
^\[main\.p0\] s_always \[0:9\] main\.x < 10: PROVED up to bound 20$
5+
^\[main\.p1\] not \(s_always \[0:9\] main\.x < 10\): REFUTED$
6+
^EXIT=10$
7+
^SIGNAL=0$
8+
--
9+
^warning: ignoring
10+
--
11+
main.p1 is not refuted.
Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
CORE
2+
../../verilog/SVA/sva_iff2.sv
3+
--buechi --bound 10
4+
^EXIT=0$
5+
^SIGNAL=0$
6+
--
7+
^warning: ignoring
8+
--
Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
CORE
2+
../../verilog/SVA/sva_implies2.sv
3+
--buechi --bound 2
4+
^EXIT=0$
5+
^SIGNAL=0$
6+
--
7+
^warning: ignoring
8+
--

src/temporal-logic/ltl_sva_to_string.cpp

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,19 @@ ltl_sva_to_stringt::rec(const exprt &expr, modet mode)
177177
}
178178
else if(expr.id() == ID_sva_s_always)
179179
{
180-
throw ebmc_errort{} << "cannot convert " << expr.id() << " to Buechi";
180+
auto &always = to_sva_s_always_expr(expr);
181+
auto new_expr = unary_exprt{ID_sva_s_always, always.op()};
182+
auto from = numeric_cast_v<mp_integer>(always.from());
183+
if(!always.is_range())
184+
return prefix("G[" + integer2string(from) + "]", new_expr, mode);
185+
else
186+
{
187+
auto to = numeric_cast_v<mp_integer>(always.to());
188+
return prefix(
189+
"G[" + integer2string(from) + ":" + integer2string(to) + "]",
190+
new_expr,
191+
mode);
192+
}
181193
}
182194
else if(expr.id() == ID_sva_s_eventually)
183195
{

0 commit comments

Comments
 (0)