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+ CORE
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+ followed-by4.sv
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+ --bound 3
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+ ^\[main\.p1\] always \(main\.x == 0 #-# 1\): REFUTED$
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+ ^\[main\.p2\] \(1 or \(##2 1\)\) #-# main\.x == 2: PROVED up to bound 3$
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+ ^\[main\.p3\] \(1 or \(##2 1\)\) #-# main\.x == 0: PROVED up to bound 3$
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+ ^EXIT=10$
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+ ^SIGNAL=0$
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+ --
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+ ^warning: ignoring
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+ --
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+ module main (input clk);
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+
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+ reg [31 : 0 ] x;
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+
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+ initial x= 0 ;
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+
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+ // 0, 1, ...
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+ always @ (posedge clk)
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+ x<= x+ 1 ;
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+
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+ // fails in the 2nd timeframe since the LHS doesn't match
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+ p1 : assert property (x== 0 # - # 1 );
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+
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+ // the RHS only needs to hold from _any one_ of the LHS matches,
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+ // not all
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+ initial p2 : assert property ((1 or ## 2 1 ) # - # x== 2 );
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+ initial p3 : assert property ((1 or ## 2 1 ) # - # x== 0 );
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+
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+ endmodule
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