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Merge pull request #1129 from diffblue/more-buechi
SVA-to-Buechi: `#-#` and `#=#`
2 parents fcde983 + 6d6ca0c commit e3179b5

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+98
-4
lines changed

8 files changed

+98
-4
lines changed
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CORE
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../../verilog/SVA/followed-by1.sv
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--buechi --bdd
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^\[main\.p0\] main\.x == 0 #=# \(main\.x == 1 #=# main\.x == 2\): PROVED$
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^\[main\.p1\] main\.x == 0 #-# \(\(##1 main\.x == 1\) #-# \(##1 main\.x == 2\)\): PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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../../verilog/SVA/followed-by1.sv
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--buechi --bound 20 --numbered-trace
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^\[main\.p0\] main\.x == 0 #=# \(main\.x == 1 #=# main\.x == 2\): PROVED up to bound 20$
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^\[main\.p1\] main\.x == 0 #-# \(\(##1 main\.x == 1\) #-# \(##1 main\.x == 2\)\): PROVED up to bound 20$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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../../verilog/SVA/followed-by2.sv
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--buechi --bdd
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^\[main\.p0\] always \(\(main\.a #-# main\.b\) iff \(not \(main\.a |-> \(not main\.b\)\)\)\): PROVED$
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^\[main\.p1\] always \(\(main\.a #=# main\.b\) iff \(not \(main\.a |=> \(not main\.b\)\)\)\): PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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../../verilog/SVA/followed-by2.sv
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--buechi --bound 20
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^\[main\.p0\] always \(\(main\.a #-# main\.b\) iff \(not \(main\.a |-> \(not main\.b\)\)\)\): PROVED up to bound 20$
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^\[main\.p1\] always \(\(main\.a #=# main\.b\) iff \(not \(main\.a |=> \(not main\.b\)\)\)\): PROVED up to bound 20$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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../../verilog/SVA/followed-by3.sv
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--buechi --bound 20
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^\[.*\] \(main\.x == 0 ##1 main\.x == 1\) #-# \(s_eventually main\.x == 10\): PROVED up to bound 20$
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^\[.*\] \(main\.x == 0 ##1 main\.x == 1\) #=# \(s_eventually main\.x == 10\): PROVED up to bound 20$
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^\[.*\] \(main\.x == 0 ##1 main\.x == 1\) #-# \(s_eventually main\.x == 2\): PROVED up to bound 20$
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^\[.*\] \(main\.x == 0 ##1 main\.x == 1\) #-# \(s_eventually main\.x == 11\): REFUTED$
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^\[.*\] \(main\.x == 0 ##1 main\.x == 1\) #=# \(s_eventually main\.x == 1\): REFUTED$
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^\[.*\] \(main\.x == 0 ##1 main\.x == 2\) #-# 1: REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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../../verilog/SVA/followed-by4.sv
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--buechi --bdd
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^\[main\.p1\] always \(main\.x == 0 #-# 1\): REFUTED$
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^\[main\.p2\] \(1 or \(##2 1\)\) #-# main\.x == 2: PROVED$
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^\[main\.p3\] \(1 or \(##2 1\)\) #-# main\.x == 0: PROVED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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KNOWNBUG
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../../verilog/SVA/followed-by4.sv
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--buechi --bound 3
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^\[main\.p1\] always \(main\.x == 0 #-# 1\): REFUTED$
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^\[main\.p2\] \(1 or \(##2 1\)\) #-# main\.x == 2: PROVED up to bound 3$
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^\[main\.p3\] \(1 or \(##2 1\)\) #-# main\.x == 0: PROVED up to bound 3$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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p1 is not refuted.

src/temporal-logic/ltl_sva_to_string.cpp

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -233,12 +233,29 @@ ltl_sva_to_stringt::rec(const exprt &expr, modet mode)
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ID_sva_implicit_weak, new_expr.sequence()};
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return infix("|=>", new_expr, mode);
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}
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else if(
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expr.id() == ID_sva_nonoverlapped_followed_by ||
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expr.id() == ID_sva_overlapped_followed_by)
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else if(expr.id() == ID_sva_overlapped_followed_by)
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{
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PRECONDITION(mode == PROPERTY);
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throw ebmc_errort{} << "cannot convert " << expr.id() << " to Buechi";
239+
// 1800 2017 16.12.9
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// (a #-# b) ---> !(a |-> !b)
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auto &followed_by = to_sva_followed_by_expr(expr);
242+
auto not_b = not_exprt{followed_by.consequent()};
243+
return rec(
244+
not_exprt{
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sva_overlapped_implication_exprt{followed_by.antecedent(), not_b}},
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mode);
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}
248+
else if(expr.id() == ID_sva_nonoverlapped_followed_by)
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{
250+
PRECONDITION(mode == PROPERTY);
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// 1800 2017 16.12.9
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// (a #=# b) ---> !(a |=> !b)
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auto &followed_by = to_sva_followed_by_expr(expr);
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auto not_b = not_exprt{followed_by.consequent()};
255+
return rec(
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not_exprt{
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sva_non_overlapped_implication_exprt{followed_by.antecedent(), not_b}},
258+
mode);
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}
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else if(expr.id() == ID_sva_sequence_property)
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{

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