default disable iff is unsupported

Is it still not possible to support this kind of syntax?
```
module main(input clock, reset);

  default clocking cb @(posedge clk);
  endclocking
  default disable iff (!reset);

endmodule
```

```
Parsing main.sv
Converting
Type-checking Verilog::main
file main.sv line 5: default disable iff is unsupported
CONVERSION ERROR
```

Thank you!