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Author: dongchen-yang

correctOutput/alpha/insertsort.txt

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+Student Name:   SOLUTION
+Student ID:     PID
+Student email:  EMAIL
+Simulator Memory Hierarchy:
+  I$ Configuration:
+    Size:  64 KB
+    Sets:  512
+    Assoc: 2
+    Lat:   2 Cycles
+  D$ Configuration:
+    Size:  64 KB
+    Sets:  256
+    Assoc: 4
+    Lat:   2 Cycles
+  L2$ Configuration:
+    Size:  8192 KB
+    Sets:  16384
+    Assoc: 8
+    Lat:   50 Cycles
+    Inclusive: No
+  Block Size: 64 Bytes
+  Memspeed:   100 Cycles
+Cache Statistics:
+  total I-cache accesses:   118797444
+  total I-cache misses:            19
+  total I-cache penalties:       2850
+  I-cache miss rate:                0.00%
+  avg I-cache access time:          2.00 cycles
+  total D-cache accesses:    31237729
+  total D-cache misses:           316
+  total D-cache penalties:      47300
+  D-cache miss rate:                0.00%
+  avg D-cache access time:          2.00 cycles
+  total L2-cache accesses:        335
+  total L2-cache misses:          334
+  total L2-cache penalties:     33400
+  L2-cache miss rate:              99.70%
+  avg L2-cache access time:       149.70 cycles
+Total Memory accesses:  150035173
+Total Memory penalties: 300120496
+avg Memory access time:          2.00 cycles

correctOutput/alpha/mat_20M.txt

@@ -0,0 +1,41 @@
+Student Name:   SOLUTION
+Student ID:     PID
+Student email:  EMAIL
+Simulator Memory Hierarchy:
+  I$ Configuration:
+    Size:  64 KB
+    Sets:  512
+    Assoc: 2
+    Lat:   2 Cycles
+  D$ Configuration:
+    Size:  64 KB
+    Sets:  256
+    Assoc: 4
+    Lat:   2 Cycles
+  L2$ Configuration:
+    Size:  8192 KB
+    Sets:  16384
+    Assoc: 8
+    Lat:   50 Cycles
+    Inclusive: No
+  Block Size: 64 Bytes
+  Memspeed:   100 Cycles
+Cache Statistics:
+  total I-cache accesses:    18398965
+  total I-cache misses:             6
+  total I-cache penalties:        900
+  I-cache miss rate:                0.00%
+  avg I-cache access time:          2.00 cycles
+  total D-cache accesses:     1601035
+  total D-cache misses:         66372
+  total D-cache penalties:    3778400
+  D-cache miss rate:                4.15%
+  avg D-cache access time:          4.36 cycles
+  total L2-cache accesses:      66378
+  total L2-cache misses:         4604
+  total L2-cache penalties:    460400
+  L2-cache miss rate:               6.94%
+  avg L2-cache access time:        56.94 cycles
+Total Memory accesses:  20000000
+Total Memory penalties: 43779300
+avg Memory access time:          2.19 cycles

correctOutput/mips/insertsort.txt

@@ -0,0 +1,41 @@
+Student Name:   SOLUTION
+Student ID:     PID
+Student email:  EMAIL
+Simulator Memory Hierarchy:
+  I$ Configuration:
+    Size:  32 KB
+    Sets:  128
+    Assoc: 2
+    Lat:   2 Cycles
+  D$ Configuration:
+    Size:  32 KB
+    Sets:  64
+    Assoc: 4
+    Lat:   2 Cycles
+  L2$ Configuration:
+    Size:  128 KB
+    Sets:  128
+    Assoc: 8
+    Lat:   50 Cycles
+    Inclusive: No
+  Block Size: 128 Bytes
+  Memspeed:   100 Cycles
+Cache Statistics:
+  total I-cache accesses:   118797444
+  total I-cache misses:            10
+  total I-cache penalties:       1500
+  I-cache miss rate:                0.00%
+  avg I-cache access time:          2.00 cycles
+  total D-cache accesses:    31237729
+  total D-cache misses:           160
+  total D-cache penalties:      23900
+  D-cache miss rate:                0.00%
+  avg D-cache access time:          2.00 cycles
+  total L2-cache accesses:        170
+  total L2-cache misses:          169
+  total L2-cache penalties:     16900
+  L2-cache miss rate:              99.41%
+  avg L2-cache access time:       149.41 cycles
+Total Memory accesses:  150035173
+Total Memory penalties: 300095746
+avg Memory access time:          2.00 cycles

correctOutput/mips/mat_20M.txt

@@ -0,0 +1,41 @@
+Student Name:   SOLUTION
+Student ID:     PID
+Student email:  EMAIL
+Simulator Memory Hierarchy:
+  I$ Configuration:
+    Size:  32 KB
+    Sets:  128
+    Assoc: 2
+    Lat:   2 Cycles
+  D$ Configuration:
+    Size:  32 KB
+    Sets:  64
+    Assoc: 4
+    Lat:   2 Cycles
+  L2$ Configuration:
+    Size:  128 KB
+    Sets:  128
+    Assoc: 8
+    Lat:   50 Cycles
+    Inclusive: No
+  Block Size: 128 Bytes
+  Memspeed:   100 Cycles
+Cache Statistics:
+  total I-cache accesses:    18398965
+  total I-cache misses:             4
+  total I-cache penalties:        600
+  I-cache miss rate:                0.00%
+  avg I-cache access time:          2.00 cycles
+  total D-cache accesses:     1601035
+  total D-cache misses:         59179
+  total D-cache penalties:    6300350
+  D-cache miss rate:                3.70%
+  avg D-cache access time:          5.94 cycles
+  total L2-cache accesses:      59183
+  total L2-cache misses:        33418
+  total L2-cache penalties:   3341800
+  L2-cache miss rate:              56.47%
+  avg L2-cache access time:       106.47 cycles
+Total Memory accesses:  20000000
+Total Memory penalties: 46300950
+avg Memory access time:          2.32 cycles