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chore: refactor ValueAccumukator logics
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‎src/BenchmarkDotNet/Disassemblers/Arm64InstructionExtensions.cs‎

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using AsmArm64;
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using Gee.External.Capstone.Arm64;
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using System.Buffers.Binary;
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using System.Diagnostics;
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using System.Diagnostics.CodeAnalysis;
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using AsmArm64Instruction = AsmArm64.Arm64Instruction;
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using AsmArm64Operand = AsmArm64.Arm64Operand;
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using Arm64InstructionId = AsmArm64.Arm64InstructionId;
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using CapstoneArm64Instruction = Gee.External.Capstone.Arm64.Arm64Instruction;
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using CapstoneArm64InstructionId = Gee.External.Capstone.Arm64.Arm64InstructionId;
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using CapstoneArm64Operand = Gee.External.Capstone.Arm64.Arm64Operand;
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using CapstoneArm64OperandType = Gee.External.Capstone.Arm64.Arm64OperandType;
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using CapstoneArm64RegisterId = Gee.External.Capstone.Arm64.Arm64RegisterId;
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namespace BenchmarkDotNet.Disassemblers;
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internal static class Arm64InstructionExtensions
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{
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#region Extension methods for Capstone
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extension(CapstoneArm64Instruction instruction)
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{
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public CapstoneArm64RegisterId GetRegisterId(int index)
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{
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var operands = instruction.Details.Operands;
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if ((uint)index >= (uint)operands.Length)
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throw new ArgumentOutOfRangeException(nameof(index));
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return operands[index].Register.Id;
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}
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public Arm64ShiftOperation GetShiftOperation(int index)
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{
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var operands = instruction.Details.Operands;
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if ((uint)index >= (uint)operands.Length)
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throw new ArgumentOutOfRangeException(nameof(index));
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var operand = operands[index];
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var shiftOperation = operand.ShiftOperation;
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switch (instruction.Id)
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{
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case CapstoneArm64InstructionId.ARM64_INS_ADD:
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case CapstoneArm64InstructionId.ARM64_INS_ADRP:
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case CapstoneArm64InstructionId.ARM64_INS_MOVK:
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case CapstoneArm64InstructionId.ARM64_INS_MOVZ:
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switch (shiftOperation)
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{
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case Arm64ShiftOperation.ARM64_SFT_LSL:
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return shiftOperation;
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case Arm64ShiftOperation.Invalid:
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if (operand.ShiftValue == 0)
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return Arm64ShiftOperation.ARM64_SFT_LSL; // Capstone represents LSL #0 as ARM64_SFT_INVALID.
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goto default;
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// Currently used instructions don't accept other shift operations.
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default:
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throw new NotSupportedException($"Unexpected shift operation({shiftOperation}) is specified on instruction({instruction.Id})");
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}
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// Currently other instructions are not supported.
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default:
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throw new UnreachableException($"Unexpected instruction({instruction.Id}) is specified");
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}
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}
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public int GetShiftAmount(int index)
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{
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var operands = instruction.Details.Operands;
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if ((uint)index >= (uint)operands.Length)
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throw new ArgumentOutOfRangeException(nameof(index));
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var operand = operands[index];
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// Capstone represents LSL #0 as ARM64_SFT_INVALID.
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if (operand.ShiftOperation == Arm64ShiftOperation.Invalid)
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return 0;
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return operand.ShiftValue;
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}
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public long GetRawImmediateValue(int index)
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{
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var operands = instruction.Details.Operands;
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if ((uint)index >= (uint)operands.Length)
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throw new ArgumentOutOfRangeException(nameof(index));
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return operands[index].Immediate;
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}
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public long GetShiftedImmediateValue(int index)
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{
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var operands = instruction.Details.Operands;
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if ((uint)index >= (uint)operands.Length)
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throw new ArgumentOutOfRangeException(nameof(index));
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var operand = operands[index];
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var shiftOperation = instruction.GetShiftOperation(index);
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switch (shiftOperation)
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{
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case Arm64ShiftOperation.ARM64_SFT_LSL:
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var shiftAmount = instruction.GetShiftAmount(index);
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return operand.Immediate << shiftAmount;
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default:
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throw new NotSupportedException($"Unexpected shift operation({shiftOperation}) is specified on instruction({instruction.Id})");
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}
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}
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public bool TryGetOperand(
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int index,
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CapstoneArm64OperandType type,
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[NotNullWhen(true)] out CapstoneArm64Operand? result)
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{
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var operands = instruction.Details.Operands;
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if ((uint)index >= (uint)operands.Length)
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{
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result = null;
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return false;
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}
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result = operands[index];
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if (result.Type == type)
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return true;
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result = null;
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return false;
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}
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public bool BelongsToGroup(Arm64InstructionGroupId expectedGroup)
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{
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if (instruction.Bytes.Length < 4)
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return false;
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var rawInstruction = BinaryPrimitives.ReadUInt32LittleEndian(instruction.Bytes);
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return AsmArm64Instruction.Decode(rawInstruction).BelongsToGroup(expectedGroup);
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}
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public bool IsLdrFromTrackedRegister(CapstoneArm64RegisterId trackedRegister)
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{
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if (instruction.Id != CapstoneArm64InstructionId.ARM64_INS_LDR)
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return false;
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if (!instruction.TryGetOperand(1, CapstoneArm64OperandType.Memory, out var memoryOperand))
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return false;
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// Check base register is the register that is currently tracked.
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var memory = memoryOperand.Memory;
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if (memory.Base.Id != trackedRegister)
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return false;
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// Check displacement.
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if (memory.Displacement != 0)
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return false;
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// Check index register is specified.
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if (memory.Index != null)
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return false;
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// Ldr from tracked register (with no displacement/index register).
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return true;
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}
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public bool IsConditionalBranch()
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{
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switch (instruction.Id)
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{
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case Gee.External.Capstone.Arm64.Arm64InstructionId.ARM64_INS_CBZ:
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case Gee.External.Capstone.Arm64.Arm64InstructionId.ARM64_INS_CBNZ:
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case Gee.External.Capstone.Arm64.Arm64InstructionId.ARM64_INS_TBZ:
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case Gee.External.Capstone.Arm64.Arm64InstructionId.ARM64_INS_TBNZ:
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return true;
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case Gee.External.Capstone.Arm64.Arm64InstructionId.ARM64_INS_B:
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switch (instruction.Details.ConditionCode)
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{
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// `B` and `B.AL` instructions is unconditional branch.
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case Gee.External.Capstone.Arm64.Arm64ConditionCode.Invalid:
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case Gee.External.Capstone.Arm64.Arm64ConditionCode.ARM64_CC_AL:
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return false;
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default:
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return true;
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}
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default:
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return false;
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}
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}
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public bool IsUnconditionalControlFlow()
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{
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return instruction.BelongsToGroup(Arm64InstructionGroupId.ARM64_GRP_BRANCH_RELATIVE)
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|| instruction.BelongsToGroup(Arm64InstructionGroupId.ARM64_GRP_CALL)
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|| instruction.BelongsToGroup(Arm64InstructionGroupId.ARM64_GRP_JUMP);
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}
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}
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#endregion
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#region Extension methods for AsmArm64
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extension(AsmArm64Instruction instruction)
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{
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public Arm64RegisterOperand GetRegisterOperand(int index)
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=> (Arm64RegisterOperand)instruction.GetOperand(index, Arm64OperandKind.Register);
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public Arm64ImmediateOperand GetImmediateOperand(int index)
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=> (Arm64ImmediateOperand)instruction.GetOperand(index, Arm64OperandKind.Immediate);
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private AsmArm64Operand GetOperand(int index, Arm64OperandKind expectedKind)
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{
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var operand = instruction.GetOperand(index);
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if (operand.Kind != expectedKind)
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throw new ArgumentException($"The operand at index {index} is not of the expected kind {expectedKind}. Actual kind: {operand.Kind}");
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return operand;
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}
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public bool BelongsToGroup(Arm64InstructionGroupId expectedGroup)
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{
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// AsmArm64 don't provide mapping for instruction groups.
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// So it need to simulate Capstone's BelongsToGroup behavior.
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// Capstone's group mappings are defined at https://github.com/capstone-engine/capstone/blob/6.0.0-Alpha10/arch/AArch64/AArch64GenCSMappingInsn.inc
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switch (expectedGroup)
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{
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case Arm64InstructionGroupId.ARM64_GRP_JUMP:
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switch (instruction.Id)
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{
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case Arm64InstructionId.B_only_branch_imm:
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case Arm64InstructionId.B_only_condbranch:
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case Arm64InstructionId.BC_only_condbranch:
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case Arm64InstructionId.BR_64_branch_reg:
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case Arm64InstructionId.BRAA_64p_branch_reg:
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case Arm64InstructionId.BRAAZ_64_branch_reg:
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case Arm64InstructionId.BRAB_64p_branch_reg:
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case Arm64InstructionId.BRABZ_64_branch_reg:
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case Arm64InstructionId.CBNZ_32_compbranch:
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case Arm64InstructionId.CBNZ_64_compbranch:
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case Arm64InstructionId.CBZ_32_compbranch:
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case Arm64InstructionId.CBZ_64_compbranch:
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case Arm64InstructionId.DRPS_64e_branch_reg:
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case Arm64InstructionId.ERET_64e_branch_reg:
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case Arm64InstructionId.ERETAA_64e_branch_reg:
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case Arm64InstructionId.ERETAB_64e_branch_reg:
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case Arm64InstructionId.RET_64r_branch_reg:
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case Arm64InstructionId.RETAA_64e_branch_reg:
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case Arm64InstructionId.RETAASPPCR_64m_branch_reg:
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case Arm64InstructionId.RETAASPPC_only_miscbranch:
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case Arm64InstructionId.RETAB_64e_branch_reg:
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case Arm64InstructionId.RETABSPPCR_64m_branch_reg:
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case Arm64InstructionId.RETABSPPC_only_miscbranch:
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case Arm64InstructionId.TBNZ_only_testbranch:
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case Arm64InstructionId.TBZ_only_testbranch:
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return true;
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default:
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return false;
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}
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case Arm64InstructionGroupId.ARM64_GRP_CALL:
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switch (instruction.Id)
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{
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case Arm64InstructionId.BL_only_branch_imm:
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case Arm64InstructionId.BLR_64_branch_reg: // BLR: Branch with link
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case Arm64InstructionId.BLRAA_64p_branch_reg: // BLRAA: Branch with link to register with PAC
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case Arm64InstructionId.BLRAB_64p_branch_reg: // BLRAB: Branch with link to register with PAC
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case Arm64InstructionId.BLRAAZ_64_branch_reg: // Z: Zero modifier
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case Arm64InstructionId.BLRABZ_64_branch_reg: // Z: Zero modifier
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case Arm64InstructionId.HVC_ex_exception:
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case Arm64InstructionId.SMC_ex_exception:
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case Arm64InstructionId.SVC_ex_exception:
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return true;
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default:
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return false;
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}
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case Arm64InstructionGroupId.ARM64_GRP_RET:
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switch (instruction.Id)
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{
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case Arm64InstructionId.DRPS_64e_branch_reg:
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case Arm64InstructionId.ERET_64e_branch_reg:
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case Arm64InstructionId.ERETAA_64e_branch_reg:
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case Arm64InstructionId.ERETAB_64e_branch_reg:
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case Arm64InstructionId.RET_64r_branch_reg:
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case Arm64InstructionId.RETAA_64e_branch_reg:
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case Arm64InstructionId.RETAASPPC_only_miscbranch:
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case Arm64InstructionId.RETAASPPCR_64m_branch_reg:
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case Arm64InstructionId.RETAB_64e_branch_reg:
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case Arm64InstructionId.RETABSPPC_only_miscbranch:
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case Arm64InstructionId.RETABSPPCR_64m_branch_reg:
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return true;
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default:
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return false;
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}
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case Arm64InstructionGroupId.ARM64_GRP_BRANCH_RELATIVE:
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switch (instruction.Id)
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{
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case Arm64InstructionId.B_only_branch_imm:
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case Arm64InstructionId.B_only_condbranch:
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case Arm64InstructionId.BC_only_condbranch:
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case Arm64InstructionId.BL_only_branch_imm:
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case Arm64InstructionId.CBNZ_32_compbranch:
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case Arm64InstructionId.CBNZ_64_compbranch:
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case Arm64InstructionId.CBZ_32_compbranch:
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case Arm64InstructionId.CBZ_64_compbranch:
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case Arm64InstructionId.RETAASPPC_only_miscbranch:
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case Arm64InstructionId.RETABSPPC_only_miscbranch:
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case Arm64InstructionId.TBNZ_only_testbranch:
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case Arm64InstructionId.TBZ_only_testbranch:
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return true;
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default:
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return false;
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}
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// Currently, other group ids are not supported.
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case Arm64InstructionGroupId.Invalid:
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case Arm64InstructionGroupId.ARM64_GRP_INT:
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case Arm64InstructionGroupId.ARM64_GRP_PRIVILEGE:
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case Arm64InstructionGroupId.ARM64_GRP_CRYPTO:
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case Arm64InstructionGroupId.ARM64_GRP_FPARMV8:
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case Arm64InstructionGroupId.ARM64_GRP_NEON:
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case Arm64InstructionGroupId.ARM64_GRP_CRC:
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default:
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throw new NotSupportedException($"Group {expectedGroup} is not supported.");
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}
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}
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public IEnumerable<Arm64RegisterAny> GetWrittenRegisters()
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{
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foreach (var operand in instruction.Operands)
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{
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switch (operand.Kind)
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{
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case Arm64OperandKind.Register:
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var registerOperand = (Arm64RegisterOperand)operand;
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if ((registerOperand.Flags & Arm64OperandFlags.Write) != 0)
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yield return registerOperand.Value;
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continue;
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case Arm64OperandKind.RegisterGroup:
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var registerGroupOperand = (Arm64RegisterGroupOperand)operand;
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if ((registerGroupOperand.Flags & Arm64OperandFlags.Write) != 0)
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{
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var registerGroupAny = registerGroupOperand.Value;
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var baseRegister = registerGroupAny.BaseRegister;
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for (int i = 0; i < registerGroupAny.Count; ++i)
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{
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yield return Arm64RegisterAny.Create(baseRegister.Kind, baseRegister.Index + i, baseRegister.VKind, baseRegister.ElementCount, baseRegister.ElementIndex);
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}
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}
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continue;
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default:
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continue;
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}
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}
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}
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}
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#endregion
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}

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