- Circuit: 12-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add12u_19A | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| add12u_4RF | 0.0098 | 0.049 | 25.00 | 0.025 | 2.5 | [Verilog] [C] |
| add12u_4XD | 0.19 | 0.78 | 36.72 | 0.52 | 760 | [Verilog] [C] |
| add12u_4YK | 0.046 | 0.24 | 39.84 | 0.13 | 54 | [Verilog] [C] |
| add12u_4YR | 0.24 | 0.78 | 49.22 | 0.65 | 876 | [Verilog] [C] |
| add12u_4FZ | 0.048 | 0.29 | 58.98 | 0.13 | 48 | [Verilog] [C] |
| add12u_4R6 | 0.22 | 0.81 | 69.53 | 0.60 | 628 | [Verilog] [C] |
| add12u_054 | 6.35 | 14.55 | 89.56 | 16.19 | 524173 | [Verilog] [C] |
| add12u_2MB | 12.50 | 25.00 | 100.00 | 30.62 | 13015.54e2 | [Verilog] [C] |
- V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020