- Circuit: 8-bit signed adders (with overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8s_83C | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8s_83N | 0.16 | 1.56 | 12.50 | 1.29 | 0.5 | [Verilog] [C] |
| add8s_6FR | 0.39 | 1.56 | 37.30 | 1.48 | 0.7 | [Verilog] [C] |
| add8s_6TR | 0.86 | 3.91 | 66.85 | 4.21 | 2.4 | [Verilog] [C] |
| add8s_6UN | 1.88 | 5.47 | 87.50 | 11.76 | 8.4 | [Verilog] [C] |
| add8s_6PM | 3.75 | 9.38 | 93.75 | 26.40 | 35 | [Verilog] [C] |
| add8s_6H2 | 6.88 | 25.00 | 99.27 | 40.60 | 110 | [Verilog] [C] |
| add8s_6J2 | 12.27 | 33.59 | 98.52 | 75.00 | 343 | [Verilog] [C] |
| add8s_701 | 25.47 | 72.66 | 99.11 | 161.98 | 1507 | [Verilog] [C] |
| add8s_6HF | 44.45 | 100.00 | 99.48 | 99.98 | 4551 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020