- Circuit: 8-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8se_7A2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8se_7C9 | 0.078 | 0.78 | 12.50 | 1.00 | 0.5 | [Verilog] [C] |
| add8se_91X | 0.20 | 0.78 | 25.00 | 1.74 | 1.0 | [Verilog] [C] |
| add8se_78P | 0.39 | 0.78 | 50.00 | 4.15 | 2.0 | [Verilog] [C] |
| add8se_7LN | 0.47 | 1.17 | 62.50 | 4.89 | 2.8 | [Verilog] [C] |
| add8se_90J | 0.55 | 1.56 | 78.12 | 5.69 | 3.2 | [Verilog] [C] |
| add8se_8VV | 1.09 | 3.12 | 89.06 | 10.79 | 12 | [Verilog] [C] |
| add8se_8XS | 25.00 | 50.00 | 99.95 | 249.36 | 4798 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020