- Circuit: 8-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8se_7A2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8se_8YC | 0.078 | 0.39 | 25.00 | 0.87 | 0.2 | [Verilog] [C] |
| add8se_91X | 0.20 | 0.78 | 25.00 | 1.74 | 1.0 | [Verilog] [C] |
| add8se_7LN | 0.47 | 1.17 | 62.50 | 4.89 | 2.8 | [Verilog] [C] |
| add8se_7J7 | 0.82 | 2.73 | 84.38 | 8.19 | 7.2 | [Verilog] [C] |
| add8se_76P | 2.23 | 7.42 | 93.75 | 18.02 | 50 | [Verilog] [C] |
| add8se_8UF | 4.38 | 12.50 | 97.27 | 39.03 | 190 | [Verilog] [C] |
| add8se_7N1 | 16.64 | 50.00 | 99.22 | 75.00 | 2723 | [Verilog] [C] |
| add8se_90X | 15.35 | 50.00 | 99.22 | 100.10 | 2301 | [Verilog] [C] |
| add8se_8XS | 25.00 | 50.00 | 99.95 | 249.36 | 4798 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020