- Circuit: 8x2-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x2u_106 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x2u_07K | 0.024 | 0.098 | 25.00 | 0.59 | 0.25 | [Verilog] [C] |
| mul8x2u_0PJ | 0.049 | 0.20 | 25.00 | 0.76 | 1.0 | [Verilog] [C] |
| mul8x2u_0X3 | 0.14 | 0.68 | 53.12 | 2.72 | 5.0 | [Verilog] [C] |
| mul8x2u_0SV | 0.32 | 1.46 | 65.62 | 6.33 | 23 | [Verilog] [C] |
| mul8x2u_0A3 | 0.68 | 3.03 | 71.78 | 11.78 | 105 | [Verilog] [C] |
| mul8x2u_16M | 1.50 | 8.30 | 72.75 | 21.82 | 528 | [Verilog] [C] |
| mul8x2u_0SJ | 3.53 | 12.70 | 74.41 | 37.40 | 2582 | [Verilog] [C] |
| mul8x2u_0SN | 7.50 | 25.39 | 74.71 | 60.33 | 10903 | [Verilog] [C] |
| mul8x2u_0NG | 18.68 | 74.71 | 74.71 | 100.00 | 76011 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020