- Circuit: 8x2-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
---|---|---|---|---|---|---|
mul8x2u_106 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
mul8x2u_07K | 0.024 | 0.098 | 25.00 | 0.59 | 0.25 | [Verilog] [C] |
mul8x2u_0M1 | 0.073 | 0.20 | 37.50 | 1.64 | 1.5 | [Verilog] [C] |
mul8x2u_0S7 | 0.067 | 0.29 | 37.50 | 1.45 | 1.5 | [Verilog] [C] |
mul8x2u_0FS | 0.23 | 0.88 | 64.06 | 4.34 | 12 | [Verilog] [C] |
mul8x2u_15A | 0.35 | 1.66 | 69.14 | 6.59 | 27 | [Verilog] [C] |
mul8x2u_11V | 1.17 | 3.81 | 71.29 | 15.38 | 296 | [Verilog] [C] |
mul8x2u_098 | 2.00 | 7.91 | 73.83 | 25.39 | 829 | [Verilog] [C] |
mul8x2u_0XM | 4.90 | 15.53 | 74.22 | 43.01 | 5217 | [Verilog] [C] |
mul8x2u_0SN | 7.50 | 25.39 | 74.71 | 60.33 | 10903 | [Verilog] [C] |
mul8x2u_0NG | 18.68 | 74.71 | 74.71 | 100.00 | 76011 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020