- Circuit: 8x6-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x6u_049 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x6u_12E | 0.00076 | 0.024 | 3.12 | 0.019 | 0.5 | [Verilog] [C] |
| mul8x6u_5EZ | 0.0015 | 0.0061 | 25.00 | 0.058 | 0.25 | [Verilog] [C] |
| mul8x6u_5TS | 0.0045 | 0.012 | 37.11 | 0.16 | 1.5 | [Verilog] [C] |
| mul8x6u_446 | 0.019 | 0.061 | 73.83 | 0.60 | 17 | [Verilog] [C] |
| mul8x6u_3DQ | 0.07 | 0.29 | 86.56 | 1.70 | 219 | [Verilog] [C] |
| mul8x6u_3E7 | 0.20 | 0.74 | 95.88 | 4.51 | 1613 | [Verilog] [C] |
| mul8x6u_4RX | 0.76 | 3.06 | 97.53 | 12.27 | 24027 | [Verilog] [C] |
| mul8x6u_23K | 3.56 | 13.99 | 97.90 | 36.16 | 532474 | [Verilog] [C] |
| mul8x6u_51C | 24.51 | 98.05 | 98.05 | 100.00 | 28960.286e3 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020