- Circuit: 8x6-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x6u_049 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x6u_5EZ | 0.0015 | 0.0061 | 25.00 | 0.058 | 0.25 | [Verilog] [C] |
| mul8x6u_5TS | 0.0045 | 0.012 | 37.11 | 0.16 | 1.5 | [Verilog] [C] |
| mul8x6u_4TY | 0.014 | 0.037 | 62.50 | 0.47 | 10 | [Verilog] [C] |
| mul8x6u_629 | 0.028 | 0.10 | 79.69 | 0.83 | 38 | [Verilog] [C] |
| mul8x6u_5HD | 0.12 | 0.43 | 95.75 | 2.81 | 556 | [Verilog] [C] |
| mul8x6u_5Y1 | 0.31 | 1.21 | 95.89 | 6.26 | 3923 | [Verilog] [C] |
| mul8x6u_2HT | 0.96 | 3.88 | 97.55 | 15.15 | 38505 | [Verilog] [C] |
| mul8x6u_0MH | 2.90 | 11.38 | 97.96 | 35.91 | 353184 | [Verilog] [C] |
| mul8x6u_045 | 7.98 | 30.23 | 98.02 | 64.72 | 29431.077e2 | [Verilog] [C] |
| mul8x6u_51C | 24.51 | 98.05 | 98.05 | 100.00 | 28960.286e3 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020