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stm32/timer: add bare type-erased timer driver
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‎.gitignore‎

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@@ -5,3 +5,4 @@ Cargo.lock
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third_party
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/Cargo.toml
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out/
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Session.vim

‎embassy-stm32/src/timer/bare.rs‎

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//! Bare register-level timer driver.
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//!
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//! This module provides the core functionality for type-erased drivers for all STM32 timers. It
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//! provides integration with the RCC and direct access to the timer registers. It is intended to
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//! serve as a building block for higher level drivers.
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use core::marker::PhantomData;
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use embassy_hal_internal::PeripheralRef;
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use super::{AdvancedInstance4Channel, Channel, CoreInstance, GeneralInstance4Channel, Info, TimerBits};
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use crate::gpio::{AfType, AnyPin, Pin, SealedPin};
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use crate::time::Hertz;
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use crate::{into_ref, pac, rcc, Peripheral};
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trait TimerPinMarkerSealed {}
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/// Trait for marker types that represent all possible timer pins.
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#[allow(private_bounds)]
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pub trait TimerPinMarker: TimerPinMarkerSealed {}
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/// Timer pin trait.
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///
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/// If a pin peripheral implements `TimerPin<T, M>`, it means that it can be used with timer `T` in
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/// the role represented by marker type `M`. For example, `TimerPin<TIM1, Ch2>` is implemented for
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/// all pins that can be used as channel 2 for timer TIM1.
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///
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/// This trait is equivalent to the pin-specific traits defined in the [`timer`][super] module; for
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/// example `TimerPin<T, Ch1>` is equivalent to [`timer::Channel1Pin<T>`][super::Channel1Pin].
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pub trait TimerPin<T: CoreInstance, M: TimerPinMarker>: Pin {
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/// Get the AF number needed to use this pin with timer `T` as pin `M`.
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fn af_num(&self) -> u8;
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}
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/// Marker type for channel 1 pin.
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pub enum Ch1 {}
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/// Marker type for channel 2 pin.
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pub enum Ch2 {}
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/// Marker type for channel 3 pin.
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pub enum Ch3 {}
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/// Marker type for channel 4 pin.
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pub enum Ch4 {}
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/// Marker type for external trigger pin.
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pub enum Etr {}
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/// Marker type for channel 1 complementary pin.
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pub enum Ch1N {}
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/// Marker type for channel 2 complementary pin.
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pub enum Ch2N {}
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/// Marker type for channel 3 complementary pin.
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pub enum Ch3N {}
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/// Marker type for channel 4 complementary pin.
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pub enum Ch4N {}
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/// Marker type for break input pin.
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pub enum Bkin {}
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/// Marker type for break input comparator 1 pin.
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pub enum BkinComp1 {}
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/// Marker type for break input comparator 2 pin.
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pub enum BkinComp2 {}
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/// Marker type for break 2 input pin.
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pub enum Bkin2 {}
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/// Marker type for break 2 input comparator 1 pin.
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pub enum Bkin2Comp1 {}
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/// Marker type for break 2 input comparator 2 pin.
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pub enum Bkin2Comp2 {}
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macro_rules! impl_pin {
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($marker_ty:ident, $t:ident, $pin_trait:path, $peri_trait:ident) => {
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impl TimerPinMarkerSealed for $marker_ty {}
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impl TimerPinMarker for $marker_ty {}
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impl<$t: $peri_trait, P> TimerPin<$t, $marker_ty> for P
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where
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P: $pin_trait,
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{
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fn af_num(&self) -> u8 {
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<P as $pin_trait>::af_num(self)
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}
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}
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};
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}
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impl_pin!(Ch1, T, super::Channel1Pin<T>, GeneralInstance4Channel);
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impl_pin!(Ch2, T, super::Channel2Pin<T>, GeneralInstance4Channel);
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impl_pin!(Ch3, T, super::Channel3Pin<T>, GeneralInstance4Channel);
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impl_pin!(Ch4, T, super::Channel4Pin<T>, GeneralInstance4Channel);
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impl_pin!(Etr, T, super::ExternalTriggerPin<T>, GeneralInstance4Channel);
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impl_pin!(Ch1N, T, super::Channel1ComplementaryPin<T>, AdvancedInstance4Channel);
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impl_pin!(Ch2N, T, super::Channel2ComplementaryPin<T>, AdvancedInstance4Channel);
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impl_pin!(Ch3N, T, super::Channel3ComplementaryPin<T>, AdvancedInstance4Channel);
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impl_pin!(Ch4N, T, super::Channel4ComplementaryPin<T>, AdvancedInstance4Channel);
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impl_pin!(Bkin, T, super::BreakInputPin<T>, AdvancedInstance4Channel);
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impl_pin!(
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BkinComp1,
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T,
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super::BreakInputComparator1Pin<T>,
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AdvancedInstance4Channel
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);
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impl_pin!(
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BkinComp2,
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T,
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super::BreakInputComparator2Pin<T>,
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AdvancedInstance4Channel
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);
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impl_pin!(Bkin2, T, super::BreakInput2Pin<T>, AdvancedInstance4Channel);
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impl_pin!(
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Bkin2Comp1,
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T,
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super::BreakInput2Comparator1Pin<T>,
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AdvancedInstance4Channel
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);
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impl_pin!(
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Bkin2Comp2,
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T,
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super::BreakInput2Comparator2Pin<T>,
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AdvancedInstance4Channel
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);
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/// Trait for marker types that represent the four channel pins ([`Ch1`], [`Ch2`], [`Ch3`],
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/// [`Ch4`]).
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pub trait TimerChannelMarker: TimerPinMarker {
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/// Representation of the channel number.
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const CHANNEL: Channel;
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}
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macro_rules! impl_channel {
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($marker_ty:ident, $channel:expr) => {
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impl TimerChannelMarker for $marker_ty {
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const CHANNEL: Channel = $channel;
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}
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};
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}
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impl_channel!(Ch1, Channel::Ch1);
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impl_channel!(Ch2, Channel::Ch2);
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impl_channel!(Ch3, Channel::Ch3);
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impl_channel!(Ch4, Channel::Ch4);
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/// Type-erased timer pin.
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///
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/// The only purpose of this struct is to correctly initialize the pin in the constructor and
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/// deinitialize it (set it as disconnected) in the constructor. It can be used to implement
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/// higher-level pin wrappers, like [`simple_pwm::PwmPin`](super::simple_pwm::PwmPin).
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pub struct AnyTimerPin<'d> {
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pin: PeripheralRef<'d, AnyPin>,
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}
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impl<'d> AnyTimerPin<'d> {
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/// Initializes a timer pin `M` for timer instance `T`.
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pub fn new<T: CoreInstance, M: TimerPinMarker>(
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pin: impl Peripheral<P = impl TimerPin<T, M>> + 'd,
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af_type: AfType,
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) -> Self {
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into_ref!(pin);
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let af_num = pin.af_num();
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let pin = pin.map_into();
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pin.set_as_af(af_num, af_type);
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Self { pin }
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}
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}
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impl<'d> Drop for AnyTimerPin<'d> {
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fn drop(&mut self) {
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self.pin.set_as_disconnected();
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}
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}
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/// Type-erased bare driver for timers.
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///
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/// This driver provides direct access to the timer registers, with the type of the peripheral
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/// erased.
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pub struct AnyTimer<'d, Regs> {
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info: &'d Info,
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kernel_clock: Hertz,
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_phantom: PhantomData<&'d mut Regs>,
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}
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macro_rules! impl_regs {
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($reg_ty:path, $new:ident, $peri_trait:path) => {
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impl<'d> AnyTimer<'d, $reg_ty> {
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/// Initializes timer instance `T`.
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pub fn $new<T: $peri_trait>(_tim: impl Peripheral<P = T> + 'd) -> Self {
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rcc::enable_and_reset::<T>();
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Self {
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info: T::info(),
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kernel_clock: T::frequency(),
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_phantom: PhantomData,
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}
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}
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/// Get the registers for this timer.
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pub fn regs(&self) -> $reg_ty {
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unsafe { <$reg_ty>::from_ptr(self.info.regs) }
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}
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}
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};
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}
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impl_regs!(pac::timer::TimCore, new_core, CoreInstance);
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impl_regs!(pac::timer::TimBasicNoCr2, new_basic_no_cr2, super::BasicNoCr2Instance);
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impl_regs!(pac::timer::TimBasic, new_basic, super::BasicInstance);
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impl_regs!(pac::timer::Tim1ch, new_1ch, super::GeneralInstance1Channel);
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impl_regs!(pac::timer::Tim2ch, new_2ch, super::GeneralInstance2Channel);
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impl_regs!(pac::timer::TimGp16, new_gp16, GeneralInstance4Channel);
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#[cfg(not(timer_l0))]
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impl_regs!(pac::timer::TimGp32, new_gp32, super::GeneralInstance32bit4Channel);
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#[cfg(not(timer_l0))]
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impl_regs!(pac::timer::Tim1chCmp, new_1ch_cmp, super::AdvancedInstance1Channel);
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#[cfg(not(timer_l0))]
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impl_regs!(pac::timer::Tim2chCmp, new_2ch_cmp, super::AdvancedInstance2Channel);
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#[cfg(not(timer_l0))]
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impl_regs!(pac::timer::TimAdv, new_advanced, AdvancedInstance4Channel);
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impl<'d, Regs> AnyTimer<'d, Regs> {
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/// Get the kernel clock frequency for the timer peripheral.
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///
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/// Unless you switch the timer to a different clock source, this is the frequency that is fed
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/// into the prescaler to drive the timer.
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pub fn clock_frequency(&self) -> Hertz {
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self.kernel_clock
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}
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/// Get the number of bits in this timer (16 or 32).
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pub fn bits(&self) -> TimerBits {
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self.info.bits
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}
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}
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impl<'d, Regs> Drop for AnyTimer<'d, Regs> {
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fn drop(&mut self) {
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self.info.rcc.disable();
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}
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}

‎embassy-stm32/src/timer/mod.rs‎

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@@ -4,6 +4,7 @@ use core::marker::PhantomData;
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use embassy_sync::waitqueue::AtomicWaker;
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pub mod bare;
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#[cfg(not(stm32l0))]
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pub mod complementary_pwm;
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pub mod input_capture;
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pub mod simple_pwm;
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use crate::interrupt;
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use crate::rcc::RccPeripheral;
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use crate::rcc::{RccInfo, RccPeripheral, SealedRccPeripheral};
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/// Timer channel.
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#[derive(Clone, Copy)]
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}
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}
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trait SealedInstance: RccPeripheral {
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struct Info {
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regs: *mut (),
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rcc: RccInfo,
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bits: TimerBits,
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}
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unsafe impl Sync for Info {}
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trait SealedInstance {
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fn info() -> &'static Info;
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/// Async state for this timer
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fn state() -> &'static State;
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}
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/// Core timer instance.
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#[allow(private_bounds)]
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pub trait CoreInstance: SealedInstance + 'static {
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pub trait CoreInstance: SealedInstance + RccPeripheral + 'static {
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/// Update Interrupt for this timer.
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type UpdateInterrupt: interrupt::typelevel::Interrupt;
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/// This is a raw pointer to the register block. The actual register block layout varies depending on the timer type.
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fn regs() -> *mut ();
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}
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/// Cut-down basic timer instance.
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pub trait BasicNoCr2Instance: CoreInstance {}
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/// Basic timer instance.
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// This trait add *extra* methods to GeneralInstance4Channel,
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// that GeneralInstance4Channel doesn't use, but the "AdvancedInstance"s need.
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// And it's a private trait, so it's content won't leak to outer namespace.
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// And it's a private trait, so its content won't leak to outer namespace.
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//
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// If you want to add a new method to it, please leave a detail comment to explain it.
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trait General4ChBlankSealed {
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macro_rules! impl_core_timer {
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($inst:ident, $bits:expr) => {
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impl SealedInstance for crate::peripherals::$inst {
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fn info() -> &'static Info {
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static INFO: Info = Info {
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regs: crate::pac::$inst.as_ptr(),
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rcc: crate::peripherals::$inst::RCC_INFO,
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bits: $bits,
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};
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&INFO
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}
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fn state() -> &'static State {
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static STATE: State = State::new();
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&STATE

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