Move operand fields to standard RISCV file

Author: pietraferreira

include/opcode/riscv-sfpu.h

@@ -483,13 +483,4 @@
 #define OP_SH_POOL_ADDR_MODE		15
 #define OP_MASK_POOL_ADDR_MODE     	0x7
 
-#define OP_SH_CMDBUF		31
-#define OP_MASK_CMDBUF        	0x1
-#define OP_SH_REG_VALUE       	25
-#define OP_MASK_REG_VALUE     	0x3f
-#define OP_SH_CMDBUF_ADDRGEN  	30
-#define OP_MASK_CMDBUF_ADDRGEN  0x1
-#define OP_SH_REG_ADDRGEN  	25
-#define OP_MASK_REG_ADDRGEN     0x1f
-
 #endif  // RISCV_SFPU_H

include/opcode/riscv.h

@@ -399,6 +399,16 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define OP_MASK_XSO1            0x1
 #define OP_SH_XSO1              26
 
+/* Tenstorrent fields. */
+#define OP_SH_CMDBUF		31
+#define OP_MASK_CMDBUF        	0x1
+#define OP_SH_REG_VALUE       	25
+#define OP_MASK_REG_VALUE     	0x3f
+#define OP_SH_CMDBUF_ADDRGEN  	30
+#define OP_MASK_CMDBUF_ADDRGEN  0x1
+#define OP_SH_REG_ADDRGEN  	25
+#define OP_MASK_REG_ADDRGEN     0x1f
+
 #include "opcode/riscv-sfpu.h"
 
 /* ABI names for selected x-registers.  */