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pietraferreirapietraferreira
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Addrgen encodings implemention + custom operands
1 parent b527d8e commit 73ff4c8

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8 files changed

+104
-4
lines changed

8 files changed

+104
-4
lines changed

‎gas/config/tc-riscv.c‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1936,6 +1936,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
19361936
{
19371937
case '0': USE_BITS (OP_MASK_CMDBUF, OP_SH_CMDBUF); break;
19381938
case '1': USE_BITS (OP_MASK_REG_VALUE, OP_SH_REG_VALUE); break;
1939+
case '2': USE_BITS (OP_MASK_CMDBUF_ADDRGEN, OP_SH_CMDBUF_ADDRGEN); break;
1940+
case '3': USE_BITS (OP_MASK_REG_ADDRGEN, OP_SH_REG_ADDRGEN); break;
19391941
}
19401942
break;
19411943
}
@@ -8169,6 +8171,36 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
81698171
imm_expr->X_op = O_absent;
81708172
asarg = expr_parse_end;
81718173
break;
8174+
8175+
case '2':
8176+
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
8177+
|| imm_expr->X_op != O_constant
8178+
|| imm_expr->X_add_number < 0
8179+
|| imm_expr->X_add_number > 1)
8180+
{
8181+
as_bad (_("bad value for cmdbuf field, "
8182+
"values and 0...1"));
8183+
break;
8184+
}
8185+
INSERT_OPERAND (CMDBUF_ADDRGEN, *ip, imm_expr->X_add_number);
8186+
imm_expr->X_op = O_absent;
8187+
asarg = expr_parse_end;
8188+
break;
8189+
8190+
case '3':
8191+
if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
8192+
|| imm_expr->X_op != O_constant
8193+
|| imm_expr->X_add_number < 0
8194+
|| imm_expr->X_add_number > 31)
8195+
{
8196+
as_bad (_("bad value for reg field, "
8197+
"values and 0...31"));
8198+
break;
8199+
}
8200+
INSERT_OPERAND (REG_ADDRGEN, *ip, imm_expr->X_add_number);
8201+
imm_expr->X_op = O_absent;
8202+
asarg = expr_parse_end;
8203+
break;
81728204
}
81738205
}
81748206
continue;

‎gas/testsuite/gas/riscv/ttrocc-test.d‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,3 +81,12 @@ Disassembly of section .text:
8181
[ ]+118:[ ]+f005a02b[ ]+tt.rocc.scmdbuf_issue_read1_trans[ ]+a1
8282
[ ]+11c:[ ]+ee05a02b[ ]+tt.rocc.scmdbuf_issue_write1_trans[ ]+a1
8383
[ ]+120:[ ]+eec5b02b[ ]+tt.rocc.scmdbuf_issue_write2_trans[ ]+a1,a2
84+
[ ]+124:[ ]+4405a02b[ ]+tt.rocc.addrgen_wr_reg[ ]+zero,1,2,a1,zero
85+
[ ]+128:[ ]+0200452b[ ]+tt.rocc.addrgen_rd_reg[ ]+a0,0,1,zero,zero
86+
[ ]+12c:[ ]+7400002b[ ]+tt.rocc.addrgen_reset[ ]+1
87+
[ ]+130:[ ]+3400202b[ ]+tt.rocc.addrgen_reset_counters[ ]+0,zero
88+
[ ]+134:[ ]+3e00452b[ ]+tt.rocc.addrgen_peek_src[ ]+a0,0
89+
[ ]+138:[ ]+7e00e52b[ ]+tt.rocc.addrgen_pop_src[ ]+a0,1
90+
[ ]+13c:[ ]+3e05e52b[ ]+tt.rocc.addrgen_pop_x_src[ ]+a0,0,a1
91+
[ ]+140:[ ]+3c00e52b[ ]+tt.rocc.addrgen_pop_dest[ ]+a0,0
92+
[ ]+144:[ ]+3c05e52b[ ]+tt.rocc.addrgen_pop_x_dest[ ]+a0,0,a1

‎gas/testsuite/gas/riscv/ttrocc-test.s‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,3 +94,13 @@ target:
9494
tt.rocc.scmdbuf_issue_read1_trans a1
9595
tt.rocc.scmdbuf_issue_write1_trans a1
9696
tt.rocc.scmdbuf_issue_write2_trans a1,a2
97+
98+
tt.rocc.addrgen_wr_reg x0, 1, 2, a1, x0
99+
tt.rocc.addrgen_rd_reg a0, 0, 1, x0, x0
100+
tt.rocc.addrgen_reset 1
101+
tt.rocc.addrgen_reset_counters 0, x0
102+
tt.rocc.addrgen_peek_src a0, 0
103+
tt.rocc.addrgen_pop_src a0, 1
104+
tt.rocc.addrgen_pop_x_src a0, 0, a1
105+
tt.rocc.addrgen_pop_dest a0, 0
106+
tt.rocc.addrgen_pop_x_dest a0, 0, a1

‎include/opcode/riscv-opc.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3720,6 +3720,27 @@
37203720
#define MASK_TTROCC_CS_SAVE 0xfff07fff
37213721
#define MATCH_TTROCC_CS_RESTORE 0x0000205b
37223722
#define MASK_TTROCC_CS_RESTORE 0xfff07fff
3723+
#define MATCH_TTROCC_ADDRGEN_WR_REG 0x0000202b
3724+
#define MASK_TTROCC_ADDRGEN_WR_REG 0x8000707f
3725+
#define MATCH_TTROCC_ADDRGEN_RD_REG 0x0000402b
3726+
#define MASK_TTROCC_ADDRGEN_RD_REG 0x8000707f
3727+
#define MATCH_TTROCC_ADDRGEN_RESET 0x3400002b
3728+
#define MASK_TTROCC_ADDRGEN_RESET 0xbfffffff
3729+
#define MATCH_TTROCC_ADDRGEN_RESET_COUNTERS 0x3400202b
3730+
#define MASK_TTROCC_ADDRGEN_RESET_COUNTERS 0xbff07fff
3731+
#define MATCH_TTROCC_ADDRGEN_PEEK_SRC 0x3e00402b
3732+
#define MASK_TTROCC_ADDRGEN_PEEK_SRC 0xbffff07f
3733+
#define MATCH_TTROCC_ADDRGEN_POP_SRC 0x3e00e02b
3734+
#define MASK_TTROCC_ADDRGEN_POP_SRC 0xbffff07f
3735+
#define MATCH_TTROCC_ADDRGEN_POP_X_SRC 0x3e00602b
3736+
#define MASK_TTROCC_ADDRGEN_POP_X_SRC 0xbff0707f
3737+
#define MATCH_TTROCC_ADDRGEN_PEEK_DEST 0x3c00402b
3738+
#define MASK_TTROCC_ADDRGEN_PEEK_DEST 0xbffff07f
3739+
#define MATCH_TTROCC_ADDRGEN_POP_DEST 0x3c00e02b
3740+
#define MASK_TTROCC_ADDRGEN_POP_DEST 0xbffff07f
3741+
#define MATCH_TTROCC_ADDRGEN_POP_X_DEST 0x3c00602b
3742+
#define MASK_TTROCC_ADDRGEN_POP_X_DEST 0xbff0707f
3743+
37233744
#define MATCH_TTROCC_CMDBUF_WR_REG 0x0000200b
37243745
#define MASK_TTROCC_CMDBUF_WR_REG 0x0000707f
37253746
#define MATCH_TTROCC_CMDBUF_RD_REG 0x0000400b

‎include/opcode/riscv-sfpu.h‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -483,9 +483,13 @@
483483
#define OP_SH_POOL_ADDR_MODE 15
484484
#define OP_MASK_POOL_ADDR_MODE 0x7
485485

486-
#define OP_SH_CMDBUF 31
487-
#define OP_MASK_CMDBUF 0x1
488-
#define OP_SH_REG_VALUE 25
489-
#define OP_MASK_REG_VALUE 0x3f
486+
#define OP_SH_CMDBUF 31
487+
#define OP_MASK_CMDBUF 0x1
488+
#define OP_SH_REG_VALUE 25
489+
#define OP_MASK_REG_VALUE 0x3f
490+
#define OP_SH_CMDBUF_ADDRGEN 30
491+
#define OP_MASK_CMDBUF_ADDRGEN 0x1
492+
#define OP_SH_REG_ADDRGEN 25
493+
#define OP_MASK_REG_ADDRGEN 0x1f
490494

491495
#endif // RISCV_SFPU_H

‎include/opcode/riscv.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
136136
(RV_X(x, 31, 1))
137137
#define EXTRACT_REG_VALUE(x) \
138138
(RV_X(x, 25, 6))
139+
#define EXTRACT_CMDBUF_ADDRGEN(x) \
140+
(RV_X(x, 30, 1))
141+
#define EXTRACT_REG_ADDRGEN(x) \
142+
(RV_X(x, 25, 5))
139143

140144
#define ENCODE_ITYPE_IMM(x) \
141145
(RV_X(x, 0, 12) << 20)
@@ -208,6 +212,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
208212
(RV_X(x, 0, 1) << 31)
209213
#define ENCODE_REG_VALUE(x) \
210214
(RV_X(x, 0, 6) << 25)
215+
#define ENCODE_CMDBUF_ADDRGEN(x) \
216+
(RV_X(x, 0, 1) << 30)
217+
#define ENCODE_REG_ADDRGEN(x) \
218+
(RV_X(x, 0, 5) << 25)
211219

212220
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
213221
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))

‎opcodes/riscv-dis.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1542,6 +1542,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
15421542
break;
15431543
case '1':
15441544
print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (REG_VALUE, l));
1545+
break;
1546+
case '2':
1547+
print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (CMDBUF_ADDRGEN, l));
1548+
break;
1549+
case '3':
1550+
print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (REG_ADDRGEN, l));
15451551
break;
15461552
}
15471553
break;

‎opcodes/riscv-opc.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3498,6 +3498,16 @@ const struct riscv_opcode riscv_opcodes[] =
34983498
{"tt.rocc.scmdbuf_issue_read1_trans", 0, INSN_CLASS_XTTROCC, "s", MATCH_TTROCC_SCMDBUF_ISSUE_READ1_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_READ1_TRANS, match_opcode, 0},
34993499
{"tt.rocc.scmdbuf_issue_write1_trans", 0, INSN_CLASS_XTTROCC, "s", MATCH_TTROCC_SCMDBUF_ISSUE_WRITE1_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_WRITE1_TRANS, match_opcode, 0},
35003500
{"tt.rocc.scmdbuf_issue_write2_trans", 0, INSN_CLASS_XTTROCC, "s,t", MATCH_TTROCC_SCMDBUF_ISSUE_WRITE2_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_WRITE2_TRANS, match_opcode, 0},
3501+
{"tt.rocc.addrgen_reset", 0, INSN_CLASS_XTTROCC, "Jxd2", MATCH_TTROCC_ADDRGEN_RESET, MASK_TTROCC_ADDRGEN_RESET, match_opcode, 0},
3502+
{"tt.rocc.addrgen_reset_counters", 0, INSN_CLASS_XTTROCC, "Jxd2,s", MATCH_TTROCC_ADDRGEN_RESET_COUNTERS, MASK_TTROCC_ADDRGEN_RESET_COUNTERS, match_opcode, 0},
3503+
{"tt.rocc.addrgen_pop_dest", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_POP_DEST, MASK_TTROCC_ADDRGEN_POP_DEST, match_opcode, 0},
3504+
{"tt.rocc.addrgen_pop_x_dest", 0, INSN_CLASS_XTTROCC, "d,Jxd2,s", MATCH_TTROCC_ADDRGEN_POP_X_DEST, MASK_TTROCC_ADDRGEN_POP_X_DEST, match_opcode, 0},
3505+
{"tt.rocc.addrgen_peek_dest", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_PEEK_DEST, MASK_TTROCC_ADDRGEN_PEEK_DEST, match_opcode, 0},
3506+
{"tt.rocc.addrgen_peek_src", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_PEEK_SRC, MASK_TTROCC_ADDRGEN_PEEK_SRC, match_opcode, 0},
3507+
{"tt.rocc.addrgen_pop_src", 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_POP_SRC, MASK_TTROCC_ADDRGEN_POP_SRC, match_opcode, 0},
3508+
{"tt.rocc.addrgen_pop_x_src", 0, INSN_CLASS_XTTROCC, "d,Jxd2,s", MATCH_TTROCC_ADDRGEN_POP_X_SRC, MASK_TTROCC_ADDRGEN_POP_X_SRC, match_opcode, 0},
3509+
{"tt.rocc.addrgen_wr_reg", 0, INSN_CLASS_XTTROCC, "d,Jxd2,Jxd3,s,t", MATCH_TTROCC_ADDRGEN_WR_REG, MASK_TTROCC_ADDRGEN_WR_REG, match_opcode, 0},
3510+
{"tt.rocc.addrgen_rd_reg", 0, INSN_CLASS_XTTROCC, "d,Jxd2,Jxd3,s,t", MATCH_TTROCC_ADDRGEN_RD_REG, MASK_TTROCC_ADDRGEN_RD_REG, match_opcode, 0},
35013511
{"tt.rocc.cmdbuf_issue_write2_trans", 0, INSN_CLASS_XTTROCC, "Jxd0,s,t", MATCH_TTROCC_CMDBUF_ISSUE_WRITE2_TRANS, MASK_TTROCC_CMDBUF_ISSUE_WRITE2_TRANS, match_opcode, 0},
35023512
{"tt.rocc.cmdbuf_issue_write1_trans", 0, INSN_CLASS_XTTROCC, "Jxd0,s", MATCH_TTROCC_CMDBUF_ISSUE_WRITE1_TRANS, MASK_TTROCC_CMDBUF_ISSUE_WRITE1_TRANS, match_opcode, 0},
35033513
{"tt.rocc.cmdbuf_issue_read2_trans", 0, INSN_CLASS_XTTROCC, "Jxd0,s,t", MATCH_TTROCC_CMDBUF_ISSUE_READ2_TRANS, MASK_TTROCC_CMDBUF_ISSUE_READ2_TRANS, match_opcode, 0},

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