diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index b8f6958aa1d..8d6b3c8c92d 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1936,6 +1936,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		    {
 		    case '0': USE_BITS (OP_MASK_CMDBUF, OP_SH_CMDBUF); break;
 		    case '1': USE_BITS (OP_MASK_REG_VALUE, OP_SH_REG_VALUE); break;
+		    case '2': USE_BITS (OP_MASK_CMDBUF_ADDRGEN, OP_SH_CMDBUF_ADDRGEN); break;
+		    case '3': USE_BITS (OP_MASK_REG_ADDRGEN, OP_SH_REG_ADDRGEN); break;
 		    }
 		  break;
 		  }
@@ -8169,6 +8171,36 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 			  imm_expr->X_op = O_absent;
 			  asarg = expr_parse_end;
 			  break;
+
+			case '2':
+			  if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
+			      || imm_expr->X_op != O_constant
+			      || imm_expr->X_add_number < 0
+			      || imm_expr->X_add_number > 1)
+			    {
+			      as_bad (_("bad value for cmdbuf field, "
+					"values and 0...1"));
+			      break;
+			    }
+			  INSERT_OPERAND (CMDBUF_ADDRGEN, *ip, imm_expr->X_add_number);
+			  imm_expr->X_op = O_absent;
+			  asarg = expr_parse_end;
+			  break;
+
+			case '3':
+			  if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)
+			      || imm_expr->X_op != O_constant
+			      || imm_expr->X_add_number < 0
+			      || imm_expr->X_add_number > 31)
+			    {
+			      as_bad (_("bad value for reg field, "
+					"values and 0...31"));
+			      break;
+			    }
+			  INSERT_OPERAND (REG_ADDRGEN, *ip, imm_expr->X_add_number);
+			  imm_expr->X_op = O_absent;
+			  asarg = expr_parse_end;
+			  break;
 			}
 		    }
 		  continue;
diff --git a/gas/testsuite/gas/riscv/ttrocc-test.d b/gas/testsuite/gas/riscv/ttrocc-test.d
index 32e0745b800..f85bed4b77a 100644
--- a/gas/testsuite/gas/riscv/ttrocc-test.d
+++ b/gas/testsuite/gas/riscv/ttrocc-test.d
@@ -81,3 +81,12 @@ Disassembly of section .text:
 [ 	]+118:[ 	]+f005a02b[ 	]+tt.rocc.scmdbuf_issue_read1_trans[ 	]+a1
 [ 	]+11c:[ 	]+ee05a02b[ 	]+tt.rocc.scmdbuf_issue_write1_trans[ 	]+a1
 [ 	]+120:[ 	]+eec5b02b[ 	]+tt.rocc.scmdbuf_issue_write2_trans[ 	]+a1,a2
+[ 	]+124:[ 	]+4405a02b[ 	]+tt.rocc.addrgen_wr_reg[ 	]+zero,1,2,a1,zero
+[ 	]+128:[ 	]+0200452b[ 	]+tt.rocc.addrgen_rd_reg[ 	]+a0,0,1,zero,zero
+[ 	]+12c:[ 	]+7400002b[ 	]+tt.rocc.addrgen_reset[ 	]+1
+[ 	]+130:[ 	]+3400202b[ 	]+tt.rocc.addrgen_reset_counters[ 	]+0,zero
+[ 	]+134:[ 	]+3e00452b[ 	]+tt.rocc.addrgen_peek_src[ 	]+a0,0
+[ 	]+138:[ 	]+7e00e52b[ 	]+tt.rocc.addrgen_pop_src[ 	]+a0,1
+[ 	]+13c:[ 	]+3e05e52b[ 	]+tt.rocc.addrgen_pop_x_src[ 	]+a0,0,a1
+[ 	]+140:[ 	]+3c00e52b[ 	]+tt.rocc.addrgen_pop_dest[ 	]+a0,0
+[ 	]+144:[ 	]+3c05e52b[ 	]+tt.rocc.addrgen_pop_x_dest[ 	]+a0,0,a1
diff --git a/gas/testsuite/gas/riscv/ttrocc-test.s b/gas/testsuite/gas/riscv/ttrocc-test.s
index 3d24a3f686a..eda5aa24af0 100644
--- a/gas/testsuite/gas/riscv/ttrocc-test.s
+++ b/gas/testsuite/gas/riscv/ttrocc-test.s
@@ -94,3 +94,13 @@ target:
     tt.rocc.scmdbuf_issue_read1_trans       a1
     tt.rocc.scmdbuf_issue_write1_trans      a1
     tt.rocc.scmdbuf_issue_write2_trans      a1,a2
+
+    tt.rocc.addrgen_wr_reg                  x0, 1, 2, a1, x0
+    tt.rocc.addrgen_rd_reg                  a0, 0, 1, x0, x0
+    tt.rocc.addrgen_reset                   1
+    tt.rocc.addrgen_reset_counters          0, x0
+    tt.rocc.addrgen_peek_src                a0, 0
+    tt.rocc.addrgen_pop_src                 a0, 1
+    tt.rocc.addrgen_pop_x_src               a0, 0, a1
+    tt.rocc.addrgen_pop_dest                a0, 0
+    tt.rocc.addrgen_pop_x_dest              a0, 0, a1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index e108ad14f96..f6433d95959 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3720,6 +3720,26 @@
 #define MASK_TTROCC_CS_SAVE 0xfff07fff
 #define MATCH_TTROCC_CS_RESTORE 0x0000205b
 #define MASK_TTROCC_CS_RESTORE 0xfff07fff
+#define MATCH_TTROCC_ADDRGEN_WR_REG 0x0000202b
+#define MASK_TTROCC_ADDRGEN_WR_REG 0x8000707f
+#define MATCH_TTROCC_ADDRGEN_RD_REG 0x0000402b
+#define MASK_TTROCC_ADDRGEN_RD_REG 0x8000707f
+#define MATCH_TTROCC_ADDRGEN_RESET 0x3400002b
+#define MASK_TTROCC_ADDRGEN_RESET 0xbfffffff
+#define MATCH_TTROCC_ADDRGEN_RESET_COUNTERS 0x3400202b
+#define MASK_TTROCC_ADDRGEN_RESET_COUNTERS 0xbff07fff
+#define MATCH_TTROCC_ADDRGEN_PEEK_SRC 0x3e00402b
+#define MASK_TTROCC_ADDRGEN_PEEK_SRC 0xbffff07f
+#define MATCH_TTROCC_ADDRGEN_POP_SRC 0x3e00e02b
+#define MASK_TTROCC_ADDRGEN_POP_SRC 0xbffff07f
+#define MATCH_TTROCC_ADDRGEN_POP_X_SRC 0x3e00602b
+#define MASK_TTROCC_ADDRGEN_POP_X_SRC 0xbff0707f
+#define MATCH_TTROCC_ADDRGEN_PEEK_DEST 0x3c00402b
+#define MASK_TTROCC_ADDRGEN_PEEK_DEST 0xbffff07f
+#define MATCH_TTROCC_ADDRGEN_POP_DEST 0x3c00e02b
+#define MASK_TTROCC_ADDRGEN_POP_DEST 0xbffff07f
+#define MATCH_TTROCC_ADDRGEN_POP_X_DEST 0x3c00602b
+#define MASK_TTROCC_ADDRGEN_POP_X_DEST 0xbff0707f
 #define MATCH_TTROCC_CMDBUF_WR_REG 0x0000200b
 #define MASK_TTROCC_CMDBUF_WR_REG 0x0000707f
 #define MATCH_TTROCC_CMDBUF_RD_REG 0x0000400b
diff --git a/include/opcode/riscv-sfpu.h b/include/opcode/riscv-sfpu.h
index 7434c9de88c..149f1572813 100644
--- a/include/opcode/riscv-sfpu.h
+++ b/include/opcode/riscv-sfpu.h
@@ -483,9 +483,4 @@
 #define OP_SH_POOL_ADDR_MODE		15
 #define OP_MASK_POOL_ADDR_MODE     	0x7
 
-#define OP_SH_CMDBUF       31
-#define OP_MASK_CMDBUF     0x1
-#define OP_SH_REG_VALUE    25
-#define OP_MASK_REG_VALUE  0x3f
-
 #endif  // RISCV_SFPU_H
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d8f8b5e4dac..eb0049b06a9 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -136,6 +136,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 31, 1))
 #define EXTRACT_REG_VALUE(x) \
   (RV_X(x, 25, 6))
+#define EXTRACT_CMDBUF_ADDRGEN(x) \
+  (RV_X(x, 30, 1))
+#define EXTRACT_REG_ADDRGEN(x) \
+  (RV_X(x, 25, 5))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -208,6 +212,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 1) << 31)
 #define ENCODE_REG_VALUE(x) \
   (RV_X(x, 0, 6) << 25)
+#define ENCODE_CMDBUF_ADDRGEN(x) \
+  (RV_X(x, 0, 1) << 30)
+#define ENCODE_REG_ADDRGEN(x) \
+  (RV_X(x, 0, 5) << 25)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -391,6 +399,16 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define OP_MASK_XSO1            0x1
 #define OP_SH_XSO1              26
 
+/* Tenstorrent fields. */
+#define OP_SH_CMDBUF		31
+#define OP_MASK_CMDBUF        	0x1
+#define OP_SH_REG_VALUE       	25
+#define OP_MASK_REG_VALUE     	0x3f
+#define OP_SH_CMDBUF_ADDRGEN  	30
+#define OP_MASK_CMDBUF_ADDRGEN  0x1
+#define OP_SH_REG_ADDRGEN  	25
+#define OP_MASK_REG_ADDRGEN     0x1f
+
 #include "opcode/riscv-sfpu.h"
 
 /* ABI names for selected x-registers.  */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 1f0b34374be..dcb57c7870d 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1542,6 +1542,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 			break;
 		      case '1':
 			print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (REG_VALUE, l));
+			break;
+		      case '2':
+			print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (CMDBUF_ADDRGEN, l));
+			break;
+		      case '3':
+			print (info->stream, dis_style_immediate, "%ld", EXTRACT_OPERAND (REG_ADDRGEN, l));
 			break;
 			  }
 			break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4d13458d752..5c708ad6b12 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3498,6 +3498,16 @@ const struct riscv_opcode riscv_opcodes[] =
 {"tt.rocc.scmdbuf_issue_read1_trans",	    0, INSN_CLASS_XTTROCC, "s", MATCH_TTROCC_SCMDBUF_ISSUE_READ1_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_READ1_TRANS, match_opcode, 0},
 {"tt.rocc.scmdbuf_issue_write1_trans",	    0, INSN_CLASS_XTTROCC, "s", MATCH_TTROCC_SCMDBUF_ISSUE_WRITE1_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_WRITE1_TRANS, match_opcode, 0},
 {"tt.rocc.scmdbuf_issue_write2_trans",	    0, INSN_CLASS_XTTROCC, "s,t", MATCH_TTROCC_SCMDBUF_ISSUE_WRITE2_TRANS, MASK_TTROCC_SCMDBUF_ISSUE_WRITE2_TRANS, match_opcode, 0},
+{"tt.rocc.addrgen_reset",                   0, INSN_CLASS_XTTROCC, "Jxd2", MATCH_TTROCC_ADDRGEN_RESET, MASK_TTROCC_ADDRGEN_RESET, match_opcode, 0},
+{"tt.rocc.addrgen_reset_counters",          0, INSN_CLASS_XTTROCC, "Jxd2,s", MATCH_TTROCC_ADDRGEN_RESET_COUNTERS, MASK_TTROCC_ADDRGEN_RESET_COUNTERS, match_opcode, 0},
+{"tt.rocc.addrgen_pop_dest",                0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_POP_DEST, MASK_TTROCC_ADDRGEN_POP_DEST, match_opcode, 0},
+{"tt.rocc.addrgen_pop_x_dest",              0, INSN_CLASS_XTTROCC, "d,Jxd2,s", MATCH_TTROCC_ADDRGEN_POP_X_DEST, MASK_TTROCC_ADDRGEN_POP_X_DEST, match_opcode, 0},
+{"tt.rocc.addrgen_peek_dest",               0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_PEEK_DEST, MASK_TTROCC_ADDRGEN_PEEK_DEST, match_opcode, 0},
+{"tt.rocc.addrgen_peek_src",                0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_PEEK_SRC, MASK_TTROCC_ADDRGEN_PEEK_SRC, match_opcode, 0},
+{"tt.rocc.addrgen_pop_src",                 0, INSN_CLASS_XTTROCC, "d,Jxd2", MATCH_TTROCC_ADDRGEN_POP_SRC, MASK_TTROCC_ADDRGEN_POP_SRC, match_opcode, 0},
+{"tt.rocc.addrgen_pop_x_src",               0, INSN_CLASS_XTTROCC, "d,Jxd2,s", MATCH_TTROCC_ADDRGEN_POP_X_SRC, MASK_TTROCC_ADDRGEN_POP_X_SRC, match_opcode, 0},
+{"tt.rocc.addrgen_wr_reg",                  0, INSN_CLASS_XTTROCC, "d,Jxd2,Jxd3,s,t", MATCH_TTROCC_ADDRGEN_WR_REG, MASK_TTROCC_ADDRGEN_WR_REG, match_opcode, 0},
+{"tt.rocc.addrgen_rd_reg",                  0, INSN_CLASS_XTTROCC, "d,Jxd2,Jxd3,s,t", MATCH_TTROCC_ADDRGEN_RD_REG, MASK_TTROCC_ADDRGEN_RD_REG, match_opcode, 0},
 {"tt.rocc.cmdbuf_issue_write2_trans",       0, INSN_CLASS_XTTROCC, "Jxd0,s,t", MATCH_TTROCC_CMDBUF_ISSUE_WRITE2_TRANS, MASK_TTROCC_CMDBUF_ISSUE_WRITE2_TRANS, match_opcode, 0},
 {"tt.rocc.cmdbuf_issue_write1_trans",       0, INSN_CLASS_XTTROCC, "Jxd0,s", MATCH_TTROCC_CMDBUF_ISSUE_WRITE1_TRANS, MASK_TTROCC_CMDBUF_ISSUE_WRITE1_TRANS, match_opcode, 0},
 {"tt.rocc.cmdbuf_issue_read2_trans",        0, INSN_CLASS_XTTROCC, "Jxd0,s,t", MATCH_TTROCC_CMDBUF_ISSUE_READ2_TRANS, MASK_TTROCC_CMDBUF_ISSUE_READ2_TRANS, match_opcode, 0},