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Xylopyrographerpre-commit-ci-lite[bot]
Xylopyrographer
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pre-commit-ci-lite[bot]
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feat(board): add Waveshare ESP32-S3-Matrix (#10072)
* feat(board) add Waveshare ESP32-S3-Matrix Adds support for the Waveshare ESP32-S3-Matrix board. Includes changes to the Rainmaker partitions as per PR #10046 . * ci(pre-commit): Apply automatic fixes --------- Co-authored-by: pre-commit-ci-lite[bot] <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com>
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‎boards.txt

100644100755
+195
Original file line numberDiff line numberDiff line change
@@ -37830,6 +37830,201 @@ Geekble_ESP32C3.menu.EraseFlash.none.upload.erase_cmd=
3783037830
Geekble_ESP32C3.menu.EraseFlash.all=Enabled
3783137831
Geekble_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e
3783237832

37833+
######################################################
37834+
37835+
ws_esp32_s3_matrix.name=Waveshare ESP32-S3-Matrix
37836+
ws_esp32_s3_matrix.vid.0=0x303a
37837+
ws_esp32_s3_matrix.pid.0=0x81FB
37838+
ws_esp32_s3_matrix.upload_port.0.vid=0x303a
37839+
ws_esp32_s3_matrix.upload_port.0.pid=0x81FB
37840+
37841+
ws_esp32_s3_matrix.bootloader.tool=esptool_py
37842+
ws_esp32_s3_matrix.bootloader.tool.default=esptool_py
37843+
37844+
ws_esp32_s3_matrix.upload.tool=esptool_py
37845+
ws_esp32_s3_matrix.upload.tool.default=esptool_py
37846+
ws_esp32_s3_matrix.upload.tool.network=esp_ota
37847+
37848+
ws_esp32_s3_matrix.upload.maximum_size=1310720
37849+
37850+
ws_esp32_s3_matrix.upload.maximum_data_size=327680
37851+
ws_esp32_s3_matrix.upload.flags=
37852+
ws_esp32_s3_matrix.upload.extra_flags=
37853+
ws_esp32_s3_matrix.upload.use_1200bps_touch=false
37854+
ws_esp32_s3_matrix.upload.wait_for_upload_port=false
37855+
37856+
ws_esp32_s3_matrix.serial.disableDTR=false
37857+
ws_esp32_s3_matrix.serial.disableRTS=false
37858+
37859+
ws_esp32_s3_matrix.build.tarch=xtensa
37860+
ws_esp32_s3_matrix.build.bootloader_addr=0x0
37861+
ws_esp32_s3_matrix.build.target=esp32s3
37862+
ws_esp32_s3_matrix.build.mcu=esp32s3
37863+
ws_esp32_s3_matrix.build.core=esp32
37864+
ws_esp32_s3_matrix.build.variant=ws_esp32_s3_matrix
37865+
ws_esp32_s3_matrix.build.board=WS_ESP32_S3_MATRIX
37866+
37867+
ws_esp32_s3_matrix.build.usb_mode=1
37868+
ws_esp32_s3_matrix.build.cdc_on_boot=0
37869+
ws_esp32_s3_matrix.build.msc_on_boot=0
37870+
ws_esp32_s3_matrix.build.dfu_on_boot=0
37871+
ws_esp32_s3_matrix.build.f_cpu=240000000L
37872+
ws_esp32_s3_matrix.build.flash_size=4MB
37873+
ws_esp32_s3_matrix.build.flash_freq=80m
37874+
ws_esp32_s3_matrix.build.flash_mode=dio
37875+
ws_esp32_s3_matrix.build.boot=qio
37876+
ws_esp32_s3_matrix.build.boot_freq=80m
37877+
ws_esp32_s3_matrix.build.partitions=default
37878+
ws_esp32_s3_matrix.build.defines=
37879+
ws_esp32_s3_matrix.build.loop_core=
37880+
ws_esp32_s3_matrix.build.event_core=
37881+
ws_esp32_s3_matrix.build.psram_type=qspi
37882+
ws_esp32_s3_matrix.build.memory_type={build.boot}_{build.psram_type}
37883+
37884+
ws_esp32_s3_matrix.menu.PSRAM.disabled=Disabled
37885+
ws_esp32_s3_matrix.menu.PSRAM.disabled.build.defines=
37886+
ws_esp32_s3_matrix.menu.PSRAM.disabled.build.psram_type=qspi
37887+
ws_esp32_s3_matrix.menu.PSRAM.enabled=Enabled
37888+
ws_esp32_s3_matrix.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
37889+
ws_esp32_s3_matrix.menu.PSRAM.enabled.build.psram_type=qspi
37890+
37891+
ws_esp32_s3_matrix.menu.FlashMode.qio=QIO 80MHz
37892+
ws_esp32_s3_matrix.menu.FlashMode.qio.build.flash_mode=dio
37893+
ws_esp32_s3_matrix.menu.FlashMode.qio.build.boot=qio
37894+
ws_esp32_s3_matrix.menu.FlashMode.qio.build.boot_freq=80m
37895+
ws_esp32_s3_matrix.menu.FlashMode.qio.build.flash_freq=80m
37896+
ws_esp32_s3_matrix.menu.FlashMode.qio120=QIO 120MHz
37897+
ws_esp32_s3_matrix.menu.FlashMode.qio120.build.flash_mode=dio
37898+
ws_esp32_s3_matrix.menu.FlashMode.qio120.build.boot=qio
37899+
ws_esp32_s3_matrix.menu.FlashMode.qio120.build.boot_freq=120m
37900+
ws_esp32_s3_matrix.menu.FlashMode.qio120.build.flash_freq=80m
37901+
37902+
ws_esp32_s3_matrix.menu.FlashSize.4M=4MB (32Mb)
37903+
ws_esp32_s3_matrix.menu.FlashSize.4M.build.flash_size=4MB
37904+
37905+
ws_esp32_s3_matrix.menu.LoopCore.1=Core 1
37906+
ws_esp32_s3_matrix.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
37907+
ws_esp32_s3_matrix.menu.LoopCore.0=Core 0
37908+
ws_esp32_s3_matrix.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
37909+
37910+
ws_esp32_s3_matrix.menu.EventsCore.1=Core 1
37911+
ws_esp32_s3_matrix.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
37912+
ws_esp32_s3_matrix.menu.EventsCore.0=Core 0
37913+
ws_esp32_s3_matrix.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
37914+
37915+
ws_esp32_s3_matrix.menu.USBMode.hwcdc=Hardware CDC and JTAG
37916+
ws_esp32_s3_matrix.menu.USBMode.hwcdc.build.usb_mode=1
37917+
ws_esp32_s3_matrix.menu.USBMode.default=USB-OTG (TinyUSB)
37918+
ws_esp32_s3_matrix.menu.USBMode.default.build.usb_mode=0
37919+
37920+
ws_esp32_s3_matrix.menu.CDCOnBoot.default=Disabled
37921+
ws_esp32_s3_matrix.menu.CDCOnBoot.default.build.cdc_on_boot=0
37922+
ws_esp32_s3_matrix.menu.CDCOnBoot.cdc=Enabled
37923+
ws_esp32_s3_matrix.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
37924+
37925+
ws_esp32_s3_matrix.menu.MSCOnBoot.default=Disabled
37926+
ws_esp32_s3_matrix.menu.MSCOnBoot.default.build.msc_on_boot=0
37927+
ws_esp32_s3_matrix.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
37928+
ws_esp32_s3_matrix.menu.MSCOnBoot.msc.build.msc_on_boot=1
37929+
37930+
ws_esp32_s3_matrix.menu.DFUOnBoot.default=Disabled
37931+
ws_esp32_s3_matrix.menu.DFUOnBoot.default.build.dfu_on_boot=0
37932+
ws_esp32_s3_matrix.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
37933+
ws_esp32_s3_matrix.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
37934+
37935+
ws_esp32_s3_matrix.menu.UploadMode.default=UART0 / Hardware CDC
37936+
ws_esp32_s3_matrix.menu.UploadMode.default.upload.use_1200bps_touch=false
37937+
ws_esp32_s3_matrix.menu.UploadMode.default.upload.wait_for_upload_port=false
37938+
ws_esp32_s3_matrix.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
37939+
ws_esp32_s3_matrix.menu.UploadMode.cdc.upload.use_1200bps_touch=true
37940+
ws_esp32_s3_matrix.menu.UploadMode.cdc.upload.wait_for_upload_port=true
37941+
37942+
ws_esp32_s3_matrix.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
37943+
ws_esp32_s3_matrix.menu.PartitionScheme.default.build.partitions=default
37944+
ws_esp32_s3_matrix.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
37945+
ws_esp32_s3_matrix.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
37946+
ws_esp32_s3_matrix.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
37947+
ws_esp32_s3_matrix.menu.PartitionScheme.no_ota.build.partitions=no_ota
37948+
ws_esp32_s3_matrix.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
37949+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
37950+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
37951+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
37952+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
37953+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
37954+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
37955+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
37956+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
37957+
ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
37958+
ws_esp32_s3_matrix.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
37959+
ws_esp32_s3_matrix.menu.PartitionScheme.huge_app.build.partitions=huge_app
37960+
ws_esp32_s3_matrix.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
37961+
ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
37962+
ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
37963+
ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
37964+
ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker=RainMaker 4MB
37965+
ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
37966+
ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
37967+
ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
37968+
ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
37969+
ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
37970+
37971+
ws_esp32_s3_matrix.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
37972+
ws_esp32_s3_matrix.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
37973+
ws_esp32_s3_matrix.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
37974+
ws_esp32_s3_matrix.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
37975+
ws_esp32_s3_matrix.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
37976+
ws_esp32_s3_matrix.menu.PartitionScheme.all_app.upload.maximum_size=4128768
37977+
37978+
ws_esp32_s3_matrix.menu.PartitionScheme.custom=Custom
37979+
ws_esp32_s3_matrix.menu.PartitionScheme.custom.build.partitions=
37980+
ws_esp32_s3_matrix.menu.PartitionScheme.custom.upload.maximum_size=16777216
37981+
37982+
ws_esp32_s3_matrix.menu.CPUFreq.240=240MHz (WiFi)
37983+
ws_esp32_s3_matrix.menu.CPUFreq.240.build.f_cpu=240000000L
37984+
ws_esp32_s3_matrix.menu.CPUFreq.160=160MHz (WiFi)
37985+
ws_esp32_s3_matrix.menu.CPUFreq.160.build.f_cpu=160000000L
37986+
ws_esp32_s3_matrix.menu.CPUFreq.80=80MHz (WiFi)
37987+
ws_esp32_s3_matrix.menu.CPUFreq.80.build.f_cpu=80000000L
37988+
ws_esp32_s3_matrix.menu.CPUFreq.40=40MHz
37989+
ws_esp32_s3_matrix.menu.CPUFreq.40.build.f_cpu=40000000L
37990+
ws_esp32_s3_matrix.menu.CPUFreq.20=20MHz
37991+
ws_esp32_s3_matrix.menu.CPUFreq.20.build.f_cpu=20000000L
37992+
ws_esp32_s3_matrix.menu.CPUFreq.10=10MHz
37993+
ws_esp32_s3_matrix.menu.CPUFreq.10.build.f_cpu=10000000L
37994+
37995+
ws_esp32_s3_matrix.menu.UploadSpeed.921600=921600
37996+
ws_esp32_s3_matrix.menu.UploadSpeed.921600.upload.speed=921600
37997+
ws_esp32_s3_matrix.menu.UploadSpeed.115200=115200
37998+
ws_esp32_s3_matrix.menu.UploadSpeed.115200.upload.speed=115200
37999+
ws_esp32_s3_matrix.menu.UploadSpeed.256000.windows=256000
38000+
ws_esp32_s3_matrix.menu.UploadSpeed.256000.upload.speed=256000
38001+
ws_esp32_s3_matrix.menu.UploadSpeed.230400.windows.upload.speed=256000
38002+
ws_esp32_s3_matrix.menu.UploadSpeed.230400=230400
38003+
ws_esp32_s3_matrix.menu.UploadSpeed.230400.upload.speed=230400
38004+
ws_esp32_s3_matrix.menu.UploadSpeed.460800.linux=460800
38005+
ws_esp32_s3_matrix.menu.UploadSpeed.460800.macosx=460800
38006+
ws_esp32_s3_matrix.menu.UploadSpeed.460800.upload.speed=460800
38007+
ws_esp32_s3_matrix.menu.UploadSpeed.512000.windows=512000
38008+
ws_esp32_s3_matrix.menu.UploadSpeed.512000.upload.speed=512000
38009+
38010+
ws_esp32_s3_matrix.menu.DebugLevel.none=None
38011+
ws_esp32_s3_matrix.menu.DebugLevel.none.build.code_debug=0
38012+
ws_esp32_s3_matrix.menu.DebugLevel.error=Error
38013+
ws_esp32_s3_matrix.menu.DebugLevel.error.build.code_debug=1
38014+
ws_esp32_s3_matrix.menu.DebugLevel.warn=Warn
38015+
ws_esp32_s3_matrix.menu.DebugLevel.warn.build.code_debug=2
38016+
ws_esp32_s3_matrix.menu.DebugLevel.info=Info
38017+
ws_esp32_s3_matrix.menu.DebugLevel.info.build.code_debug=3
38018+
ws_esp32_s3_matrix.menu.DebugLevel.debug=Debug
38019+
ws_esp32_s3_matrix.menu.DebugLevel.debug.build.code_debug=4
38020+
ws_esp32_s3_matrix.menu.DebugLevel.verbose=Verbose
38021+
ws_esp32_s3_matrix.menu.DebugLevel.verbose.build.code_debug=5
38022+
38023+
ws_esp32_s3_matrix.menu.EraseFlash.none=Disabled
38024+
ws_esp32_s3_matrix.menu.EraseFlash.none.upload.erase_cmd=
38025+
ws_esp32_s3_matrix.menu.EraseFlash.all=Enabled
38026+
ws_esp32_s3_matrix.menu.EraseFlash.all.upload.erase_cmd=-e
38027+
3783338028
##############################################################
3783438029

3783538030
waveshare_esp32s3_touch_lcd_128.name=Waveshare ESP32S3 Touch LCD 128

‎variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv

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@@ -0,0 +1,3 @@
1+
# Name, Type, SubType, Offset, Size, Flags
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nvs, data, nvs, 0x9000, 0x5000,
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factory, app, factory, 0x10000, 0x3F0000,

‎variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv

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# Name, Type, SubType, Offset, Size, Flags
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nvs, data, nvs, 0x9000, 0x5000,
3+
otadata, data, ota, 0xE000, 0x2000,
4+
app0, app, ota_0, 0x10000, 0x1F0000,
5+
app1, app, ota_1, 0x200000, 0x1F0000,
6+
coredump, data, coredump, 0x3F0000, 0x10000,

‎variants/ws_esp32_s3_matrix/pins_arduino.h

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@@ -0,0 +1,77 @@
1+
2+
#ifndef Pins_Arduino_h
3+
#define Pins_Arduino_h
4+
5+
#include <stdint.h>
6+
#include "soc/soc_caps.h"
7+
8+
// BN: ESP32 Family Device
9+
#define USB_VID 0x303a
10+
#define USB_PID 0x1001
11+
12+
#define USB_MANUFACTURER "Waveshare"
13+
#define USB_PRODUCT "ESP32-S3-Matrix"
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#define USB_SERIAL ""
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// Onboard 8 x 8 Matrix panel
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#define WS_MATRIX_DIN 14
18+
19+
// Onboard QMI8658 IMU
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#define WS_IMU_SDA 11
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#define WS_IMU_SCL 12
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#define WS_IMU_ADDRESS 0x6B
23+
#define WS_IMU_INT1 10
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#define WS_IMU_INT2 13
25+
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// UART0 pins
27+
static const uint8_t TX = 43;
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static const uint8_t RX = 44;
29+
30+
// Def for I2C that shares the IMU I2C pins
31+
static const uint8_t SDA = 11;
32+
static const uint8_t SCL = 12;
33+
34+
// Mapping based on the ESP32S3 data sheet - alternate for SPI2
35+
static const uint8_t SS = 34; // FSPICS0
36+
static const uint8_t MOSI = 35; // FSPID
37+
static const uint8_t MISO = 37; // FSPIQ
38+
static const uint8_t SCK = 36; // FSPICLK
39+
40+
// Analog capable pins on the header
41+
static const uint8_t A0 = 1;
42+
static const uint8_t A1 = 2;
43+
static const uint8_t A2 = 3;
44+
static const uint8_t A3 = 4;
45+
static const uint8_t A4 = 5;
46+
static const uint8_t A5 = 6;
47+
static const uint8_t A6 = 7;
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// GPIO capable pins on the header
50+
static const uint8_t D0 = 7;
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static const uint8_t D1 = 6;
52+
static const uint8_t D2 = 5;
53+
static const uint8_t D3 = 4;
54+
static const uint8_t D4 = 3;
55+
static const uint8_t D5 = 2;
56+
static const uint8_t D6 = 1;
57+
static const uint8_t D7 = 44;
58+
static const uint8_t D8 = 43;
59+
static const uint8_t D9 = 40;
60+
static const uint8_t D10 = 39;
61+
static const uint8_t D11 = 38;
62+
static const uint8_t D12 = 37;
63+
static const uint8_t D13 = 36;
64+
static const uint8_t D14 = 35;
65+
static const uint8_t D15 = 34;
66+
static const uint8_t D16 = 33;
67+
68+
// Touch input capable pins on the header
69+
static const uint8_t T1 = 1;
70+
static const uint8_t T2 = 2;
71+
static const uint8_t T3 = 3;
72+
static const uint8_t T4 = 4;
73+
static const uint8_t T5 = 5;
74+
static const uint8_t T6 = 6;
75+
static const uint8_t T7 = 7;
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77+
#endif /* Pins_Arduino_h */

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