Replies: 1 comment
-
|
Is going to be done here (#144 ) for Verilog |
Beta Was this translation helpful? Give feedback.
0 replies
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Uh oh!
There was an error while loading. Please reload this page.
-
This can be done by strict compilation rules for Verilator/GHDL after #74
Beta Was this translation helpful? Give feedback.
All reactions