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Merge branch 'main' into serialization
2 parents 21c30b6 + 4b7e12d commit a36d007

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.pre-commit-config.yaml

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@@ -30,7 +30,7 @@ repos:
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args: ["--profile", "black", --line-length=125]
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- repo: https://github.com/asottile/pyupgrade
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rev: v3.19.0
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rev: v3.19.1
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hooks:
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- id: pyupgrade
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args: ["--py36-plus"]

hls4ml/writer/vivado_accelerator_writer.py

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@@ -394,6 +394,8 @@ def write_board_script(self, model):
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f.write('set clock_uncertainty {}\n'.format(model.config.get_config_value('ClockUncertainty', '12.5%')))
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f.write('variable version\n')
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f.write('set version "{}"\n'.format(model.config.get_config_value('Version', '1.0.0')))
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f.write('variable maximum_size\n')
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f.write('set maximum_size {}\n'.format(model.config.get_config_value('MaximumSize', '4096')))
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if self.vivado_accelerator_config.get_interface() == 'axi_stream':
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in_bit, out_bit = self.vivado_accelerator_config.get_io_bitwidth()
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f.write(f'set bit_width_hls_output {in_bit}\n')

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