Updated how Quartus workflow is run

Quartus workflow is now run as a system call in the background and its
log file is read in Matlab until exit is encountered

Additionally less html reports are generated by HDLCoder and it was
updated for the new target names. Additionally the logging module is now
used by the Quartus workflow.

Also fixes were made regarding updating the target from De10 to
Audiomini as compilitation previously was failing from the name change

Author: fe-wickham

vhdl/autogen_quartus.py

@@ -1,15 +1,38 @@
 import argparse
+import sys
+import logging
 
 from dataplane_config import DataplaneConfig
 from quartus.quartus_workflow import execute_quartus_workflow
 
 
-def main(inputFilename, working_dir):
+def main(inputFilename, working_dir, log_to_file=False):
     if not(working_dir.endswith("/")):
         working_dir += "/"
-    dataplane_config = DataplaneConfig.parse_json(inputFilename)
-    execute_quartus_workflow(
-        dataplane_config, working_dir)
+    logger = init_logging(logging.INFO, log_to_file)
+    try:
+        dataplane_config = DataplaneConfig.parse_json(inputFilename)
+        execute_quartus_workflow(
+            dataplane_config.target_system, dataplane_config.custom_components, dataplane_config.clock_rate, working_dir)
+    finally:
+        logger.info("exit")
+
+def init_logging(debugLevel, log_to_file=False):
+    logger = logging.getLogger('autogen_quartus')
+
+    if log_to_file:
+        file_log_handler = logging.FileHandler('autogen_quartus.log', 'w')
+        file_log_handler.setLevel(debugLevel)
+        file_log_handler.setFormatter(logging.Formatter())
+        logger.addHandler(file_log_handler)
+
+    console_handler = logging.StreamHandler()
+    console_handler.setLevel(debugLevel)
+    console_handler.setFormatter(logging.Formatter())
+    logger.addHandler(console_handler)
+
+    logger.setLevel(debugLevel)
+    return logger
 
 def parseargs():
     """
@@ -21,11 +44,13 @@ def parseargs():
                         help="JSON file containing autogen configuration")
     parser.add_argument('-w', '--working-dir',
                         help="Working directory to execute the quartus workflow in")
+    parser.add_argument('-l', '--logging', required=False, action="store_true",
+                        help="Enable logging to autogen_quartus.log")
     args = parser.parse_args()
-    return (args.json, args.working_dir)
+    return (args.json, args.working_dir, args.logging)
 
 
 if __name__ == "__main__":
-    (json_filename, working_dir) = parseargs()
+    (json_filename, working_dir, log_to_file) = parseargs()
 
-    main(json_filename, working_dir)
+    main(json_filename, working_dir, log_to_file)

vhdl/hdlworkflow.m

@@ -3,10 +3,10 @@
 dataplane_name = 'dataplane';
 load_system(model);
 
-if strcmp(mp.target_system,'de10')
+if strcmp(mp.target_system,'audiomini')
     device_family = 'Cyclone V';
     device = '5CSEBA6U23I7';
-elseif strcmp(mp.target_system,'arria10')
+elseif strcmp(mp.target_system,'audioblade')
     device_family = 'Arria 10';
     device = '10AS066H2F34I1HG';
 end
@@ -19,10 +19,10 @@
     'CriticalPathEstimation', 'off', ...
     'GenerateHDLTestBench', 'off', ...
     'HDLCodingStandardCustomizations',hdlcodingstd.IndustryCustomizations(), ...
-    'HDLGenerateWebview', 'on', ...
+    'HDLGenerateWebview', 'off', ...
     'HDLSubsystem', [model '/' dataplane_name], ...
-    'OptimizationReport', 'on', ...
-    'ResourceReport', 'on', ...
+    'OptimizationReport', 'off', ...
+    'ResourceReport', 'off', ...
     'SynthesisTool', 'Altera QUARTUS II', ...
     'SynthesisToolChipFamily', device_family, ...
     'SynthesisToolDeviceName', device, ...

vhdl/quartus/quartus_workflow.py

@@ -3,6 +3,7 @@
 import fileinput
 import sys
 import re
+import logging
 from shutil import copyfile
 from quartus.quartus_templates import quartus_templates
 from quartus.target import Audiomini, Audioblade, Target
@@ -71,7 +72,7 @@ def create_tcl_system_file(target, custom_components, sys_clock_rate_hz, templat
     """
     tcl_file = target.system_name + ".tcl"
 
-    print("Making tcl file for qsys")
+    logger.info("Making tcl file for qsys")
     copyfile(RES_DIR + target.base_qsys_file, working_dir + target.base_qsys_file)
 
     quartus_version = re.search(r'.intelFPGA.(\d+\.\d+)', QUARTUS_BIN_DIR).group(1)
@@ -107,8 +108,9 @@ def run_cmd_and_log(cmd, log_msg, log_file_path, err_on_fail=True):
     ChildProcessError
         Throws error if the command fails
     """
-    print(log_msg)
-    print(cmd.replace("\\", "\\\\"))
+    logger.info(log_msg)
+    logger.info(f"log file can be found at {log_file_path}")
+    logger.info(cmd.replace("\\", "\\\\"))
     with open(log_file_path, "w") as log_file:
         process = subprocess.Popen(cmd,
                                    stdout=log_file,
@@ -170,7 +172,7 @@ def gen_qsys_system(target, custom_components, sys_clock_rate_hz, template, work
     """
     ipx_file = "components.ipx"
     copyfile(RES_DIR + ipx_file, working_dir + ipx_file)
-    
+
     if not(system_exists(target.system_name, working_dir)):
         gen_qsys_file(target, custom_components, sys_clock_rate_hz, template, working_dir)
     gen_qsys_system_from_qsys_file(target.system_name, working_dir)
@@ -212,7 +214,8 @@ def gen_project_tcl(project_name, target, template, working_dir):
     top_level_vhdl_file = target.top_level_vhdl_file
     original_system = target.original_system
 
-    print("Generating make_project.tcl")
+    logger.info("Generating make_project.tcl")
+    
     with open(working_dir + "make_project.tcl", "w") as proj_file:
         proj_file.write(template.add_quartus_project(
             project_name, target))
@@ -244,7 +247,7 @@ def gen_pll_qsys(working_dir):
 
 def project_with_revision_exists(project_name, project_revision, working_dir):
     try:
-        with open(working_dir + project_name, "r") as project_file:
+        with open(working_dir + project_name + ".qpf", "r") as project_file:
             for line in project_file:
                 if f"PROJECT_REVISION = \"{project_revision}\"" in line:
                     return True
@@ -273,10 +276,9 @@ def gen_project(project_name, target, template, working_dir):
 
 def compile_project(project_name, project_revision, template, working_dir):
     tcl_file = "compile_project.tcl"
-    if not(os.path.isfile(working_dir + tcl_file)):
-        with open(working_dir + tcl_file, "w") as compile_file:
-            compile_file.write(template.add_quartus_compile_project(
-                project_name, project_revision))
+    with open(working_dir + tcl_file, "w") as compile_file:
+        compile_file.write(template.add_quartus_compile_project(
+            project_name, project_revision))
 
     log_msg = "Compiling project"
     cmd = f"cd {working_dir} && {QUARTUS_BIN_DIR}quartus_sh -t {tcl_file}"
@@ -301,6 +303,9 @@ def gen_rbf(working_dir, target_system):
 
     run_cmd_and_log(cmd, log_msg, log_file_path)
 
+def init_logging():
+    global logger
+    logger = logging.getLogger('autogen_quartus')
 
 def execute_quartus_workflow(target_system, custom_components, sys_clock_rate_hz, working_dir=""):
     """Executes quartus workflow that creates a system and project, compiles it,
@@ -313,6 +318,7 @@ def execute_quartus_workflow(target_system, custom_components, sys_clock_rate_hz
     working_dir : str, optional
         Working directory of the generation process, by default ""
     """
+    init_logging()
     target = None
 
     if(target_system == "audiomini"):
@@ -322,7 +328,7 @@ def execute_quartus_workflow(target_system, custom_components, sys_clock_rate_hz
     else:
         raise ValueError(
             f"The provided target: {target_system} is not supported")
-
+    
     abspath = os.path.abspath(__file__)
     dname = os.path.dirname(abspath)
     global RES_DIR

vhdl/quartus/res/Audiomini_System.vhd renamed to vhdl/quartus/res/Audiomini.vhd

@@ -17,7 +17,7 @@ USE altera.altera_primitives_components.all;
 -- Signal Names are defined in the DE10-Nano User Manual
 -- http://de10-nano.terasic.com
 -----------------------------------------------------------
- entity DE10Nano_System is
+ entity Audiomini is
 	port(
 		----------------------------------------
 		--  CLOCK Inputs
@@ -198,11 +198,11 @@ USE altera.altera_primitives_components.all;
 		HPs_USB_NXT					: in STD_LOGIC
 
 	);
-end entity DE10Nano_System;
+end entity Audiomini;
 
 
 
-architecture DE10Nano_arch of DE10Nano_System is
+architecture Audiomini_arch of Audiomini is
 
 
    --------------------------------------------------------------
@@ -560,4 +560,4 @@ begin
 	ADC_CONVST	      <= '0'; 				
   ADC_SCK			      <= '0';			
 	ADC_SDI			      <= '0';		
-end architecture DE10Nano_arch;
+end architecture Audiomini_arch;

vhdl/quartus/res/audiomini_proj.tcl

@@ -516,7 +516,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Audio_Mini_GPIO_0[33
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Audio_Mini_GPIO_1[12]
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CSEBA6U23I7
-set_global_assignment -name TOP_LEVEL_ENTITY Audiomini_System
+set_global_assignment -name TOP_LEVEL_ENTITY Audiomini
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

vhdl/quartus/target.py

@@ -7,9 +7,9 @@
 
 Audiomini = Target(name='audiomini', system_name='audiomini_system', device_family='Cyclone V',
               device='5CSEBA6U23I7', base_qsys_file='soc_base_system.qsys', base_proj_tcl_file='audiomini_proj.tcl',
-              files_list=['audiominiNano_System.vhd',
+              files_list=['Audiomini.vhd',
                           'audiomini_system/synthesis/audiomini_system.qip'],
-              top_level_vhdl_file='audiomini_System.vhd', original_system='soc_system', base_address='20', axi_master_name='hps.h2f_lw_axi_master',
+              top_level_vhdl_file='Audiomini.vhd', original_system='soc_system', base_address='20', axi_master_name='hps.h2f_lw_axi_master',
               audio_in='FE_Qsys_AD1939_Audio_Mini_v1_0.Line_In', audio_out='FE_Qsys_AD1939_Audio_Mini_v1_0.Headphone_Out',
               clock_name='clk_hps'
               )

vhdl/vgenQuartus.m

@@ -89,16 +89,44 @@
 
 %% Generate the .tcl script to be used by Platform Designer in Quartus
 disp('vgen: Creating .tcl script for Platform Designer.')
-infile = [avalon.entity '.json'];
+config_file = [avalon.entity '.json'];
 % NOTE: platform designer only adds components if they have the _hw.tcl suffix
 outfile = [hdlpath filesep avalon.entity '_avalon_hw.tcl'];
-disp(['file ' infile ' out ' outfile ' path ' hdlpath])
-vgenHwTcl(infile, outfile, hdlpath)
+disp(['file ' config_file ' out ' outfile ' path ' hdlpath])
+vgenHwTcl(config_file, outfile, hdlpath)
 
 disp(['      created tcl file: ' outfile])
 
 disp('vgen: Executing Quartus workflow')
-vgenQuartus(infile, hdlpath + "/quartus/")
+if ispc; second_cmd = "&"; else; second_cmd = ";"; end
+working_dir = hdlpath + "/quartus/";
+quartus_workflow_cmd = "python " + mp.vhdl_codegen_path + "/autogen_quartus.py -j " + config_file ...
+    + " -w " + working_dir + " -l " + second_cmd + " exit &";
+disp(quartus_workflow_cmd)
+system(quartus_workflow_cmd);
+
+fid = fopen("autogen_quartus.log");
+if fid>0
+    % loop until end of file is reached
+    while 1
+        % read the current line
+        where = ftell(fid);
+        line = fgetl(fid);
+        % Print file until exit is encountered
+        if line == -1
+            pause(20/1000)
+            fseek(fid, where, 'bof');
+        elseif line == "exit"
+            break
+        else
+            disp(line)
+        end
+    end
+    % close the file
+    fclose(fid);
+end
+
+%disp("r: ---------------------------------------------------\n" + r)
 disp('Executed Quartus workflow')
 
 %% Generate the device driver code
@@ -114,10 +142,6 @@
 disp(['      created Kbuild: ' [hdlpath filesep 'Kbuild']])
 
 %% Build kernel module
-% TODO: this needs to be platform independent, but how? Our Windows users 
-%       use a virtual machine to compile the device driver, but that
-%       won't automate very well. Maybe we can build the kernel module 
-%       with Quartus' embedded command shell instead?
 disp('Building kernel module.')
 cd(hdlpath)
 if ispc
@@ -136,12 +160,14 @@
 
 % TODO: this file now generates C code, but "vgen" make it seem like it is just VHDL still. This should be changed, and the repository should be reorganized a bit. 
 %       This file shouldn't live in the vhdl folder anymore.
+%% Build Device Tree blob
 project_revision = mp.model_name + "_" + mp.target_system;
-try
-    py.generate.generate_device_tree_overlay(hdlpath + "/quartus/" + mp.target_system + '_system.sopcinfo', project_revision + '.rbf')
-catch e
-    disp(getReport(e))
-end
+sopcinfo_file = hdlpath + "/quartus/" + mp.target_system + '_system.sopcinfo';
+disp("Generating device tree source file")
+disp("python " + mp.dtogen_path + filesep + "dtogen -s " + sopcinfo_file + " -r " + project_revision + " -o " + hdlpath)
+system("python " + mp.dtogen_path + filesep + "dtogen -s " + sopcinfo_file + " -r " + project_revision + " -o " + hdlpath);
+
+disp("Compiling device tree source file")
 
 if ispc
     if system('wsl.exe cd') == 0