24.23 support on AM, updated driver name, etc (#54)

* 24.23 support on AM, updated driver name, etc

AD1939 sending 24.23 format is supported on Audiomini
Driver path in sysfs is now /sys/class/fe_devicename/fe_devicenameminor#/, where minor# is generally going to be 0
Registers no longer are assumed to have register_control in front of them, so register names in model must match model.json instead of register_control_regname

In progress on support for avalon wrapper handling registers that are outputs rather than inputs

Fixed issues with regenerating a model that has an existing project but on a new target

* Updated device driver generation to no longer use fe prefix as well as no longer hardcoding prefix everywhere

* Fixed {Driver_Prefix} not being substituted out on the generated file

* 0 register support, slave address size being inconsistent fixed, and baseAddr updated to 0x40

Slave address was being calculated with log 10 instead of log2 in dataplane_config.py
After fixing slave address issue and attempting to generate sound_effects model, Platform Designer
insisted that the base address be 0x00 or 0x40 instead of 0x20.

Author: fe-wickham

device_drivers/device.py

@@ -20,7 +20,7 @@
 #     Bozeman, MT 59718
 #     [email protected]
 
-from device_drivers.device import DeviceType
+from device_drivers.device import DeviceType, DRIVER_PREFIX
 
 class DataType:
     """Represent a fixed point number."""
@@ -137,7 +137,7 @@ def create_read_func(self, device_name):
             Returns C function definition for reading the attribute value
         """
         c_code = "static ssize_t " + self.name + "_read(struct device *dev, struct device_attribute *attr, char *buf) {\n"
-        c_code += "  fe_" + device_name + "_dev_t * devp = (fe_" + device_name + "_dev_t *)dev_get_drvdata(dev);\n"
+        c_code += f"  {DRIVER_PREFIX}_{device_name}_dev_t * devp = ({DRIVER_PREFIX}_{device_name}_dev_t *)dev_get_drvdata(dev);\n"
         if self.data_type.name == "string":
             c_code += self._read_string()
         else:
@@ -244,7 +244,7 @@ def create_write_func(self, device_name):
         c_code += "  char substring[80];\n"
         c_code += "  int substring_count = 0;\n"
         c_code += "  int i;\n"
-        c_code += "  fe_" + device_name + "_dev_t *devp = (fe_" + device_name + \
+        c_code += f"  {DRIVER_PREFIX}_{device_name}_dev_t *devp = ({DRIVER_PREFIX}_" + device_name + \
                         "_dev_t *)dev_get_drvdata(dev);\n"
         c_code += "  for (i = 0; i < count; i++) {\n"
         c_code += "    if ((buf[i] != ',') && (buf[i] != ' ') && (buf[i] != '\\0') && (buf[i] != '\\r') && (buf[i] != '\\n')) {\n"
@@ -329,7 +329,7 @@ def create_write_func(self, device_name, device_name_abbrev):
                 c_code += ","
         c_code += "};\n"
         c_code += "  uint8_t code = 0x00;\n"
-        c_code += "  fe_" + device_name + "_dev_t * devp = (fe_" + device_name + \
+        c_code += f"  {DRIVER_PREFIX}_{device_name}_dev_t * devp = ({DRIVER_PREFIX}_" + device_name + \
                         "_dev_t *) dev_get_drvdata(dev);\n"
         c_code += "  for (i = 0; i < count; i++) {\n"
         c_code += "    if ((buf[i] != ',') && (buf[i] != ' ') && (buf[i] != '\\0') && (buf[i] != '\\r') && (buf[i] != '\\n')) {\n"
@@ -399,7 +399,7 @@ def create_write_func(self, device_name, device_name_abbrev):
                 c_code += ","
         c_code += "};\n"
         c_code += "  uint8_t code = 0x00;\n"
-        c_code += "  fe_" + device_name + "_dev_t * devp = (fe_" + device_name + \
+        c_code += f"  {DRIVER_PREFIX}_{device_name}_dev_t * devp = ({DRIVER_PREFIX}_" + device_name + \
                         "_dev_t *) dev_get_drvdata(dev);\n"
         c_code += "  for (i = 0; i < count; i++) {\n"
         c_code += "    if ((buf[i] != ',') && (buf[i] != ' ') && (buf[i] != '\\0') && (buf[i] != '\\r') && (buf[i] != '\\n')) {\n"

device_drivers/device_attributes.py

@@ -61,14 +61,16 @@ def parse_json(config_filepath):
         json_registers = modeljson['devices'][0]["registers"]
         registers = []
         for reg in json_registers:
+            direction = reg.get("direction") or "in"
             registers.append(Register(
                 reg["name"],
                 DataType(
                     reg["dataType"]["wordLength"],
                     reg["dataType"]["fractionLength"],
                     reg["dataType"]["signed"]
                     ),
-                reg["defaultValue"]
+                reg["defaultValue"],
+                direction
             ))
         entity_name = modeljson['devices'][0]["name"] + "_dataplane"
         is_sample_based = modeljson['system']['processing'].lower() == "sample"

ipcore/avalon_config.py

@@ -39,28 +39,28 @@ def generate_avalon_wrapper(registers, audio_in, audio_out, entity_name, working
     working_dir : str, optional
         Directory to output avalon wrapper to, by default "" which is the current directory
     """
-    avalon_in_data_type = AD1939_DATA_TYPE
-    avalon_out_data_type = AD1939_DATA_TYPE
+    avalon_in_data_type = audio_in.data_type
+    avalon_out_data_type = audio_out.data_type
     if len(registers) == 0:
         addr_width = 0
     else:
         addr_width = int(ceil(log(len(registers), 2)))
     if addr_width == 0 and len(registers) == 1:
         addr_width = 1
     channel_in_width = int(ceil(log(audio_in.channel_count, 2)))
-    print(channel_in_width)
+    
     channel_out_width = int(ceil(log(audio_out.channel_count, 2)))
 
     avalon_entity_ports = [
         Port(PortDir.In, Signal("clk")),
         Port(PortDir.In, Signal("reset")),
         Port(PortDir.In, Signal("avalon_sink_valid")),
-        Port(PortDir.In, Signal("avalon_sink_data", 32,
+        Port(PortDir.In, Signal("avalon_sink_data", audio_in.data_type.word_len,
                                 None, "std_logic_vector", avalon_in_data_type)),
         Port(PortDir.In, Signal("avalon_sink_channel", channel_in_width, None, "std_logic_vector")),
         Port(PortDir.In, Signal("avalon_sink_error", 2)),
         Port(PortDir.Out, Signal("avalon_source_valid")),
-        Port(PortDir.Out, Signal("avalon_source_data", 32,
+        Port(PortDir.Out, Signal("avalon_source_data", audio_out.data_type.word_len,
                                  None, "std_logic_vector", avalon_out_data_type)),
         Port(PortDir.Out, Signal("avalon_source_channel", channel_out_width, None, "std_logic_vector")),
         Port(PortDir.Out, Signal("avalon_source_error", 2)),
@@ -93,12 +93,11 @@ def generate_avalon_wrapper(registers, audio_in, audio_out, entity_name, working
         for reg in registers]
     dataplane_signals = create_dataplane_signals(
         audio_in, audio_out, is_sample_based)
-    register_prefix = "register_control_"
     register_ports = [
         Port(
-            PortDir.In,
+            PortDir.Out if reg.direction == "out" else PortDir.In,
             Signal(
-                register_prefix + reg.name,
+                reg.name.replace(" ", "_"),
                 reg.data_type.word_len,
                 None,
                 "std_logic" if reg.data_type.word_len == 1 else "std_logic_vector",
@@ -214,7 +213,7 @@ def create_dataplane_port_map(dataplane, entity, registers, register_signals, ar
         reg_signal = next(
             port for port in register_signals if port.name == reg.name)
         port_map[dataplane.get_port(
-            f"register_control_{reg.name}")] = reg_signal
+        reg.name)] = reg_signal
     return PortMap(f"u_{dataplane.name}", port_map, dataplane)
 
 
@@ -277,8 +276,10 @@ def create_bus_read_logic(register_signals, avalon_slave_readdata_signal):
     logic_string += tab() + \
         f"if rising_edge(clk) and {read_enable} = '1' then \n"
     logic_string += tab(2) + f"case {avalon_slave_address} is\n"
-
-    addr_width = int(ceil(log(len(register_signals), 2)))
+    try:
+        addr_width = int(ceil(log(len(register_signals), 2)))
+    except ValueError:
+        addr_width = 0
     for idx, reg in enumerate(register_signals):
         addr = "{0:0{1}b}".format(idx, addr_width)
         assignment = data_out.generate_assignment(reg)
@@ -291,13 +292,13 @@ def create_bus_read_logic(register_signals, avalon_slave_readdata_signal):
     return logic_string
 
 
-def create_bus_write_logic(register_signals, avalon_slave_writedata_signal):
+def create_bus_write_logic(register_ports, avalon_slave_writedata_signal):
     """Create VHDL logic to write to dataplane registers.
 
     Parameters
     ----------
-    register_signals : list of Signal
-        Signals connected to dataplane registers
+    register_ports : list of Port
+        Ports connected to dataplane registers
     avalon_slave_writedata_signal : Signal
         Signal that the avalon writes data to
 
@@ -312,7 +313,7 @@ def create_bus_write_logic(register_signals, avalon_slave_writedata_signal):
 
     logic_string = ""
     logic_string += tab() + f"if reset = '1' then \n"
-    for reg in register_signals:
+    for reg in register_ports:
         data_type = reg.underlying_data_type
         default_bit_string = num_to_bitstring(
                 reg.default_value, data_type.word_len, data_type.frac_len)
@@ -323,8 +324,13 @@ def create_bus_write_logic(register_signals, avalon_slave_writedata_signal):
         f"elsif rising_edge(clk) and {write_enable} = '1' then\n"
     logic_string += tab(2) + f"case {avalon_slave_address} is\n"
 
-    addr_width = int(ceil(log(len(register_signals), 2)))
-    for idx, reg in enumerate(register_signals):
+    try:
+        addr_width = int(ceil(log(len(register_ports), 2)))
+    except ValueError:
+        addr_width = 0
+    for idx, reg in enumerate(register_ports):
+        # if(reg.direction == PortDir.Out):
+        #     continue
         addr = "{0:0{1}b}".format(idx, addr_width)
         assignment = reg.generate_assignment(data_in)
         logic_string += tab(3) + f"when \"{addr}\" => {assignment}"

ipcore/avalon_wrapper.py

@@ -21,6 +21,8 @@ def __init__(self):
 
         self.sink_max_channel = 0
         self.source_max_channel = 0
+        self.sink_bits_per_symbol = 24
+        self.source_bits_per_symbol = 24
 
     def populate_additional_filesets(self, additionalFilesetAbsDir, sourceFilePatterns):
         for pattern in sourceFilePatterns:
@@ -53,10 +55,12 @@ def parse_json(inputFilename, deviceIndex=0):
         if len(model.devices[deviceIndex].registers) > 0:
             config.has_avalon_mm_slave_signal = True
             config.address_bus_size = int(
-                ceil(log(len(model.devices[deviceIndex].registers))))
+                ceil(log(len(model.devices[deviceIndex].registers), 2)))
 
         config.sink_max_channel = model.system.audioIn.numberOfChannels - 1
         config.source_max_channel = model.system.audioOut.numberOfChannels - 1
+        config.sink_bits_per_symbol = model.system.audioIn.wordLength
+        config.source_bits_per_symbol = model.system.audioOut.wordLength
         return config
 
 

ipcore/dataplane_config.py

@@ -20,6 +20,9 @@ def __init__(self, dataplane_config):
         self.sink_max_channel = dataplane_config.sink_max_channel
         self.source_max_channel = dataplane_config.source_max_channel
 
+        self.sink_bits_per_symbol = dataplane_config.sink_bits_per_symbol
+        self.source_bits_per_symbol = dataplane_config.source_bits_per_symbol
+
     def write_tcl(self, outputFilename):
         with open(outputFilename, "w") as out_file:
             out_file.write(self.generate())
@@ -128,8 +131,9 @@ def create_connection_point_reset(self):
 
 
     def create_mm_connection_point(self):
-        if not self.has_avalon_mm_slave_signal:
-            return ""
+        # Even if no memory, the interface is still needed
+        #if not self.has_avalon_mm_slave_signal:
+        #    return ""
         tcl = ""
         memory_slave = 'avalon_slave'
         tcl += "add_interface " + memory_slave + " avalon end\n"
@@ -189,7 +193,7 @@ def create_sink_connection_point(self):
         tcl += "set_interface_property " + sink + " associatedClock clock\n"
         tcl += "set_interface_property " + sink + " associatedReset reset\n"
         tcl += "set_interface_property " + sink + \
-            " dataBitsPerSymbol " + str(self.data_bus_size) + "\n"
+            " dataBitsPerSymbol " + str(self.sink_bits_per_symbol) + "\n"
         tcl += "set_interface_property " + sink + " errorDescriptor \"\"\n"
         tcl += "set_interface_property " + \
             sink + " firstSymbolInHighOrderBits true\n"
@@ -203,7 +207,7 @@ def create_sink_connection_point(self):
             sink + " CMSIS_SVD_VARIABLES \"\"\n"
         tcl += "set_interface_property " + sink + " SVD_ADDRESS_GROUP \"\"\n"
         tcl += "add_interface_port " + sink + " avalon_sink_valid valid Input 1\n"
-        tcl += "add_interface_port " + sink + " avalon_sink_data data Input 32\n"
+        tcl += f"add_interface_port {sink} avalon_sink_data data Input {self.sink_bits_per_symbol}\n"
         tcl += f"add_interface_port {sink} avalon_sink_channel channel Input {int(ceil(log(self.sink_max_channel + 1, 2))) or 1}\n"
         tcl += "add_interface_port " + sink + " avalon_sink_error error Input 2\n"
         tcl += "\n\n\n"
@@ -217,7 +221,7 @@ def create_source_connection_point(self):
         tcl += "set_interface_property " + source + " associatedClock clock\n"
         tcl += "set_interface_property " + source + " associatedReset reset\n"
         tcl += "set_interface_property " + source + \
-            " dataBitsPerSymbol " + str(self.data_bus_size) + "\n"
+            " dataBitsPerSymbol " + str(self.source_bits_per_symbol) + "\n"
         tcl += "set_interface_property " + source + " errorDescriptor \"\"\n"
         tcl += "set_interface_property " + \
             source + " firstSymbolInHighOrderBits true\n"
@@ -232,7 +236,7 @@ def create_source_connection_point(self):
         tcl += "set_interface_property " + source + " SVD_ADDRESS_GROUP \"\"\n"
 
         tcl += "add_interface_port " + source + " avalon_source_valid valid Output 1\n"
-        tcl += "add_interface_port " + source + " avalon_source_data data Output 32\n"
+        tcl += f"add_interface_port {source} avalon_source_data data Output {self.source_bits_per_symbol}\n"
         tcl += f"add_interface_port {source} avalon_source_channel channel Output {int(ceil(log(self.source_max_channel + 1, 2))) or 1}\n"
         tcl += "add_interface_port " + source + " avalon_source_error error Output 2\n"
         tcl += "\n\n\n"

ipcore/hw_tcl_generator.py

@@ -1,7 +1,7 @@
 from math import fabs
 import collections
 
-Register = collections.namedtuple('Register', ['name', 'data_type', 'default'])
+Register = collections.namedtuple('Register', ['name', 'data_type', 'default', 'direction'])
 Audio = collections.namedtuple('Audio', ['data_type', 'channel_count', 'dual'])
 DataType = collections.namedtuple(
     'DataType', ['word_len', 'frac_len', 'signed'])

ipcore/util.py

@@ -27,8 +27,8 @@
 load_package flow
 
 if [project_exists $project] {
-    project_open $project
-    create_revision $revision
+    project_open -force -current_revision $project
+    create_revision -set_current $revision
 } else {
     project_new $project -revision ${revision} -overwrite
 }
@@ -60,7 +60,7 @@
 class QuartusTemplates:
     """Generate templates for Quartus workflow."""
 
-    def __init__(self, num_custom_components, baseAddress=20):
+    def __init__(self, num_custom_components, baseAddress=40):
         """Initialize QuartusTemplates.
 
         Parameters