0.0.2

- (#25) - Correct issue passing string-type parameters

Signed-off-by: Matthew Ballance <[email protected]>

Author: mballance

doc/ChangeLog.md

@@ -0,0 +1,5 @@
+
+## 0.0.2
+- (#25) - Correct issue passing string-type parameters
+
+

setup.py

@@ -6,7 +6,7 @@
 import sysconfig
 from setuptools import Extension, setup, find_namespace_packages
 
-version="0.0.1"
+version="0.0.2"
 
 proj_dir = os.path.dirname(os.path.abspath(__file__))
 pythondir = os.path.join(proj_dir, "src")

src/hdl_if/impl/call/gen_sv_class.py

@@ -512,7 +512,7 @@ def py2sv_func(self, type):
             ctypes.c_uint16 : "PyLong_AsLong",
             ctypes.c_uint32 : "PyLong_AsLong",
             ctypes.c_uint64 : "PyLong_AsUnsignedLongLong",
-            str : "string",
+            str : "PyUnicode_AsUTF8",
             ctypes.py_object : ""
         }
         if type not in type_m.keys():
@@ -534,7 +534,7 @@ def sv2py_func(self, type, var):
             ctypes.c_uint16 : "PyLong_FromLong",
             ctypes.c_uint32 : "PyLong_FromLong",
             ctypes.c_uint64 : "PyLong_FromUnsignedLongLong",
-            str : "string"
+            str : "PyUnicode_FromString"
         }
         if type in type_m.keys():
             return "pyhdl_if::%s(%s)" % (type_m[type], var)

tests/unit/data/test_smoke_str/call_sv_bfm.py

@@ -0,0 +1,50 @@
+
+import ctypes as ct
+import hdl_if as hif
+
+@hif.api
+class WishboneInitiator(object):
+
+    @hif.imp
+    async def is_eq_hello(self, val : str) -> ct.c_bool:
+        pass
+
+    @hif.imp
+    async def write(self, addr : ct.c_uint32, data : ct.c_uint32):
+        pass
+
+    @hif.imp
+    async def read(self, addr : ct.c_uint32) -> ct.c_uint32:
+        pass
+
+@hif.api
+class Test(object):
+
+    @hif.exp
+    async def run(self, bfm : ct.py_object):
+        errors = 0
+        print("run")
+
+        for i in range(64):
+            wr_val = (i+1)
+            print(f'[Py] writing: {wr_val}')
+            await bfm.write(0x8000_0000+(4*i), wr_val)
+            rd = await bfm.read(0x8000_0000+(4*i))
+            print(f'[Py] readback: {rd}')
+            if wr_val != rd:
+                errors += 1
+        
+        is_eq_1 = await bfm.is_eq_hello("hello")
+        is_eq_2 = await bfm.is_eq_hello("goodbye")
+        print("is_eq_1: %s" % is_eq_1, flush=True)
+        print("is_eq_2: %s" % is_eq_2, flush=True)
+
+        if not is_eq_1:
+            errors += 1
+
+        if is_eq_2:
+            errors += 1
+
+        with open("status.txt", "w") as fp:
+            fp.write("%s: %d errors\n" % (("PASS" if errors==0 else "FAIL"), errors))
+

tests/unit/data/test_smoke_str/call_sv_bfm.sv

@@ -0,0 +1,61 @@
+
+module call_sv_bfm;
+    import pyhdl_if::*;
+    import call_sv_bfm_pkg::*;
+
+    reg clk = 0;
+    reg reset = 1;
+    initial begin
+
+        clk = 0;
+        forever begin
+            #10ns;
+            clk = ~clk;
+        end
+    end
+
+    wire[31:0] dat_r, dat_w;
+    wire[31:0] adr;
+    wire stb, cyc, we;
+    reg  ack_r;
+    wire ack = (ack_r && cyc && stb);
+
+    always @(posedge clk or reset) begin
+        if (reset) begin
+            ack_r <= 1'b0;
+        end else begin
+            ack_r <= (stb & cyc);
+        end
+    end
+
+    assign dat_r = dat_w;
+
+    WishboneInitiatorBFM    init_bfm(
+        .clock(clk),
+        .reset(reset),
+        .adr(adr),
+        .dat_r(dat_r),
+        .dat_w(dat_w),
+        .stb(stb),
+        .cyc(cyc),
+        .ack(ack),
+        .we(we)
+    );
+
+    initial begin
+        automatic Test test;
+
+        pyhdl_if_start();
+
+        #50ns;
+        reset = 0;
+
+        // Create an instance of the Test class and run
+        $display("%0t --> run", $time);
+        test = new();
+        test.run(init_bfm.m_api_obj.m_obj);
+        $display("%0t <-- run", $time);
+        $finish;
+    end
+
+endmodule

tests/unit/data/test_smoke_str/wb_init_bfm.sv

@@ -0,0 +1,124 @@
+
+module WishboneInitiatorBFM(
+    input           clock,
+    input           reset,
+    output reg[31:0]        adr,
+    output reg[31:0]        dat_w,
+    input[31:0]             dat_r,
+    output                  cyc,
+    input                   err,
+    output reg[3:0]         sel,
+    output                  stb,
+    input                   ack,
+    output reg              we
+);
+    import call_sv_bfm_pkg::*;
+
+    reg [31:0]      bfm_dat_w, bfm_dat_r, bfm_adr;
+    reg[3:0]        bfm_sel;
+    reg             bfm_we, bfm_req, bfm_ack;
+    reg             state;
+    assign stb = (state == 1'b1);
+    assign cyc = (state == 1'b1);
+    always @(posedge clock or reset) begin
+        if (reset) begin
+            bfm_dat_w = {32{1'b0}};
+            bfm_dat_r = {32{1'b0}};
+            bfm_adr = {32{1'b0}};
+            bfm_sel = {4{1'b0}};
+            bfm_we = 1'b0;
+            bfm_req = 1'b0;
+            bfm_ack = 1'b0;
+            state <= 1'b0;
+        end else begin
+            case (state)
+                1'b0: begin
+                    if (bfm_req) begin
+                        sel <= bfm_sel;
+                        we <= bfm_we;
+                        adr <= bfm_adr;
+                        dat_w <= bfm_dat_w;
+                        bfm_req = 0;
+                        state <= 1'b1;
+                    end
+                end
+                1'b1: begin
+                    if (cyc && stb && ack) begin
+                        bfm_dat_r = dat_r;
+                        bfm_ack = 1;
+                        state <= 1'b0;
+                    end
+                end
+            endcase
+        end
+    end
+
+
+    task bfm_write(int unsigned adr_v, int unsigned dat_v);
+        while (bfm_req === 1'b1) begin
+            @(posedge clock);
+        end
+        bfm_adr = adr_v;
+        bfm_we = 1'b1;
+        bfm_sel = {4{1'b1}};
+        bfm_dat_w = dat_v;
+        bfm_req = 1'b1;
+        while (bfm_ack === 1'b0) begin
+            @(posedge clock);
+        end
+        bfm_ack = 1'b0;
+    endtask
+
+    task bfm_read(output int unsigned dat_v, input int unsigned adr_v);
+        while (bfm_req === 1'b1) begin
+            @(posedge clock);
+        end
+        bfm_adr = adr_v;
+        bfm_we = 1'b0;
+        bfm_sel = {4{1'b0}};
+        //bfm_dat_w = {32{1'b0}}; // commented out to persist value
+        bfm_req = 1'b1;
+        while (bfm_ack === 1'b0) begin
+            @(posedge clock);
+        end
+        dat_v = bfm_dat_r;
+        bfm_ack = 1'b0;
+    endtask
+
+    class WishboneInitiatorImpl extends WishboneInitiator;
+        virtual task write(int unsigned addr, int unsigned data);
+            $display("write");
+            $display("--> write");
+            bfm_write(addr, data);
+            $display("<-- write");
+            #10ns;
+        endtask
+
+        virtual task read(output int unsigned retval, input int unsigned addr);
+            $display("--> read");
+            bfm_read(retval, addr);
+            $display("<-- read (addr,data): %0d,%0d ", addr, retval);
+        endtask
+
+        virtual task is_eq_hello(output bit __retval, input string val);
+            $display("is_eq_hello: %0s", val);
+            if (val == "hello") begin
+                $display("eq");
+                __retval = 1'b1;
+            end else begin
+                $display("neq");
+                __retval = 1'b0;
+            end
+        endtask
+
+    endclass
+
+    WishboneInitiatorImpl       m_api_obj;
+
+    // Register ourselves with the PyHDL-IF object registry
+    initial begin : init
+        m_api_obj = new();
+        $display("Path: %m");
+        pyhdl_if::pyhdl_if_registerObject(m_api_obj.m_obj, $sformatf("%m"), 1);
+    end
+endmodule

tests/unit/test_smoke.py

@@ -14,6 +14,7 @@
     os.path.dirname(os.path.abspath(__file__)),
     "data")
 test_smoke_data_dir = os.path.join(data_dir, "test_smoke")
+test_smoke_str_data_dir = os.path.join(data_dir, "test_smoke_str")
 
 
 def test_smoke(dirconfig : pfv.DirConfig):
@@ -57,3 +58,43 @@ def test_smoke(dirconfig : pfv.DirConfig):
 
         assert status.startswith("PASS:")
 
+def test_smoke_str(dirconfig : pfv.DirConfig):
+    flow = pfv.FlowSim(dirconfig)
+
+    print("test_smoke_data_dir: %s" % test_smoke_str_data_dir, flush=True)
+
+    flow.addTaskToPhase("generate.main", pfv.TaskCmd("gen-api",
+        cmd=[sys.executable, "-m", "hdl_if", "api-gen-sv", "-m", "call_sv_bfm",
+        "--package", "call_sv_bfm_pkg", "-o", "call_sv_bfm_pkg.sv"],
+        env=[pfv.EnvAction.prepend_path("PYTHONPATH", test_smoke_str_data_dir)],
+        cwd=dirconfig.builddir()
+    ))
+    flow.fs.add_library(hdl_if.share())
+    flow.sim.addFileset(pfv.FSVlnv("fvutils::pyhdl-if", "systemVerilogSource"))
+
+    flow.sim.addFileset(pfv.FSPaths(
+        dirconfig.builddir(),
+        ["call_sv_bfm_pkg.sv"],
+        "systemVerilogSource"))
+
+    flow.sim.addFileset(pfv.FSPaths(
+        test_smoke_str_data_dir,
+        ["wb_init_bfm.sv", "call_sv_bfm.sv"],
+        "systemVerilogSource"))
+    
+    flow.sim.dpi_libs.append(hdl_if.get_entry())
+    flow.sim.top.add("call_sv_bfm")
+
+    run_args = flow.sim.mkRunArgs(dirconfig.rundir())
+    run_args.prepend_pathenv("PYTHONPATH", test_smoke_str_data_dir)
+    flow.addTaskToPhase("run.main", flow.sim.mkRunTask(run_args))
+
+    if dirconfig.config.getHdlSim() in SKIP_HDLSIM:
+        pytest.skip("Unsupported simulator %s" % dirconfig.config.getHdlSim())
+    else:
+        flow.run_all()
+
+        with open(os.path.join(dirconfig.rundir(), "status.txt"), "r") as fp:
+            status = fp.read().strip()
+
+        assert status.startswith("PASS:")