Merge pull request #2 from Rainmannn/main

对AUIPC指令及LUI指令译码的修改

Author: github-3rr0r

src/main/scala/rv32isc/Alu.scala

@@ -27,8 +27,15 @@ class Alu extends Module {
     // 用于得到操作数
     val oprand1 = WireDefault(0.U(DATA_WIDTH.W))
     val oprand2 = WireDefault(0.U(DATA_WIDTH.W))
-
-    oprand1 := Mux(io.bundleAluControl.ctrlJAL, io.pc, io.dataRead1)
+    //新增 corrected
+    when(io.bundleAluControl.ctrlJAL || io.bundleAluControl.ctrlAUIPC){
+        oprand1 := io.pc
+    }.elsewhen(io.bundleAluControl.ctrlLUI){
+        oprand1 := 0.U
+    }.otherwise{
+        oprand1 := io.dataRead1
+    }
+    //oprand1 := Mux(io.bundleAluControl.ctrlJAL, io.pc, io.dataRead1) 语句有误
     oprand2 := Mux(io.bundleAluControl.ctrlALUSrc, io.imm, io.dataRead2)
 
     // 根据bundleAluControl中的信号进行选择
@@ -97,4 +104,4 @@ class Alu extends Module {
 
     io.resultAlu := resultAlu
     io.resultBranch := resultBranch
-}
+}

src/main/scala/rv32isc/Controller.scala

@@ -18,6 +18,8 @@ class Controller extends Module {
     // alu
     io.bundleAluControl.ctrlALUSrc := io.bundleControlIn.ctrlALUSrc
     io.bundleAluControl.ctrlJAL := io.bundleControlIn.ctrlJAL
+    io.bundleAluControl.ctrlLUI := io.bundleControlIn.ctrlLUI    //新增 corrected
+    io.bundleAluControl.ctrlAUIPC := io.bundleControlIn.ctrlAUIPC    //新增 corrected
     io.bundleAluControl.ctrlOP := io.bundleControlIn.ctrlOP
     io.bundleAluControl.ctrlSigned := io.bundleControlIn.ctrlSigned
     io.bundleAluControl.ctrlBranch := io.bundleControlIn.ctrlBranch
@@ -30,4 +32,4 @@ class Controller extends Module {
 
     // 其他
     io.bundleControlOut <> io.bundleControlIn
-}
+}

src/main/scala/rv32isc/Decoder.scala

@@ -43,18 +43,37 @@ class Decoder extends Module {
     val ctrlStore = WireDefault(false.B)
     val ctrlALUSrc = WireDefault(false.B)
     val ctrlJAL = WireDefault(false.B)
+    val ctrlAUIPC = WireDefault(false.B)//判断指令是否为AUIPC指令，如果是，操作数1的值应当为当前PC的值 新增 corrected by rainman
+    val ctrlLUI = WireDefault(false.B) //判断是否为LUI指令，如果是，操作数1的值应当为0 新增
     val ctrlOP = WireDefault(0.U(OP_TYPES_WIDTH.W))
     val ctrlSigned = WireDefault(true.B)
     val ctrlLSType = WireDefault(LS_W)
 
     // 根据opcode对控制信号赋值
     switch (io.inst(6, 2)) {
         // U: LUI, AUIPC
-        is ("b01101".U, "b00101".U) {
+        /*is ("b01101".U, "b00101".U) {
             ctrlALUSrc := true.B
             ctrlOP := OP_ADD
             imm := imm_u
+        }*/
+        //新增 corrected
+        //U: LUI
+        is ("b01101".U){
+            ctrlALUSrc := true.B
+            ctrlOP := OP_ADD
+            ctrlLUI :=true.B
+            imm := imm_u
+        }
+        //U: AUIPC
+        is ("b00101".U){
+            ctrlALUSrc := true.B
+            ctrlOP := OP_ADD
+            ctrlAUIPC := true.B
+            //ctrlJAL := true.B
+            imm := imm_u
         }
+        
         // J: JAL
         is ("b11011".U) {
             ctrlALUSrc := true.B
@@ -238,6 +257,8 @@ class Decoder extends Module {
     io.bundleCtrl.ctrlALUSrc := ctrlALUSrc
     io.bundleCtrl.ctrlBranch := ctrlBranch
     io.bundleCtrl.ctrlJAL := ctrlJAL
+    io.bundleCtrl.ctrlLUI := ctrlLUI //新增 corrected
+    io.bundleCtrl.ctrlAUIPC := ctrlAUIPC //新增 corrected
     io.bundleCtrl.ctrlJump := ctrlJump
     io.bundleCtrl.ctrlLoad := ctrlLoad
     io.bundleCtrl.ctrlOP := ctrlOP
@@ -246,4 +267,4 @@ class Decoder extends Module {
     io.bundleCtrl.ctrlStore := ctrlStore
     io.bundleCtrl.ctrlLSType := ctrlLSType
     io.imm := imm
-}
+}

src/main/scala/utils/Bundles.scala

@@ -14,6 +14,8 @@ class BundleControl extends Bundle {
     val ctrlStore = Output(Bool())
     val ctrlALUSrc = Output(Bool())
     val ctrlJAL = Output(Bool())
+    val ctrlLUI = Output(Bool()) //新增 corrected
+    val ctrlAUIPC = Output(Bool()) //新增 corrected
     val ctrlOP = Output(UInt(OP_TYPES_WIDTH.W))
     val ctrlSigned = Output(Bool())
     val ctrlLSType = Output(UInt(LS_TYPE_WIDTH.W))
@@ -22,6 +24,8 @@ class BundleControl extends Bundle {
 class BundleAluControl extends Bundle {
     val ctrlALUSrc = Input(Bool())
     val ctrlJAL = Input(Bool())
+    val ctrlLUI = Input(Bool()) //新增 corrected
+    val ctrlAUIPC = Input(Bool()) //新增 corrected
     val ctrlOP = Input(UInt(OP_TYPES_WIDTH.W))
     val ctrlSigned = Input(Bool())
     val ctrlBranch = Input(Bool())
@@ -38,4 +42,4 @@ class BundleReg extends Bundle {
     val rs1 = Output(UInt(REG_NUMS_LOG.W))
     val rs2 = Output(UInt(REG_NUMS_LOG.W))
     val rd = Output(UInt(REG_NUMS_LOG.W))
-}
+}