cmd/internal/obj/riscv: implement Zicond assembly and disassembly on riscv64

This patch implement assembler and disassembler support for the Zicond extension:
CZEROEQZ and CZERONEZ.

Update opcode names and encodings in obj/riscv, enable rv_zicond in
generated tables, and add basic test coverage in riscv64.s.

Follow-up to CL 631576
Update #75350

Author: lxq015

src/cmd/asm/internal/asm/testdata/riscv64.s

@@ -177,6 +177,12 @@ start:
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
+	// 11.: Zicond Instructions 
+	CZEROEQZ	X1, X13, X5  	// b3d2160e
+	CZEROEQZ	X1, X13			// b3d6160e
+	CZERONEZ	X31, X3, X11 	// b3f5f10f
+	CZERONEZ	X31, X3			// b3f1f10f
+
 	// 13.1: Multiplication Operations
 	MUL	X5, X6, X7				// b3035302
 	MULH	X5, X6, X7				// b3135302

src/cmd/internal/obj/riscv/anames.go

@@ -407,6 +407,10 @@ const (
 	ACSRRSI
 	ACSRRCI
 
+	// 11.: Zicond Instructions
+	ACZEROEQZ
+	ACZERONEZ
+
 	// 13.1: Multiplication Operations
 	AMUL
 	AMULH

src/cmd/internal/obj/riscv/cpu.go

@@ -2007,6 +2007,10 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	AFLD & obj.AMask: {enc: iFEncoding},
 	AFSD & obj.AMask: {enc: sFEncoding},
 
+	// 11. "Zicond" Extension for Integer Conditional Operations
+	ACZERONEZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+	ACZEROEQZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+
 	// 21.4: Double-Precision Floating-Point Computational Instructions
 	AFADDD & obj.AMask:   {enc: rFFFEncoding},
 	AFSUBD & obj.AMask:   {enc: rFFFEncoding},