remove disassembler support

lxq015 · lxq015 · commit cc8f39c60a27 · 2025-09-12T09:04:48.000+08:00
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -177,7 +177,7 @@ start:
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
-	// 11.1: Zicond Instructions
+	// 11.1: Integer Conditional Operations (Zicond)
 	CZEROEQZ	X1, X13, X5			// b3d2160e
 	CZEROEQZ	X1, X13				// b3d6160e
 	CZERONEZ	X31, X3, X11			// b3f5f10f
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
@@ -407,7 +407,7 @@ const (
 	ACSRRSI
 	ACSRRCI
 
-	// 11.1 "Zicond" Extension for Integer Conditional Operations
+	// 11.1: Integer Conditional Operations (Zicond)
 	ACZEROEQZ
 	ACZERONEZ
 
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
@@ -2007,7 +2007,7 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	AFLD & obj.AMask: {enc: iFEncoding},
 	AFSD & obj.AMask: {enc: sFEncoding},
 
-	// 11.1 "Zicond" Extension for Integer Conditional Operations
+	// 11.1: "Zicond" Extension for Integer Conditional Operations
 	ACZERONEZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
 	ACZEROEQZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
 
diff --git a/src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/tables.go b/src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/tables.go
