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Igor Grinbergtrini
Igor Grinberg
authored and
trini
committed
omap3: cm-t3517: add basic board support
CompuLab cm-t3517 is Computer on Module (CoM) based on AM3517 SoC. Features: up to 256MB DDR2, up to 512MB NAND, USB hub, mUSB, WiFi, BT, Analog audio codec, touch screen controller, LED. Add basic support including: LED, Serial console, NAND, MMC, GPIO, I2C, 256MB DRAM. Signed-off-by: Igor Grinberg <[email protected]>
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‎arch/arm/cpu/armv7/omap3/Kconfig

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@@ -22,6 +22,9 @@ config TARGET_CM_T35
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bool "CompuLab CM-T3530 and CM-T3730 boards"
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select SUPPORT_SPL
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config TARGET_CM_T3517
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bool "CompuLab CM-T3517 boards"
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config TARGET_DEVKIT8000
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bool "TimLL OMAP3 Devkit8000"
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select SUPPORT_SPL
@@ -98,6 +101,7 @@ source "board/teejet/mt_ventoux/Kconfig"
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source "board/ti/sdp3430/Kconfig"
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source "board/ti/beagle/Kconfig"
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source "board/compulab/cm_t35/Kconfig"
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source "board/compulab/cm_t3517/Kconfig"
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source "board/timll/devkit8000/Kconfig"
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source "board/ti/evm/Kconfig"
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source "board/isee/igep00x0/Kconfig"

‎board/compulab/cm_t3517/Kconfig

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if TARGET_CM_T3517
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config SYS_BOARD
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default "cm_t3517"
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config SYS_VENDOR
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default "compulab"
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config SYS_CONFIG_NAME
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default "cm_t3517"
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endif

‎board/compulab/cm_t3517/MAINTAINERS

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CM_T3517 BOARD
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M: Igor Grinberg <[email protected]>
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S: Maintained
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F: board/compulab/cm_t3517/
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F: include/configs/cm_t3517.h
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F: configs/cm_t3517_defconfig

‎board/compulab/cm_t3517/Makefile

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#
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# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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#
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# Authors: Igor Grinberg <[email protected]>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cm_t3517.o mux.o

‎board/compulab/cm_t3517/cm_t3517.c

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/*
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* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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*
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* Authors: Igor Grinberg <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <status_led.h>
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#include <mmc.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/am35x_def.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"CM-T3517 board",
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"NAND 128/512M",
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};
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
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#endif
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return 0;
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}
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int misc_init_r(void)
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{
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cl_print_pcb_info();
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dieid_num_r();
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return 0;
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}
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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#define SB_T35_CD_GPIO 144
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#define SB_T35_WP_GPIO 59
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
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}
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#endif

‎board/compulab/cm_t3517/mux.c

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/*
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* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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*
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* Authors: Igor Grinberg <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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void set_muxconf_regs(void)
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{
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/* SDRC */
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
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/* SB-T35 SD/MMC WP GPIO59 */
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MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
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/* SB-T35 Audio Enable GPIO61 */
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MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
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/* UART3 Console */
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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/* RTC V3020 nCS GPIO163 */
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
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/* SB-T35 SD/MMC CD GPIO144 */
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MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
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/* WIFI nRESET GPIO145 */
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MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
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/* MMC1 */
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MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
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/* I2C */
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MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
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MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
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MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
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MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
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/* Green LED GPIO186 */
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MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
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/* RTC V3020 CS Enable GPIO160 */
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MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
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/* SYS_BOOT */
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MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
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MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
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MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
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MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
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MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
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MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
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}

‎configs/cm_t3517_defconfig

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CONFIG_SPL=n
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+S:CONFIG_ARM=y
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+S:CONFIG_OMAP34XX=y
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+S:CONFIG_TARGET_CM_T3517=y

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