A curated list of tools, simulators, proxies, datasets, benchmarks, and workflows that support auditable AI-assisted computing-system design loops. The public registry at arch2.mlsysbook.ai/tools shows the same source records with availability and link-verification status.
Use the tool submission form to propose an entry for maintainer review.
- Simulation and Execution Environments
- Proxy Models and Surrogate Predictors
- Agentic Workflows and Generators
- Data Representations and Hardware Vocabularies
- Verification and Red-Teaming
- Benchmarks and Datasets
- Physical Design and EDA
| Tool or artifact | Availability | Description |
|---|---|---|
| gem5 | Source available; link checked 2026-07-10 | Modular computer-system simulator for architecture feedback needing workload execution and reproducible state. |
| FireSim | Source available; link checked 2026-07-10 | FPGA-accelerated full-system simulation for when the loop needs stronger hardware/software feedback than a proxy can provide. |
| Chipyard | Source available; link checked 2026-07-10 | Integrated framework for generating and evaluating hardware systems, connecting generators, RTL, and simulation. |
| SST | Source available; link checked 2026-07-10 | Modular parallel simulation framework for exploring systems where ISA, microarchitecture, memory, programming model, and communication interact. |
| ChampSim | Source available; link checked 2026-07-10 | Trace-based simulator for fast feedback on cache, branch prediction, prefetching, and memory-hierarchy ideas. |
| GPGPU-Sim | Source available; link checked 2026-07-10 | Detailed GPU simulator for CUDA and OpenCL workloads when a loop needs microarchitectural feedback for GPU designs. |
| Sniper | Source available; link checked 2026-07-10 | Fast multicore x86 simulator based on interval core modeling for many-core architecture tradeoff studies. |
| zsim | Source available; link checked 2026-07-10 | Fast x86-64 multicore simulator focused on memory hierarchies and large heterogeneous systems. |
| Ramulator 2.0 | Source available; link checked 2026-07-10 | Modular cycle-accurate DRAM simulator for evaluating memory-system designs, DRAM standards, and mitigation ideas. |
| DRAMsim3 | Source available; link checked 2026-07-10 | Cycle-accurate, thermal-capable DRAM simulator supporting DDR, LPDDR, GDDR, HBM, HMC, and related protocols. |
| BookSim | Source available; link checked 2026-07-10 | Cycle-accurate interconnection-network simulator for studying NoC topologies, routing, and router microarchitecture. |
| SCALE-Sim | Source available; link checked 2026-07-10 | Systolic-array accelerator simulator for quickly exploring DNN accelerator design spaces. |
| Verilator | Source available; link checked 2026-07-10 | The fastest free Verilog HDL simulator, converting Verilog to C++/SystemC. |
| Tool or artifact | Availability | Description |
|---|---|---|
| Apollo | Paper only; link checked 2026-07-10 | An automated framework for fast, accurate, and transferable architecture design space exploration using surrogate models. |
| Aladdin | Source available; link checked 2026-07-10 | Pre-RTL power and performance simulator for accelerator-centric design-space exploration. |
| MAESTRO | Source available; link checked 2026-07-10 | Analytical cost model for DNN dataflows and tiling; a fast-feedback model for dataflow exploration. |
| Accelergy | Source available; link checked 2026-07-10 | Energy-estimation infrastructure for accelerators, providing an explicit energy feedback source. |
| Timeloop | Source available; link checked 2026-07-10 | Mapping and modeling tool for tensor workloads on accelerator architectures. |
| McPAT | Source available; link checked 2026-07-10 | Power, area, and timing modeling framework for multicore and manycore architectures. |
| CACTI | Source available; link checked 2026-07-10 | Analytical model for cache and memory access time, cycle time, area, and power. |
| Tool or artifact | Availability | Description |
|---|---|---|
| ArchGym | Source available; link checked 2026-07-10 | Open-source gym environment for evaluating machine learning algorithms in computer architecture exploration. |
| AutoChip | Source available; link checked 2026-07-10 | Conversational hardware design using LLMs to generate Verilog from natural language specifications. |
| ChipNeMo | Paper only; link checked 2026-07-10 | Domain-adapted LLMs for chip design, demonstrating automated EDA script generation and bug analysis. |
| VeriGen | Paper only; link checked 2026-07-10 | A large language model customized for generating functional Verilog code. |
| Tool or artifact | Availability | Description |
|---|---|---|
| Chisel | Source available; link checked 2026-07-10 | A hardware construction language embedded in Scala that provides high-level primitives for RTL generation. |
| PyMTL3 | Source available; link checked 2026-07-10 | An open-source Python-based hardware generation and simulation framework. |
| FIRRTL | Source available; link checked 2026-07-10 | A flexible intermediate representation for RTL, serving as the bridge between high-level generators and EDA tools. |
| Tool or artifact | Availability | Description |
|---|---|---|
| CocoTB | Source available; link checked 2026-07-10 | A coroutine-based cosimulation library for writing VHDL and Verilog testbenches in Python. |
| SymbiYosys | Source available; link checked 2026-07-10 | Front-end for Yosys-based formal verification flows, allowing agents to assert mathematical proofs against their generated RTL. |
| Tool or artifact | Availability | Description |
|---|---|---|
| CVDP Benchmark | Benchmark available; link checked 2026-07-10 | Comprehensive Verilog Design Problems for RTL design and verification. Crucial for loops involving HDL generation and test harnesses. |
| RTLLM | Benchmark available; link checked 2026-07-10 | Benchmark for natural-language-to-RTL generation with Verilog designs, descriptions, and testbenches. |
| RTL-Repo | Dataset available; link checked 2026-07-10 | Benchmark for evaluating LLMs on Verilog code completion within larger RTL repositories. |
| MLPerf Inference | Benchmark available; link checked 2026-07-10 | MLCommons benchmark suite for measuring how fast systems run trained models across deployment scenarios. |
| QuArch | Benchmark available; link checked 2026-07-10 | Architecture question-answering and reasoning benchmark to test if a model can reason over architecture concepts. |
| VerilogEval | Benchmark available; link checked 2026-07-10 | Specification-to-RTL and Verilog code-generation benchmark with executable checks. |
| KernelBench | Benchmark available; link checked 2026-07-10 | GPU-kernel generation benchmark with correctness and performance evaluation. |
| CircuitNet | Dataset available; link checked 2026-07-10 | VLSI CAD dataset for machine-learning applications in EDA. |
| HLS-Eval | Benchmark available; link checked 2026-09-14 | HLS-Eval is a project that provides benchmarking infrastructure and benchmark tasks for high-level synthesis (HLS) design. |
| Tool or artifact | Availability | Description |
|---|---|---|
| OpenROAD | Source available; link checked 2026-07-10 | Open-source RTL-to-GDS flow for loops that need physical-design feedback and evidence. |
| ChiPBench | Paper only; link checked 2026-07-10 | Benchmark focused on end-to-end physical-design impact for AI chip placement. |