chapter1-github-software-hardware-divide.csv

# GitHub Software vs Hardware Ecosystem Divide Dataset
# Compiled from The Stack v1/v2 (Kocetkov et al., Lozhkov et al.), GitHub Octoverse (2018-2025),
# OpenRTLSet (Wang et al., IEEE ICLAD 2025), VeriGen (Thakur et al., 2023), and Efabless Open MPW shuttle data.
tier,category,name,metric_type,value,unit,share_percentage,source_citation,notes
Corpus Scale,Software Language,JavaScript,dedup_size_gb,1115.42,GB,17.3,The Stack v2 (Lozhkov et al. 2024),108.87M files
Corpus Scale,Software Language,Java,dedup_size_gb,548.00,GB,14.2,The Stack v2 (Lozhkov et al. 2024),154.28M files
Corpus Scale,Software Language,C++,dedup_size_gb,353.89,GB,7.8,The Stack v2 (Lozhkov et al. 2024),43.18M files
Corpus Scale,Software Language,Python,dedup_size_gb,233.29,GB,8.9,The Stack v2 (Lozhkov et al. 2024),56.93M files
Corpus Scale,Software Language,C,dedup_size_gb,202.05,GB,6.4,The Stack v2 (Lozhkov et al. 2024),20.78M files
Corpus Scale,Software Language,TypeScript,dedup_size_gb,61.01,GB,3.5,The Stack v2 (Lozhkov et al. 2024),23.85M files
Corpus Scale,Software Language,Go,dedup_size_gb,54.60,GB,3.1,The Stack v2 (Lozhkov et al. 2024),9.30M files
Corpus Scale,Software Language,Rust,dedup_size_gb,15.60,GB,1.2,The Stack v2 (Lozhkov et al. 2024),2.22M files
Corpus Scale,Hardware HDL,VHDL,dedup_size_gb,2.10,GB,0.123,The Stack v2 (Lozhkov et al. 2024),115k files
Corpus Scale,Hardware HDL,SystemVerilog,dedup_size_gb,0.80,GB,0.051,The Stack v2 (Lozhkov et al. 2024),92k files
Corpus Scale,Hardware HDL,Verilog,dedup_size_gb,0.70,GB,0.040,The Stack v2 (Lozhkov et al. 2024),85k files (.v deduplicated)
Corpus Scale,Hardware HDL,Chisel/Scala,dedup_size_gb,0.10,GB,0.005,The Stack v2 (Lozhkov et al. 2024),8.5k files
Corpus Scale,Hardware HDL,Bluespec BSV,dedup_size_gb,0.06,GB,0.004,The Stack v2 (Lozhkov et al. 2024),11k files
Synthesizability Funnel,OpenRTLSet Mining,Initial Public Repositories,count,189000,repositories,100.0,OpenRTLSet (Wang et al. 2025),81k Verilog + 5k VHDL + 103k C/C++ HLS repos
Synthesizability Funnel,OpenRTLSet Mining,Synthesizability Regex Screen,count,12000,repositories,6.35,OpenRTLSet (Wang et al. 2025),Filtered for synthesizable construct patterns
Synthesizability Funnel,OpenRTLSet Mining,HLS Compiler Verification Pass,count,1000,repositories,0.53,OpenRTLSet (Wang et al. 2025),Clean compilation in Xilinx Vitis HLS
Synthesizability Funnel,OpenRTLSet Mining,Extracted Verilog Modules,count,131000,modules,100.0,OpenRTLSet (Wang et al. 2025),102k Verilog + 5k VHDL + 24k HLS modules
Hardware Quality Funnel,General RTL,Raw Public HDL Files on GitHub,relative_index,100.0,percent,100.0,Open-Source EDA Survey (2025),~300k public HDL source files
Hardware Quality Funnel,General RTL,Syntactically Parsable Modules,relative_index,72.4,percent,72.4,VerilogEval (Liu et al. 2023),AST syntax parsing
Hardware Quality Funnel,General RTL,Open EDA Elaboratable (iverilog/verilator),relative_index,38.1,percent,38.1,RTLLM (Lu et al. 2024),Clean elaboration without proprietary macros
Hardware Quality Funnel,General RTL,Logic Synthesizable Netlists (Yosys),relative_index,18.0,percent,18.0,OpenRTLSet (Wang et al. 2025),Synthesizable to generic gate netlist
Hardware Quality Funnel,General RTL,Functionally Verified with Automated CI,relative_index,7.2,percent,7.2,NotSoTiny / OpenRTLSet (2025),Contains runnable testbench and passing CI
Hardware Quality Funnel,General RTL,Tapeout-Ready Clean Physical Signoff,relative_index,0.85,percent,0.85,Efabless Open MPW / HighTide (2025),DRC/LVS and timing clean in OpenROAD
Iteration Cadence,Software,Unit Test & Linting,turnaround_seconds,5.0,seconds,-,Software CI Benchmarks,pytest / cargo test / jest
Iteration Cadence,Software,Cloud CI Test Suite,turnaround_seconds,300.0,seconds,-,GitHub Actions Average,Multi-OS cloud build & test
Iteration Cadence,Hardware,RTL Fast Lint (Verilator),turnaround_seconds,5.0,seconds,-,Verilator Lint,Syntax & clock race checking
Iteration Cadence,Hardware,Cycle-Accurate Simulation (gem5/VCS),turnaround_seconds,3600.0,seconds,-,gem5 / Synopsys VCS,Full-system OS boot / testbench regression
Iteration Cadence,Hardware,Logic Synthesis (Yosys/DesignCompiler),turnaround_seconds,7200.0,seconds,-,Yosys / Synopsys DC,Technology mapping on multi-module block
Iteration Cadence,Hardware,Full Physical Signoff (OpenROAD/Innovus),turnaround_seconds,43200.0,seconds,-,OpenROAD / Cadence Innovus,Place & Route, clock tree, DRC/LVS, timing