chapter2-foundry-node-cost-inversion.csv

node_name,intro_year,transistor_architecture,transistor_density_mtr_mm2,density_source,wafer_cost_300mm_usd,wafer_cost_source,euv_layers,lithography_tool,wafer_area_mm2,wafer_cost_per_mm2_usd,cost_per_100m_transistors_usd
90 nm,2004,Planar Bulk CMOS (Al/Cu),1.25,"TSMC IEDM 2004 / ISSCC 2005 (0.345um² SRAM bitcell, ~1.25 MTr/mm²)",1850,IBS & IC Insights Foundry Wafer Pricing Model 2004,0,193nm Dry ArF Lithography,70685.83,0.02617,2.0938
65 nm,2006,Planar Bulk CMOS (Strained Si),2.65,"TSMC IEDM 2006 / ISSCC 2007 (0.160um² SRAM bitcell, ~2.65 MTr/mm²)",2100,IBS & IC Insights Foundry Wafer Pricing Model 2006,0,193nm Dry / Immersion ArF,70685.83,0.02971,1.1211
45/40 nm,2008,Planar Bulk CMOS (Immersion),5.8,"TSMC IEDM 2008 (40nm G/LP, 0.242um² SRAM, ~5.8 MTr/mm²)",2450,IBS & IC Insights 2008 Foundry Database,0,193nm Immersion ArFi Lithography,70685.83,0.03466,0.5976
28 nm,2011,Planar HKMG (High-k Metal Gate),15.3,"TSMC IEDM 2011 (28nm HP/HPM/HPC, 0.127um² SRAM, 15.3 MTr/mm²)",3000,IBS (Handel Jones) SEMI Keynote 2012; TSMC 28nm Baseline,0,193nm Immersion ArFi (Single Patterning),70685.83,0.04244,0.2774
20 nm,2014,Planar HKMG (Double Patterning),21.8,"TSMC IEDM 2013 (20nm SoC, 0.086um² SRAM, 21.8 MTr/mm²)",3800,IBS Wafer Pricing Survey 2014 (ArFi LELE Double Patterning),0,193nm Immersion ArFi (Double Patterning DPT),70685.83,0.05376,0.2466
16/14 nm,2015,3D FinFET (1st Gen 3D Tri-Gate),28.8,"TSMC IEDM 2014 (16nm FinFET+, 0.074um² SRAM, 28.8 MTr/mm²)",4500,IBS & Gartner 2015 Foundry Report (FinFET manufacturing adder),0,193nm Immersion ArFi (Self-Aligned Double Patterning SADP),70685.83,0.06366,0.221
10 nm,2017,3D FinFET (2nd Gen FinFET),52.5,"TSMC IEDM 2016 (10nm FinFET, 0.040um² SRAM, 52.5 MTr/mm²)",6000,IBS & IC Insights 2017 Foundry Analysis (Triple/Quad Patterning),0,193nm Immersion ArFi (SAQP Quad Patterning),70685.83,0.08488,0.1617
7 nm (N7),2018,3D FinFET (DUV / 1st Gen EUV),91.2,"TSMC IEDM 2017 / ISSCC 2018 (N7 FinFET, 0.027um² SRAM, 91.2 MTr/mm²)",9800,IBS 2018 Benchmark Report; TSMC N7 Commercial Wafer Contract Estimates,4,193nm ArFi SAQP + 0.33 NA EUV (N7+),70685.83,0.13864,0.152
5 nm (N5),2020,3D FinFET (Full EUV),138.2,"TSMC IEDM 2019 / ISSCC 2020 (N5 FinFET, 0.021um² SRAM, 138.2 MTr/mm² SoC density)",16500,IBS & CICC / TrendForce 2020 TSMC N5 Wafer Contract Pricing,14,0.33 NA EUV Single/Double Patterning (14+ masks),70685.83,0.23343,0.1689
3 nm (N3E),2022,3D FinFET (Enhanced FinFET),215.0,"TSMC IEDM 2022 / VLSI 2023 (N3E FinFET, 0.0199um² SRAM, 215 MTr/mm² 2-2 fin standard library)",20000,IBS (Handel Jones) 2023 Study; TSMC N3E Commercial Disclosures (~$20k/wafer),24,0.33 NA EUV Multi-Patterning (24+ masks),70685.83,0.28294,0.1316
2 nm (N2),2025,GAA Nanosheet (GAAFET + BSPDN),280.0,"TSMC IEDM 2024 / VLSI 2025 (N2 GAA Nanosheet, Backside Power Delivery BSPDN, ~280 MTr/mm²)",30000,IBS 2024/2025 Advanced Packaging & Node Study ($30k+ N2 wafer quote),30,0.33 NA High-Dose EUV + NanoSheet GAA Epitaxy,70685.83,0.42441,0.1516