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pito.core
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CAPI=2:
name : ::pito:0
description: Barrel RISC-V core to control an array of Matrix Vector Units
filesets:
rtl:
file_type : systemVerilogSource
files:
- deps/common_cells/src/cf_math_pkg.sv
- deps/apb/include/apb/assign.svh:
is_include_file: True
- deps/apb/include/apb/typedef.svh:
is_include_file: True
- deps/apb/src/apb_test.sv
- deps/apb/src/apb_pkg.sv
- deps/apb/src/apb_intf.sv
- deps/common_cells/src/onehot_to_bin.sv
- verification/lib/rv32/rv32_defines.svh:
is_include_file: true
- verification/lib/rv32/rv32_pkg.sv
- verification/lib/pito/pito_pkg.sv
- verification/lib/pito/pito_intf.sv
- vsrc/rv32_imm_gen.sv
- vsrc/rv32_decoder.sv
- vsrc/rv32_data_memory.sv
- vsrc/rv32_instruction_memory.sv
- vsrc/rv32_alu.sv
- vsrc/rv32_regfile.sv
- vsrc/rv32_barrel_regfiles.sv
- vsrc/rv32_core.sv
- vsrc/rv32_next_pc.sv
- vsrc/rv32_csr.sv
- vsrc/rv32_barrel_csrfiles.sv
- vsrc/pito_uart.sv
- vsrc/pito_soc.sv
file_type : systemVerilogSource
synth:
file_type : systemVerilogSource
files:
- deps/common_cells/src/cf_math_pkg.sv
- deps/apb/include/apb/assign.svh:
is_include_file: True
- deps/apb/include/apb/typedef.svh:
is_include_file: True
- deps/apb/src/apb_test.sv
- deps/apb/src/apb_pkg.sv
- deps/apb/src/apb_intf.sv
- deps/tech_cells_generic/src/rtl/tc_sram.sv
- deps/common_cells/src/onehot_to_bin.sv
- verification/lib/rv32/rv32_defines.svh:
is_include_file: true
- verification/lib/rv32/rv32_pkg.sv
- verification/lib/pito/pito_pkg.sv
- verification/lib/pito/pito_intf.sv
- vsrc/rv32_imm_gen.sv
- vsrc/rv32_decoder.sv
- vsrc/rv32_data_memory.sv
- vsrc/rv32_instruction_memory.sv
- vsrc/rv32_alu.sv
- vsrc/rv32_regfile.sv
- vsrc/rv32_barrel_regfiles.sv
- vsrc/rv32_core.sv
- vsrc/rv32_next_pc.sv
- vsrc/rv32_csr.sv
- vsrc/rv32_barrel_csrfiles.sv
- vsrc/pito_uart.sv
- vsrc/pito_soc.sv
- synthesis/constraint_files/pito_core.xdc:
file_type: xdc
tb:
files:
- verification/lib/testbench/testbench_macros.svh:
is_include_file: true
- verification/lib/utils/utils.sv
- verification/lib/rv32/rv32_utils.sv
- verification/lib/pito/pito_monitor.sv:
is_include_file: true
- verification/lib/testbench/testbench_config.sv:
is_include_file: true
- verification/lib/testbench/testbench_base.sv
- verification/tests/core/core_tester.sv:
is_include_file: true
- verification/tests/irq/irq_tester.sv:
is_include_file: true
- verification/tests/rv32_test/rv32_tests.sv:
is_include_file: true
- verification/lib/testbench/testbench_top.sv
file_type : systemVerilogSource
simulation_sram:
files:
- deps/tech_cells_generic/src/rtl/tc_sram.sv: {file_type : systemVerilogSource}
synthesis_sram:
files:
- synthesis/scripts/xpm_rams.tcl: {file_type: tclSource}
- deps/tech_cells_generic/src/fpga/tc_sram_xilinx.sv: {file_type : systemVerilogSource}
targets:
sim: &sim
default_tool: modelsim
filesets:
- simulation_sram
- rtl
- tb
description: Simulate the design
tools:
xsim:
xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, --timescale, 1ns/1ps]
modelsim:
vlog_options : [-timescale=1ns/1ps]
vsim_options : [-t, 1ps, -suppress, vsim-3009 , -suppress, vopt-7033]
parameters: [firmware,rodata]
toplevel: testbench_top
sim-irq:
<<: *sim
parameters: [firmware,rodata, TB_IRQ]
sim-regression:
<<: *sim
parameters: [firmware,rodata, TB_REGRESSION]
synth:
description: Synthesize the design for an FPGA board
filesets:
- synthesis_sram
- rtl
default_tool: vivado
tools:
vivado:
part: xcvu9p-flgb2104-2-e
toplevel: [pito_soc]
parameters:
firmware:
datatype : file
default : /users/hemmat/MyRepos/pito_riscv/csrc/uart/build/uart_text.hex
paramtype : plusarg
rodata:
datatype : file
default : /users/hemmat/MyRepos/pito_riscv/csrc/uart/build/uart_data.hex
paramtype : plusarg
TB_IRQ:
datatype : int
default : 1
paramtype : vlogdefine
TB_REGRESSION:
datatype : int
default : 1
paramtype : vlogdefine
SIMULATION_MODE:
datatype : int
default : 1
paramtype : vlogdefine