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nate-desimonenate-desimone
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Comet Lake FSP 9.3.7B.20
1 parent cd99eca commit b240866

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4 files changed

+124
-33
lines changed

4 files changed

+124
-33
lines changed

‎CometLakeFspBinPkg/CometLakeS/Fsp.bsf

Lines changed: 47 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33
Boot Setting File for Platform Configuration.
44

5-
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
5+
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
66

77
SPDX-License-Identifier: BSD-2-Clause-Patent
88

@@ -226,7 +226,8 @@ StructDef
226226
$gPlatformFspPkgTokenSpaceGuid_TxtLcpPdSize 8 bytes $_DEFAULT_ = 0x0000000000000000
227227
$gPlatformFspPkgTokenSpaceGuid_IsTPMPresence 1 bytes $_DEFAULT_ = 0x0
228228
$gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock 1 bytes $_DEFAULT_ = 0x00
229-
$gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 2 bytes $_DEFAULT_ = 0x00
229+
$gPlatformFspPkgTokenSpaceGuid_VmaxStress 1 bytes $_DEFAULT_ = 0x01
230+
$gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem 1 bytes $_DEFAULT_ = 0x00
230231
$gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress 12 bytes $_DEFAULT_ = 0x00,0x00,0xD9,0xFE,0x00,0x20,0xD9,0xFE,0x00,0x10,0xD9,0xFE
231232
$gPlatformFspPkgTokenSpaceGuid_SmbusEnable 1 bytes $_DEFAULT_ = 0x01
232233
$gPlatformFspPkgTokenSpaceGuid_PlatformDebugConsent 1 bytes $_DEFAULT_ = 0x00
@@ -469,7 +470,11 @@ StructDef
469470
$gPlatformFspPkgTokenSpaceGuid_CoreVfPointOffsetPrefix 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
470471
$gPlatformFspPkgTokenSpaceGuid_CoreVfPointRatio 15 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
471472
$gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount 1 bytes $_DEFAULT_ = 0x00
472-
Skip 9 bytes
473+
$gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm 1 bytes $_DEFAULT_ = 0x09
474+
$gPlatformFspPkgTokenSpaceGuid_RefreshHpWm 1 bytes $_DEFAULT_ = 0x08
475+
$gPlatformFspPkgTokenSpaceGuid_RetrainOnFastFail 1 bytes $_DEFAULT_ = 0x01
476+
$gPlatformFspPkgTokenSpaceGuid_DllBwEnOverride 1 bytes $_DEFAULT_ = 0x00
477+
Skip 5 bytes
473478
$gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0
474479
$gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00
475480
$gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01
@@ -509,15 +514,18 @@ StructDef
509514
Skip 1 bytes
510515
$gPlatformFspPkgTokenSpaceGuid_DeltaT12PowerCycleDelayPreMem 2 bytes $_DEFAULT_ = 0x0
511516
$gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride 1 bytes $_DEFAULT_ = 0x0
512-
$gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 9 bytes $_DEFAULT_ = 0x00
517+
$gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee 1 bytes $_DEFAULT_ = 0x1
518+
$gPlatformFspPkgTokenSpaceGuid_SaPreMemTestRsvd 8 bytes $_DEFAULT_ = 0x00
513519
$gPlatformFspPkgTokenSpaceGuid_TotalFlashSize 2 bytes $_DEFAULT_ = 0x0000
514520
$gPlatformFspPkgTokenSpaceGuid_BiosSize 2 bytes $_DEFAULT_ = 0x2800
515521
$gPlatformFspPkgTokenSpaceGuid_TxtAcheckRequest 1 bytes $_DEFAULT_ = 0x0
516522
$gPlatformFspPkgTokenSpaceGuid_SecurityTestRsvd 3 bytes $_DEFAULT_ = 0x00
517523
$gPlatformFspPkgTokenSpaceGuid_SmbusDynamicPowerGating 1 bytes $_DEFAULT_ = 0x01
518524
$gPlatformFspPkgTokenSpaceGuid_WdtDisableAndLock 1 bytes $_DEFAULT_ = 0x00
519525
$gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable 1 bytes $_DEFAULT_ = 0x01
520-
$gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 16 bytes $_DEFAULT_ = 0x00
526+
$gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride 1 bytes $_DEFAULT_ = 0x00
527+
$gPlatformFspPkgTokenSpaceGuid_PerCoreRatio 10 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
528+
$gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest 5 bytes $_DEFAULT_ = 0x00
521529
$gPlatformFspPkgTokenSpaceGuid_DidInitStat 1 bytes $_DEFAULT_ = 0x0
522530
$gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling 1 bytes $_DEFAULT_ = 0x0
523531
$gPlatformFspPkgTokenSpaceGuid_SendDidMsg 1 bytes $_DEFAULT_ = 0x1
@@ -546,6 +554,7 @@ StructDef
546554
$gPlatformFspPkgTokenSpaceGuid_tWTR_L 1 bytes $_DEFAULT_ = 0x00
547555
$gPlatformFspPkgTokenSpaceGuid_tWTR_S 1 bytes $_DEFAULT_ = 0x00
548556
$gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00
557+
$gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug 24 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
549558

550559
Find "CMLUPD_S"
551560
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x01
@@ -1142,7 +1151,8 @@ StructDef
11421151
$gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00
11431152
$gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00
11441153
$gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01
1145-
$gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 16 bytes $_DEFAULT_ = 0x00
1154+
$gPlatformFspPkgTokenSpaceGuid_Usb3HsioRxCtrlCompMult 10 bytes $_DEFAULT_ = 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C
1155+
$gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest 6 bytes $_DEFAULT_ = 0x00
11461156
$gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle 1 bytes $_DEFAULT_ = 0x0
11471157
$gPlatformFspPkgTokenSpaceGuid_EmmcUseCustomDlls 1 bytes $_DEFAULT_ = 0x0
11481158
Skip 1 bytes
@@ -2450,7 +2460,9 @@ Page "System Agent 1"
24502460
Help "IsTPMPresence default values"
24512461
"Valid range: 0x00 ~ 0xFF"
24522462
Combo $gPlatformFspPkgTokenSpaceGuid_AutoEasyOverclock, "Intel Speed Optimizer Enable", &EN_DIS,
2453-
Help "When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable"
2463+
Help "@Deprecated: CML won't support BIOS ISO. And XTU ISO supported depends on Board thermal design. When enabled this feature automatically overclocks your processor. It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable"
2464+
Combo $gPlatformFspPkgTokenSpaceGuid_VmaxStress, "Vmax Stress", &EN_DIS,
2465+
Help "Vmax Stress enable/disable. When enabled, frequency may be clipped the effective max voltage on the silicon is too high.0: Disable; <b>1: Enable.</b>"
24542466
Combo $gPlatformFspPkgTokenSpaceGuid_ReservedSecurityPreMem, "ReservedSecurityPreMem", &EN_DIS,
24552467
Help "Reserved for Security Pre-Mem"
24562468
EditNum $gPlatformFspPkgTokenSpaceGuid_VtdBaseAddress, "Base addresses for VT-d function MMIO access", HEX,
@@ -2476,6 +2488,8 @@ Page "System Agent 1"
24762488
Help "Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms"
24772489
Combo $gPlatformFspPkgTokenSpaceGuid_OemT12DelayOverride, "Oem T12 Dealy Override", &EN_DIS,
24782490
Help "Oem T12 Dealy Override. 0(Default)=Disable 1=Enable "
2491+
Combo $gPlatformFspPkgTokenSpaceGuid_DmaControlGuarantee, "State of DMA_CONTROL_GUARANTEE bit in the DMAR table", &EN_DIS,
2492+
Help "0=Disable/Clear, 1=Enable/Set"
24792493
EndPage
24802494

24812495
Page "System Agent 2"
@@ -3614,6 +3628,17 @@ Page "Memory Reference Code 1"
36143628
EditNum $gPlatformFspPkgTokenSpaceGuid_CoreVfPointCount, "Core VF Point Count", HEX,
36153629
Help "Number of supported Core Voltage & Frequency Point Offset"
36163630
"Valid range: 0x0 ~ 0xFF"
3631+
EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshPanicWm, "REFRESH_PANIC_WM", HEX,
3632+
Help "Refresh Panic Watermark, range 1-9"
3633+
"Valid range: 0x01 ~ 0x9"
3634+
EditNum $gPlatformFspPkgTokenSpaceGuid_RefreshHpWm, "REFRESH_HP_WM", HEX,
3635+
Help "Refresh High Priority Watermark, range 1-9"
3636+
"Valid range: 0x01 ~ 0x9"
3637+
EditNum $gPlatformFspPkgTokenSpaceGuid_RetrainOnFastFail, "Retrain On Fast Fail", HEX,
3638+
Help "Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled"
3639+
"Valid range: 0x0 ~ 0xFF"
3640+
Combo $gPlatformFspPkgTokenSpaceGuid_DllBwEnOverride, "DllBwEnOverride", &EN_DIS,
3641+
Help "DllBwEnOverride 0: Disable(Default), 1: Enable"
36173642
Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS,
36183643
Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices"
36193644
Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS,
@@ -4181,7 +4206,7 @@ Page "PCH 1"
41814206
Combo $gPlatformFspPkgTokenSpaceGuid_PchLockDownRtcMemoryLock, "RTC CMOS MEMORY LOCK", &EN_DIS,
41824207
Help "Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM."
41834208
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX,
4184-
Help "Indicate whether the root port is hot plug available."
4209+
Help "DEPRECATED"
41854210
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
41864211
EditNum $gPlatformFspPkgTokenSpaceGuid_PchSataHsioRxGen2EqBoostMagEnable, "Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override", HEX,
41874212
Help "0: Disable; 1: Enable."
@@ -4351,7 +4376,7 @@ Page "PCH 1"
43514376
Help "Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset"
43524377
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
43534378
EditNum $gPlatformFspPkgTokenSpaceGuid_PchUsbHsioRxTuningEnable, "PCH USB3 HSIO Rx Tuning Enable", HEX,
4354-
Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable"
4379+
Help "Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable, 4 - HsioCtrlCompMultEnable"
43554380
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
43564381
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpPcieSpeed, "PCIE RP Pcie Speed", HEX,
43574382
Help "Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)."
@@ -4393,11 +4418,16 @@ Page "PCH 1"
43934418
Help "Set 1 to clear WDT status, then disable and lock WDT registers."
43944419
Combo $gPlatformFspPkgTokenSpaceGuid_SmbusSpdWriteDisable, "SMBUS SPD Write Disable", &EN_DIS,
43954420
Help "Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set."
4396-
Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS,
4397-
Help "Reserved for Pch Pre-Mem Test"
4421+
Combo $gPlatformFspPkgTokenSpaceGuid_PerCoreRatioOverride, "Per Core Max Ratio override", &EN_DIS,
4422+
Help "Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. <b>0: Disable</b>, 1: enable"
4423+
EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreRatio, "Per Core Current Max Ratio", HEX,
4424+
Help "Array for the Per Core Max Ratio"
4425+
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
43984426
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCm, "PCIE Eq Ph3 Lane Param Cm", HEX,
43994427
Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1."
44004428
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
4429+
Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPreMemTest, "ReservedPchPreMemTest", &EN_DIS,
4430+
Help "Reserved for Pch Pre-Mem Test"
44014431
Combo $gPlatformFspPkgTokenSpaceGuid_DidInitStat, "Force ME DID Init Status", &EN_DIS,
44024432
Help "Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value"
44034433
Combo $gPlatformFspPkgTokenSpaceGuid_DisableCpuReplacedPolling, "CPU Replaced Polling Disable", &EN_DIS,
@@ -4415,6 +4445,9 @@ Page "PCH 1"
44154445
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieEqPh3LaneParamCp, "PCIE Eq Ph3 Lane Param Cp", HEX,
44164446
Help "PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1."
44174447
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
4448+
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieRpHotPlug, "Enable PCIE RP HotPlug", HEX,
4449+
Help "Indicate whether the root port is hot plug available"
4450+
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
44184451
EditNum $gPlatformFspPkgTokenSpaceGuid_PcieSwEqCoeffListCm, "PCIE Sw Eq CoeffList Cm", HEX,
44194452
Help "PCH_PCIE_EQ_PARAM. Coefficient C-1. The values depend on PcieNumOfCoefficients, the default value of PcieNumOfCoefficients is 3 hence only first 3 values are considered."
44204453
"Valid range: 0x00 ~ 0xFFFFFFFFFF"
@@ -4795,6 +4828,9 @@ Page "PCH 1"
47954828
Help "Allow entrance to the PCH SATA test modes."
47964829
Combo $gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock, "PCH USB OverCurrent mapping lock enable", &EN_DIS,
47974830
Help "If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked."
4831+
EditNum $gPlatformFspPkgTokenSpaceGuid_Usb3HsioRxCtrlCompMult, "CTLE Rate control CPR RCOMP multiplier (Double Rate)", HEX,
4832+
Help "CTLE Rate control CPR RCOMP multiplier (Double Rate), HSIO_RX_DWORD27 [31:24], One byte for each port."
4833+
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFF"
47984834
Combo $gPlatformFspPkgTokenSpaceGuid_ReservedPchPostMemTest, "ReservedPchPostMemTest", &EN_DIS,
47994835
Help "Reserved for Pch Post-Mem Test"
48004836
Combo $gCannonLakeFspPkgTokenSpaceGuid_MctpBroadcastCycle, "Mctp Broadcast Cycle", &EN_DIS,

‎CometLakeFspBinPkg/CometLakeS/Fsp.fd

0 Bytes
Binary file not shown.

‎CometLakeFspBinPkg/CometLakeS/Include/FspmUpd.h

Lines changed: 65 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/** @file
22
3-
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
3+
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
44
55
SPDX-License-Identifier: BSD-2-Clause-Patent
66
@@ -1116,17 +1116,25 @@ typedef struct {
11161116
UINT8 IsTPMPresence;
11171117

11181118
/** Offset 0x0241 - Intel Speed Optimizer Enable
1119-
When enabled this feature automatically overclocks your processor. It changes the
1120-
All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable
1119+
@Deprecated: CML won't support BIOS ISO. And XTU ISO supported depends on Board
1120+
thermal design. When enabled this feature automatically overclocks your processor.
1121+
It changes the All Core Frequency along with PL1, PL2, and IccMax. </b>0: Disable;<b> 1: Enable
11211122
$EN_DIS
11221123
**/
11231124
UINT8 AutoEasyOverclock;
11241125

1125-
/** Offset 0x0242 - ReservedSecurityPreMem
1126+
/** Offset 0x0242 - Vmax Stress
1127+
Vmax Stress enable/disable. When enabled, frequency may be clipped the effective
1128+
max voltage on the silicon is too high.0: Disable; <b>1: Enable.</b>
1129+
$EN_DIS
1130+
**/
1131+
UINT8 VmaxStress;
1132+
1133+
/** Offset 0x0243 - ReservedSecurityPreMem
11261134
Reserved for Security Pre-Mem
11271135
$EN_DIS
11281136
**/
1129-
UINT8 ReservedSecurityPreMem[2];
1137+
UINT8 ReservedSecurityPreMem[1];
11301138

11311139
/** Offset 0x0244 - Base addresses for VT-d function MMIO access
11321140
Base addresses for VT-d MMIO access per VT-d engine
@@ -2518,9 +2526,26 @@ typedef struct {
25182526
**/
25192527
UINT8 CoreVfPointCount;
25202528

2521-
/** Offset 0x0553
2529+
/** Offset 0x0553 - REFRESH_PANIC_WM
2530+
Refresh Panic Watermark, range 1-9
2531+
**/
2532+
UINT8 RefreshPanicWm;
2533+
2534+
/** Offset 0x0554 - REFRESH_HP_WM
2535+
Refresh High Priority Watermark, range 1-9
2536+
**/
2537+
UINT8 RefreshHpWm;
2538+
2539+
/** Offset 0x0555 - Retrain On Fast Fail
2540+
Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled
2541+
**/
2542+
UINT8 RetrainOnFastFail;
2543+
2544+
/** Offset 0x0556 - DllBwEnOverride
2545+
DllBwEnOverride 0: Disable(Default), 1: Enable
2546+
$EN_DIS
25222547
**/
2523-
UINT8 UnusedUpdSpace8[4];
2548+
UINT8 DllBwEnOverride;
25242549

25252550
/** Offset 0x0557
25262551
**/
@@ -2749,7 +2774,7 @@ typedef struct {
27492774

27502775
/** Offset 0x05B1
27512776
**/
2752-
UINT8 UnusedUpdSpace9;
2777+
UINT8 UnusedUpdSpace8;
27532778

27542779
/** Offset 0x05B2 - Jitter Dwell Time for PCIe Gen3 Software Equalization
27552780
Range: 0-65535, default is 1000. @warning Do not change from the default
@@ -2792,7 +2817,7 @@ typedef struct {
27922817

27932818
/** Offset 0x05BD
27942819
**/
2795-
UINT8 UnusedUpdSpace10;
2820+
UINT8 UnusedUpdSpace9;
27962821

27972822
/** Offset 0x05BE - Delta T12 Power Cycle Delay required in ms
27982823
Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
@@ -2807,11 +2832,17 @@ typedef struct {
28072832
**/
28082833
UINT8 OemT12DelayOverride;
28092834

2810-
/** Offset 0x05C1 - SaPreMemTestRsvd
2835+
/** Offset 0x05C1 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
2836+
0=Disable/Clear, 1=Enable/Set
2837+
$EN_DIS
2838+
**/
2839+
UINT8 DmaControlGuarantee;
2840+
2841+
/** Offset 0x05C2 - SaPreMemTestRsvd
28112842
Reserved for SA Pre-Mem Test
28122843
$EN_DIS
28132844
**/
2814-
UINT8 SaPreMemTestRsvd[9];
2845+
UINT8 SaPreMemTestRsvd[8];
28152846

28162847
/** Offset 0x05CA - TotalFlashSize
28172848
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@@ -2854,11 +2885,23 @@ typedef struct {
28542885
**/
28552886
UINT8 SmbusSpdWriteDisable;
28562887

2857-
/** Offset 0x05D5 - ReservedPchPreMemTest
2888+
/** Offset 0x05D5 - Per Core Max Ratio override
2889+
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
2890+
favored core ratio to each Core. <b>0: Disable</b>, 1: enable
2891+
$EN_DIS
2892+
**/
2893+
UINT8 PerCoreRatioOverride;
2894+
2895+
/** Offset 0x05D6 - Per Core Current Max Ratio
2896+
Array for the Per Core Max Ratio
2897+
**/
2898+
UINT8 PerCoreRatio[10];
2899+
2900+
/** Offset 0x05E0 - ReservedPchPreMemTest
28582901
Reserved for Pch Pre-Mem Test
28592902
$EN_DIS
28602903
**/
2861-
UINT8 ReservedPchPreMemTest[16];
2904+
UINT8 ReservedPchPreMemTest[5];
28622905

28632906
/** Offset 0x05E5 - Force ME DID Init Status
28642907
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
@@ -3017,7 +3060,12 @@ typedef struct {
30173060
**/
30183061
UINT8 SkipCpuReplacementCheck;
30193062

3020-
/** Offset 0x0601
3063+
/** Offset 0x0601 - Enable PCIE RP HotPlug
3064+
Indicate whether the root port is hot plug available
3065+
**/
3066+
UINT8 PcieRpHotPlug[24];
3067+
3068+
/** Offset 0x0619
30213069
**/
30223070
UINT8 ReservedFspmTestUpd[7];
30233071
} FSP_M_TEST_CONFIG;
@@ -3042,11 +3090,11 @@ typedef struct {
30423090
**/
30433091
FSP_M_TEST_CONFIG FspmTestConfig;
30443092

3045-
/** Offset 0x0608
3093+
/** Offset 0x0620
30463094
**/
3047-
UINT8 UnusedUpdSpace11[6];
3095+
UINT8 UnusedUpdSpace10[6];
30483096

3049-
/** Offset 0x060E
3097+
/** Offset 0x0626
30503098
**/
30513099
UINT16 UpdTerminator;
30523100
} FSPM_UPD;

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