Improve logs for partial read/write access

Fixes #356

Author: mandolaerik

RELEASENOTES-1.4.md

@@ -356,3 +356,4 @@
   The bugfix is opt-in, because an immediate bugfix would risk breaking existing builds; the error will only be reported when the flag `--no-compat=broken_unused_types` is passed to DMLC. This flag will be automatically enabled in Simics 8.
 - `release 7 7063`
 - `release 6 6362`
+- `note 6` Improved the log messages that are output by default for partial register accesses (fixes [#356](https://github.com/intel/device-modeling-language/issues/356)).

lib/1.4/dml-builtins.dml

@@ -2162,9 +2162,9 @@ template bank is (object, shown_desc) {
                     hits[r]._qname(), cast(size*2, int), r_val;
             } else {
                 log info, 4, Register_Read:
-                    "Partial read from register %s: bytes %d-%d -> 0x%0*x",
-                        hits[r]._qname(), r_start, r_end-1,
-                        cast(r_end - r_start, int),
+                    "Partial read from register %s[%d:%d] -> 0x%0*x",
+                        hits[r]._qname(), r_end * 8 - 1, r_start * 8,
+                        cast((r_end - r_start) * 2, int),
                         r_val[r_end * 8 - 1 : r_start * 8];
             }
 
@@ -2255,10 +2255,10 @@ template bank is (object, shown_desc) {
 	            hits[r]._qname(), cast(size*2, int), r_value;
             } else {
                 log info, 4, Register_Write:
-                    "Partial write to register %s: bytes %d-%d <- 0x%0*x",
-                    hits[r]._qname(), r_start, r_end-1,
-                    cast(r_end - r_start, int),
-                    r_value[r_end * 8 - 1 : r_start * 8];
+                    "Partial write to register %s[%d:%d] <- 0x%0*x",
+                        hits[r]._qname(), r_end * 8 - 1, r_start * 8,
+                        cast((r_end - r_start) * 2, int),
+                        r_value[r_end * 8 - 1 : r_start * 8];
             }
 
             hits[r].write_register(r_value & r_enabled_bytes, r_enabled_bytes,
@@ -2297,9 +2297,9 @@ template bank is (object, shown_desc) {
 	            hits[r]._qname(), cast(size*2, int), r_value;
             } else {
                 log info, 4, Register_Write:
-                    "Partially setting register %s: bytes %d-%d <- 0x%0*x",
-                    hits[r]._qname(), r_start, r_end-1,
-                    cast(r_end - r_start, int),
+                    "Partially setting register %s[%d:%d] <- 0x%0*x",
+                    hits[r]._qname(), r_end * 8 - 1, r_start * 8,
+                    cast((r_end - r_start) * 2, int),
                     r_value[r_end * 8 - 1 : r_start * 8];
             }
 

test/1.4/lib/T_partial_access_log.dml

@@ -0,0 +1,18 @@
+/*
+  © 2025 Intel Corporation
+  SPDX-License-Identifier: MPL-2.0
+*/
+
+dml 1.4;
+
+device test;
+
+/// DMLC-FLAG --no-compat=shared_logs_on_device
+bank le {
+    param byte_order = "little-endian";
+    register r size 4 @ 4;
+}
+bank be {
+    param byte_order = "big-endian";
+    register r size 4 @ 4;
+}

test/1.4/lib/T_partial_access_log.py

@@ -0,0 +1,50 @@
+# © 2025 Intel Corporation
+# SPDX-License-Identifier: MPL-2.0
+
+import dev_util
+import stest
+
+for (order, bank) in [('little', obj.bank.le), ('big', obj.bank.be)]:
+    bank.log_level = 4
+    bank.r = 0x04030201
+    if order == 'little':
+        whole = dev_util.Register_LE(bank, 4, size=4)
+        one = dev_util.Register_LE(bank, 5, size=1)
+        three = dev_util.Register_LE(bank, 5, size=3)
+    else:
+        whole = dev_util.Register_BE(bank, 4, size=4)
+        one = dev_util.Register_BE(bank, 6, size=1)
+        three = dev_util.Register_BE(bank, 4, size=3)
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Read from register [lb]e.r -> 0x04030201'):
+        whole.read()
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Partial read from register [lb]e.r[[]15:8[]] -> 0x02'):
+        one.read()
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Partial read from register [lb]e.r[[]31:8[]] -> 0x040302'):
+        three.read()
+
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Write to register [lb]e.r <- 0x01234567'):
+        whole.write(0x01234567)
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Partial write to register [lb]e.r[[]15:8[]] <- 0x03'):
+        one.write(0x3)
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Partial write to register [lb]e.r[[]31:8[]] <- 0x012345'):
+        three.write(0x012345)
+    with stest.expect_log_mgr(
+            bank, 'info',
+            regex='Partially setting register [lb]e.r[[]31:8[]] <- 0x012345'):
+        simics.SIM_issue_transaction(
+            bank, simics.transaction_t(write=True, size=3,
+                                       data=(0x012345).to_bytes(3, order),
+                                       inquiry=True),
+            5 if order == 'little' else 4)