INTERNAL: Revert "FROMLIST: SQUASH: i965: SIMD32 selection heuristics"

This patch is causing visual artifacts on Celadon home screen, which is
troubling because it is supposed to be disabled by default. Reverting until we
find a solution.

Signed-off-by: Kevin Strasser <[email protected]>

Author: renchenglei

src/intel/compiler/brw_compiler.h

@@ -38,15 +38,6 @@ struct ra_regs;
 struct nir_shader;
 struct brw_program;
 
-struct brw_simd32_heuristics_control {
-   bool grouped_sends_check;
-   int max_grouped_sends;
-   bool inst_count_check;
-   float inst_count_ratio;
-   bool mrt_check;
-   int max_mrts;
-};
-
 struct brw_compiler {
    const struct gen_device_info *devinfo;
 
@@ -128,8 +119,6 @@ struct brw_compiler {
     * whether nir_opt_large_constants will be run.
     */
    bool supports_shader_constants;
-
-   struct brw_simd32_heuristics_control simd32_heuristics_control;
 };
 
 /**

src/intel/compiler/brw_fs.cpp

@@ -8240,8 +8240,6 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
                char **error_str)
 {
    const struct gen_device_info *devinfo = compiler->devinfo;
-   bool simd16_failed = false;
-   bool simd16_spilled = false;
 
    unsigned max_subgroup_size = unlikely(INTEL_DEBUG & DEBUG_DO32) ? 32 : 16;
 
@@ -8325,30 +8323,20 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
                      shader_time_index16);
       v16.import_uniforms(&v8);
       if (!v16.run_fs(allow_spilling, use_rep_send)) {
-         simd16_failed = true;
          compiler->shader_perf_log(log_data,
                                    "SIMD16 shader failed to compile: %s",
                                    v16.fail_msg);
       } else {
-         simd16_spilled = v16.spilled_any_registers;
          simd16_cfg = v16.cfg;
          prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs;
          prog_data->reg_blocks_16 = brw_register_blocks(v16.grf_used);
       }
    }
 
    /* Currently, the compiler only supports SIMD32 on SNB+ */
-   const brw_simd32_heuristics_control *ctrl = &compiler->simd32_heuristics_control;
-   uint64_t mrts = shader->info.outputs_written << FRAG_RESULT_DATA0;
-
    if (v8.max_dispatch_width >= 32 && !use_rep_send &&
        compiler->devinfo->gen >= 6 &&
-       (unlikely(INTEL_DEBUG & DEBUG_DO32) ||
-        (unlikely(INTEL_DEBUG & DEBUG_HEUR32) &&
-         !simd16_failed && !simd16_spilled &&
-         (!ctrl->mrt_check ||
-          (ctrl->mrt_check &&
-          u_count_bits64(&mrts) <= ctrl->max_mrts))))) {
+       unlikely(INTEL_DEBUG & DEBUG_DO32)) {
       /* Try a SIMD32 compile */
       fs_visitor v32(compiler, log_data, mem_ctx, &key->base,
                      &prog_data->base, shader, 32,
@@ -8359,12 +8347,9 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
                                    "SIMD32 shader failed to compile: %s",
                                    v32.fail_msg);
       } else {
-         if (likely(!(INTEL_DEBUG & DEBUG_HEUR32)) ||
-              v32.run_heuristic(ctrl)) {
-            simd32_cfg = v32.cfg;
-            prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs;
-            prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used);
-         }
+         simd32_cfg = v32.cfg;
+         prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs;
+         prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used);
       }
    }
 
@@ -8439,51 +8424,14 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
    }
 
    if (simd32_cfg) {
-      uint32_t offset = g.generate_code(simd32_cfg, 32);
-
-      if (unlikely(INTEL_DEBUG & DEBUG_DO32) ||
-          (unlikely(INTEL_DEBUG & DEBUG_HEUR32) &&
-           (!simd16_cfg ||
-            (simd16_cfg &&
-             (!ctrl->inst_count_check ||
-             (ctrl->inst_count_check &&
-             (float)g.get_inst_count(32) / (float)g.get_inst_count(16) <= ctrl->inst_count_ratio)))))) {
-         prog_data->dispatch_32 = true;
-         prog_data->prog_offset_32 = offset;
-         uint32_t offset = g.generate_code(simd32_cfg, 32);
-      }
-
+      prog_data->dispatch_32 = true;
+      prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32, stats);
+      stats = stats ? stats + 1 : NULL;
    }
 
    return g.get_assembly();
 }
 
-bool
-fs_visitor::run_heuristic(const struct brw_simd32_heuristics_control *ctrl) {
-   int grouped_sends = 0;
-   int max_grouped_sends = 0;
-   bool pass = true;
-
-   foreach_block_and_inst(block, fs_inst, inst, cfg) {
-      if (inst->opcode >= SHADER_OPCODE_TEX && inst->opcode <= SHADER_OPCODE_SAMPLEINFO_LOGICAL) {
-         ++grouped_sends;
-      } else if (grouped_sends > 0) {
-         if (grouped_sends > max_grouped_sends) {
-            max_grouped_sends = grouped_sends;
-         }
-         grouped_sends = 0;
-      }
-   }
-
-   if (ctrl->grouped_sends_check) {
-      if (max_grouped_sends > ctrl->max_grouped_sends) {
-         pass = false;
-      }
-   }
-
-   return pass;
-}
-
 fs_reg *
 fs_visitor::emit_cs_work_group_id_setup()
 {

src/intel/compiler/brw_fs.h

@@ -306,8 +306,6 @@ class fs_visitor : public backend_shader
    virtual void dump_instructions(const char *name);
    void dump_instruction(backend_instruction *inst);
    void dump_instruction(backend_instruction *inst, FILE *file);
-   
-   bool run_heuristic(const struct brw_simd32_heuristics_control *ctrl);
 
    const brw_base_prog_key *const key;
    const struct brw_sampler_prog_key_data *key_tex;
@@ -432,7 +430,6 @@ class fs_generator
    void enable_debug(const char *shader_name);
    int generate_code(const cfg_t *cfg, int dispatch_width,
                      struct brw_compile_stats *stats);
-   int get_inst_count(int dispatch_width);
    const unsigned *get_assembly();
 
 private:
@@ -528,7 +525,6 @@ class fs_generator
    struct brw_stage_prog_data * const prog_data;
 
    unsigned dispatch_width; /**< 8, 16 or 32 */
-   int inst_count[3]; /* for 8, 16 and 32 */
 
    exec_list discard_halt_patches;
    struct shader_stats shader_stats;

src/intel/compiler/brw_fs.h.rej

@@ -2430,8 +2430,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
       stats->fills = fill_count;
    }
 
-   inst_count[ffs(dispatch_width) - 4] = before_size / 16;
-
    return start_offset;
 }
 
@@ -2440,13 +2438,3 @@ fs_generator::get_assembly()
 {
    return brw_get_program(p, &prog_data->program_size);
 }
-
-int
-fs_generator::get_inst_count(int dispatch_width)
-{
-   if (dispatch_width == 8 || dispatch_width == 16 || dispatch_width == 32) {
-      return inst_count[ffs(dispatch_width) - 4];
-   } else {
-      return 0;
-   }
-}

src/intel/compiler/brw_fs_generator.cpp

@@ -86,7 +86,6 @@ static const struct debug_control debug_control[] = {
    { "color",       DEBUG_COLOR },
    { "reemit",      DEBUG_REEMIT },
    { "soft64",      DEBUG_SOFT64 },
-   { "heur32",      DEBUG_HEUR32 },
    { "tcs8",        DEBUG_TCS_EIGHT_PATCH },
    { "bt",          DEBUG_BT },
    { "pc",          DEBUG_PIPE_CONTROL },

src/intel/compiler/brw_fs_generator.cpp.rej

@@ -88,7 +88,6 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_BT                  (1ull << 44)
 #define DEBUG_PIPE_CONTROL        (1ull << 45)
 #define DEBUG_NO_FAST_CLEAR       (1ull << 46)
-#define DEBUG_HEUR32              (1ull << 47)
 
 /* These flags are not compatible with the disk shader cache */
 #define DEBUG_DISK_CACHE_DISABLE_MASK DEBUG_SHADER_TIME
@@ -97,7 +96,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_DISK_CACHE_MASK \
    (DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 |  DEBUG_SPILL_FS | \
    DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32 | DEBUG_SOFT64 | \
-   DEBUG_TCS_EIGHT_PATCH | DEBUG_HEUR32)
+   DEBUG_TCS_EIGHT_PATCH)
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"