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bump llvm
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17 files changed

+50
-49
lines changed

17 files changed

+50
-49
lines changed

‎cmake/llvm-version.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
add6b2f35f2bcf1f59a2ab2d5b3dab124fe0895a
1+
7842374103b26933d71a8fe354cd4d8715d55b1c

‎include/gc/Dialect/LLVMIR/XeVMOps.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ def XeVM_L1StoreCacheControl : XeVM_StoreCacheControl<"L1">;
7070
def XeVM_L3StoreCacheControl : XeVM_StoreCacheControl<"L3">;
7171

7272
def XeVM_BlockLoad2dOp : XeVM_Op<"blockload2d">,
73-
Results<(outs FixedVectorOf<[XeVM_ElemType]>:$res)>,
73+
Results<(outs FixedVectorOfRankAndType<[1,2,3], [XeVM_ElemType]>:$res)>,
7474
Arguments<(ins
7575
Arg<LLVM_AnyPointer, "", [MemRead]>:$ptr,
7676
I32:$base_width,
@@ -137,7 +137,7 @@ def XeVM_BlockStore2dOp : XeVM_Op<"blockstore2d">,
137137
I32Attr:$tile_width,
138138
I32Attr:$tile_height,
139139
I32Attr:$v_blocks,
140-
FixedVectorOf<[XeVM_ElemType]>:$stored_val,
140+
FixedVectorOfRankAndType<[1, 2, 3], [XeVM_ElemType]>:$stored_val,
141141
DefaultValuedAttr<XeVM_L1StoreCacheControl, "::mlir::xevm::L1StoreCacheControl::DEFAULT">:$l1_cache_control,
142142
DefaultValuedAttr<XeVM_L3StoreCacheControl, "::mlir::xevm::L3StoreCacheControl::DEFAULT">:$l3_cache_control
143143
)> {
@@ -243,7 +243,7 @@ def XeVM_PrecisionTypeAttr : I32EnumAttr<"PrecisionType",
243243
}
244244

245245
def XeVM_DPASOp : XeVM_Op<"dpas">,
246-
Results<(outs FixedVectorOf<[XeVM_MatrixElemType]>:$d)>,
246+
Results<(outs FixedVectorOfRankAndType<[1], [XeVM_MatrixElemType]>:$d)>,
247247
Arguments<(ins
248248
FixedVectorOfRankAndType<[1], [XeVM_MatrixElemType]>:$c,
249249
FixedVectorOfRankAndType<[1], [XeVM_MatrixElemType]>:$a,

‎include/gc/Transforms/Microkernel/BrgemmRuntimeUtils.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,13 +27,13 @@ static inline int64_t getDnnlDataTypeVal(RewriterBase &rewriter,
2727
auto context = rewriter.getContext();
2828
auto tattr = dyn_cast_or_null<TypeAttr>(attr);
2929
assert(tattr);
30-
if (tattr == TypeAttr::get(FloatType::getF32(context))) {
30+
if (tattr == TypeAttr::get(Float32Type::get(context))) {
3131
return static_cast<int64_t>(dnnl_f32);
32-
} else if (tattr == TypeAttr::get(FloatType::getF64(context))) {
32+
} else if (tattr == TypeAttr::get(Float64Type::get(context))) {
3333
return static_cast<int64_t>(dnnl_f64);
34-
} else if (tattr == TypeAttr::get(FloatType::getBF16(context))) {
34+
} else if (tattr == TypeAttr::get(BFloat16Type::get(context))) {
3535
return static_cast<int64_t>(dnnl_bf16);
36-
} else if (tattr == TypeAttr::get(FloatType::getF16(context))) {
36+
} else if (tattr == TypeAttr::get(Float16Type::get(context))) {
3737
return static_cast<int64_t>(dnnl_f16);
3838
} else if (tattr == TypeAttr::get(
3939
IntegerType::get(context, 32, IntegerType::Signed))) {

‎include/gc/Transforms/Utils/StructuredOpMatcher.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ struct HasStaticStrides {
163163
SmallVector<int64_t> strides;
164164
if (auto memRefType = dyn_cast_or_null<MemRefType>(operandType)) {
165165
int64_t offset;
166-
if (failed(getStridesAndOffset(memRefType, strides, offset)))
166+
if (failed(memRefType.getStridesAndOffset(strides, offset)))
167167
return false;
168168
if (llvm::any_of(strides, [](int64_t stride) {
169169
return stride == ShapedType::kDynamic;
@@ -244,7 +244,8 @@ struct NumDpsInits {
244244
// Callable object to validate number of input operands for `op`.
245245
struct NumDpsInputs {
246246
NumDpsInputs() = delete;
247-
explicit NumDpsInputs(std::function<bool(size_t)> fun) : fun(std::move(fun)){};
247+
explicit NumDpsInputs(std::function<bool(size_t)> fun)
248+
: fun(std::move(fun)){};
248249

249250
bool operator()(Operation *op) {
250251
if (auto linalgOp = dyn_cast_or_null<linalg::LinalgOp>(op))

‎lib/gc/Dialect/Linalgx/Utils.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -385,7 +385,7 @@ bool isGenericAttrEquivalent(linalg::GenericOp op, ShapedType shapeA,
385385
DenseMap<AffineExpr, AffineExpr> replaceMap;
386386
std::map<unsigned, utils::IteratorType> iterMap;
387387
// get shape-to-loop map
388-
AffineMap inverse = inversePermutation(concatAffineMaps(inMaps));
388+
AffineMap inverse = inversePermutation(concatAffineMaps(inMaps, context));
389389
assert(inverse && "shape-to-loops map to be non-null");
390390
assert(dimSize == inverse.getResults().size());
391391
// renumber the dim id based on shape-to-loop map

‎lib/gc/Dialect/Microkernel/MicrokernelOps.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -551,11 +551,11 @@ static LogicalResult verifyBrgemmDataTypes(ArrayAttr dtypes,
551551

552552
auto context = op.getContext();
553553

554-
#define FTAttr(t) TypeAttr::get(FloatType::get##t(context))
554+
#define FTAttr(t) TypeAttr::get(t::get(context))
555555
#define ITAttr(s, w) TypeAttr::get(IntegerType::get(context, w, IntegerType::s))
556556
SmallVector<std::pair<TypeAttr, TypeAttr>> validDataTypes = {
557-
{FTAttr(F32), FTAttr(F32)},
558-
{FTAttr(BF16), FTAttr(BF16)},
557+
{FTAttr(Float32Type), FTAttr(Float32Type)},
558+
{FTAttr(BFloat16Type), FTAttr(BFloat16Type)},
559559
{ITAttr(Unsigned, 8), ITAttr(Signed, 8)},
560560
{ITAttr(Signed, 8), ITAttr(Unsigned, 8)},
561561
{ITAttr(Unsigned, 8), ITAttr(Unsigned, 8)},

‎lib/gc/ExecutionEngine/GPURuntime/ocl/GpuOclRuntime.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -718,7 +718,7 @@ StringRef createStaticMain(OpBuilder &builder, ModuleOp &module,
718718
auto offsetPtr = constArgs.end();
719719
constArgs.emplace_back(0);
720720
constArgs.append(shape.begin(), shape.end());
721-
if (failed(getStridesAndOffset(type, constArgs, *offsetPtr))) {
721+
if (failed(type.getStridesAndOffset(constArgs, *offsetPtr))) {
722722
gcLogD("Failed to get strides and offset of arg", i,
723723
" of the function ", funcName.begin());
724724
return {};
@@ -929,8 +929,9 @@ OclModuleBuilder::build(const OclRuntime::Ext &ext) {
929929
builder.getI64IntegerAttr(static_cast<int64_t>(wgSize)));
930930
TargetDeviceSpecInterface devSpec =
931931
TargetDeviceSpecAttr::get(ctx, dltiAttrs);
932-
auto sysSpec =
933-
TargetSystemSpecAttr::get(ctx, ArrayRef(std::pair(devStr, devSpec)));
932+
DataLayoutEntryInterface dl =
933+
DataLayoutEntryAttr::get(ctx, devStr, devSpec);
934+
auto sysSpec = TargetSystemSpecAttr::get(ctx, ArrayRef(dl));
934935
mod = mlirModule.clone();
935936
mod.getOperation()->setAttr("#dlti.sys_spec", sysSpec);
936937
PassManager pm{ctx};

‎lib/gc/Transforms/DeepTileContractionOp.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,7 @@ generateOuterLoop(RewriterBase &b, linalg::LinalgOp linalgOp,
405405
// the extra copy generated by bufferization. So remove the dummy loop
406406
// at this early stage.
407407
if (!isDummyLoop(tilingResult->loops.back())) {
408-
b.replaceOp(currentOp, tilingResult->replacements);
408+
b.replaceOp(currentOp, tilingResult->mergeResult.replacements);
409409
currentOp = dyn_cast<linalg::LinalgOp>(tilingResult->tiledOps.back());
410410
if (iteratorTypes[d] == mlir::utils::IteratorType::reduction)
411411
result.reductionLoops.push_back(tilingResult->loops.back());
@@ -477,7 +477,7 @@ generateOuterLoop(RewriterBase &b, linalg::LinalgOp linalgOp,
477477
b, cast<TilingInterface>(currentOp.getOperation()), tileOption);
478478
if (failed(tilingResult))
479479
return failure();
480-
b.replaceOp(currentOp, tilingResult->replacements);
480+
b.replaceOp(currentOp, tilingResult->mergeResult.replacements);
481481
currentOp = dyn_cast<linalg::LinalgOp>(tilingResult->tiledOps.back());
482482
}
483483
}

‎lib/gc/Transforms/IterativeTilingAndFusion.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -813,7 +813,7 @@ void iterativeTilingAndFusionUntilExhaustion(
813813
defaultTilingOfType(rewriter, op, isaOpTy, cfg);
814814
if (succeeded(tilingResult)) {
815815
tiledOps.insert(tilingResult->tiledOps[0]);
816-
rewriter.replaceOp(op, tilingResult->replacements);
816+
rewriter.replaceOp(op, tilingResult->mergeResult.replacements);
817817
break;
818818
}
819819
}

‎lib/gc/Transforms/MemRefToCPURuntime.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ uint64_t getMemRefSizeInBytes(MemRefType memrefType) {
5151
if (!layout.isIdentity()) {
5252
int64_t offset;
5353
SmallVector<int64_t, 4> strides;
54-
if (failed(getStridesAndOffset(memrefType, strides, offset))) {
54+
if (failed(memrefType.getStridesAndOffset(strides, offset))) {
5555
return UINT64_MAX;
5656
}
5757

‎lib/gc/Transforms/Microkernel/ConvertMicrokernelToDnnlFunc.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ class ConvertBrgemmDispatchOpRewriter
6363
SmallVector<Value, 10> operands;
6464
SmallVector<Type, 10> operandTypes;
6565
IntegerType integer64 = IntegerType::get(rewriter.getContext(), 64);
66-
FloatType float32 = FloatType::getF32(rewriter.getContext());
66+
FloatType float32 = Float32Type::get(rewriter.getContext());
6767

6868
// M, N, K, LDA, LDB, LDC, stride_a, stride_b
6969
// they are in the same order with BrgemmDispatchOp inputs

‎lib/gc/Transforms/Utils/ValueUtils.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ FailureOr<SmallVector<int64_t>> getStrides(Value value) {
110110
auto memrefType = cast<MemRefType>(valueType);
111111
SmallVector<int64_t> strides;
112112
int64_t offset;
113-
if (failed(getStridesAndOffset(memrefType, strides, offset)))
113+
if (failed(memrefType.getStridesAndOffset(strides, offset)))
114114
return failure();
115115
return strides;
116116
}

‎src/dnnl/JsonParser.h

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (C) 2024 Intel Corporation
2+
* Copyright (C) 2025 Intel Corporation
33
*
44
* Licensed under the Apache License, Version 2.0 (the "License");
55
* you may not use this file except in compliance with the License.
@@ -12,7 +12,6 @@
1212
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
1313
* See the License for the specific language governing permissions
1414
* and limitations under the License.
15-
*
1615
* SPDX-License-Identifier: Apache-2.0
1716
*/
1817

@@ -179,8 +178,8 @@ class JsonParser {
179178
GC_DTYPE("u8", b.getIntegerType(8, true)),
180179
GC_DTYPE("f64", b.getF64Type()),
181180
GC_DTYPE("boolean", b.getI1Type()),
182-
GC_DTYPE("f8_e5m2", b.getFloat8E5M2Type()),
183-
GC_DTYPE("f8_e4m3", b.getFloat8E4M3FNType()),
181+
GC_DTYPE("f8_e5m2", mlir::Float8E5M2Type::get(b.getContext())),
182+
GC_DTYPE("f8_e4m3", mlir::Float8E4M3Type::get(b.getContext())),
184183
GC_DTYPE("s4", b.getIntegerType(4, false)),
185184
GC_DTYPE("u4", b.getIntegerType(4, true)),
186185
};

‎test/benchgc/src/benchgc/mlir/util.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -187,12 +187,12 @@ def attach_dlti(flags: argparse.Namespace, module: ir.Module):
187187
dlti_template = f"""
188188
module attributes {{
189189
dlti.target_system_spec = #dlti.target_system_spec<
190-
"CPU": #dlti.target_device_spec<
191-
#dlti.dl_entry<"L1_cache_size_in_bytes", {l1_data_cache_size} : ui32>,
192-
#dlti.dl_entry<"L2_cache_size_in_bytes", {l2_cache_size} : ui64>,
193-
#dlti.dl_entry<"L3_cache_size_in_bytes", {l3_cache_size} : ui64>,
194-
#dlti.dl_entry<"num_threads", {num_threads} : i32>,
195-
#dlti.dl_entry<"max_vector_width", {max_vector_width} : i64>>
190+
"CPU" = #dlti.target_device_spec<
191+
"L1_cache_size_in_bytes" = {l1_data_cache_size} : ui32,
192+
"L2_cache_size_in_bytes" = {l2_cache_size} : ui64,
193+
"L3_cache_size_in_bytes" = {l3_cache_size} : ui64,
194+
"num_threads" = {num_threads} : i32>,
195+
"max_vector_width" = {max_vector_width} : i64>
196196
>}} {{}}
197197
"""
198198
with module.context:

‎test/mlir/test/gc/Transforms/deepTileContractionNamedOp.mlir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -150,12 +150,12 @@ func.func @matmul_2Dx4D_bf16(%arg0: tensor<4096x4096xbf16>, %arg1: tensor<128x12
150150

151151
module attributes {
152152
dlti.target_system_spec = #dlti.target_system_spec<
153-
"CPU": #dlti.target_device_spec<
154-
#dlti.dl_entry<"L1_cache_size_in_bytes", 49152 : i32>,
155-
#dlti.dl_entry<"L2_cache_size_in_bytes", 2097152 : i32>,
156-
#dlti.dl_entry<"L3_cache_size_in_bytes", 110100480 : i32>,
157-
#dlti.dl_entry<"num_threads", 56 : i32>,
158-
#dlti.dl_entry<"max_vector_width", 512 : i32>>
153+
"CPU" = #dlti.target_device_spec<
154+
"L1_cache_size_in_bytes" = 49152 : i32,
155+
"L2_cache_size_in_bytes" = 2097152 : i32,
156+
"L3_cache_size_in_bytes" = 110100480 : i32,
157+
"num_threads" = 56 : i32,
158+
"max_vector_width" = 512 : i32>
159159
>} {
160160
// CHECK: #[[mapA:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d1, d3 * 2 + d4)>
161161
// CHECK: #[[mapB:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d3, d2, d4)>

‎test/mlir/unittests/Analysis/TargetDescriptionAnalysisTest.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,12 +26,12 @@ using namespace mlir;
2626
static const char code1[] = R"mlir(
2727
module attributes {
2828
dlti.target_system_spec = #dlti.target_system_spec<
29-
"CPU": #dlti.target_device_spec<
30-
#dlti.dl_entry<"L1_cache_size_in_bytes", 49152 : ui32>,
31-
#dlti.dl_entry<"L2_cache_size_in_bytes", 2097152 : ui64>,
32-
#dlti.dl_entry<"L3_cache_size_in_bytes", "110100480">,
33-
#dlti.dl_entry<"num_threads", 56 : i32>,
34-
#dlti.dl_entry<"max_vector_width", 512 : i64>>
29+
"CPU" = #dlti.target_device_spec<
30+
"L1_cache_size_in_bytes" = 49152 : ui32,
31+
"L2_cache_size_in_bytes" = 2097152 : ui64,
32+
"L3_cache_size_in_bytes" = "110100480",
33+
"num_threads" = 56 : i32,
34+
"max_vector_width" = 512 : i64>
3535
>} {}
3636
)mlir";
3737

@@ -56,9 +56,9 @@ TEST(TargetDescriptionAnalysis, CPUNormal) {
5656
static const char code2[] = R"mlir(
5757
module attributes {
5858
dlti.target_system_spec = #dlti.target_system_spec<
59-
"CPU": #dlti.target_device_spec<
60-
#dlti.dl_entry<"L1_cache_size_in_bytes", 49152 : ui32>,
61-
#dlti.dl_entry<"L2_cache_size_in_bytes", 2097152 : ui32>>
59+
"CPU" = #dlti.target_device_spec<
60+
"L1_cache_size_in_bytes" = 49152 : ui32>,
61+
"L2_cache_size_in_bytes" = 2097152 : ui32>
6262
>} {}
6363
)mlir";
6464

‎test/mlir/unittests/ExecutionEngine/IMEX/IMEXGpuOclRuntimeTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ module @test {
6262
)mlir";
6363

6464
constexpr char matmulAddStatic[] = R"mlir(
65-
module @fragment_name attributes {"#dlti.sys_spec" = #dlti.target_system_spec<"GPU" : #dlti.target_device_spec<#dlti.dl_entry<"max_work_group_size", 16 : i64>>>} {
65+
module @fragment_name attributes {"#dlti.sys_spec" = #dlti.target_system_spec<"GPU" = #dlti.target_device_spec<"max_work_group_size" = 16 : i64>>} {
6666
func.func @entry(%arg0: memref<128x256xf16>, %arg1: memref<256x256xf16>, %arg2: memref<128x256xf16>) {
6767
%0 = bufferization.to_tensor %arg0 restrict : memref<128x256xf16>
6868
%1 = bufferization.to_tensor %arg1 restrict : memref<256x256xf16>

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