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xurui1995xurui1995
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Merge branch 'main' into xurui/add_benchmark
2 parents 524bd7d + 8948c6b commit 95b3cc8

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‎docs/deep_tile_matmul_design.md

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‎include/gc/Analysis/MatmulConfigAnalysis.h

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//===-- MatmulConfigAnalysis.h - the analysis for matmul config -*- C++ -*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_ANALYSIS_MATMULCONFIGANALYSIS_H
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#define MLIR_ANALYSIS_MATMULCONFIGANALYSIS_H
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#include "gc/Dialect/Linalgx/LinalgxOps.h"
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#include "mlir/Dialect/DLTI/DLTI.h"
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#include "mlir/Dialect/Linalg/IR/Linalg.h"
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#include "mlir/Interfaces/DataLayoutInterfaces.h"
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namespace mlir {
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namespace gc {
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using namespace mlir;
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// The configuration for matmul tiling
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// TODO: support batch matmul
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struct MatmulConfig {
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// The number of threads distributed to M, N, K
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uint32_t MThreads, NThreads, KThreads;
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// The outer block size for M, N, K which will be used to decide the loop tile
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// size in single thread
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uint32_t MBlock, NBlock, KBlock;
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// The innermost block size for M, N, K which will be directly converted to
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// brgemm.
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uint32_t innerMostMBlock, innerMostNBlock, innerMostKBlock;
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};
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enum DimType { Batch, M, N, K };
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// Extract the index of the given DimType in the DimType list
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inline SmallVector<unsigned> extractDimTypeIdx(ArrayRef<DimType> tyList,
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DimType ty) {
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SmallVector<unsigned> idxList;
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for (auto [idx, type] : llvm::enumerate(tyList)) {
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if (type == ty) {
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idxList.push_back(idx);
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}
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}
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return idxList;
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}
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// Get the operand dim type for every operand for the given linalg op
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inline FailureOr<SmallVector<SmallVector<DimType>>>
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getOprandDimType(linalg::LinalgOp &linalgOp) {
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// TODO: replace the linalgx op with generic op
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if (llvm::isa<linalg::MatmulOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::M, DimType::K},
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SmallVector<DimType>{DimType::K, DimType::N},
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SmallVector<DimType>{DimType::M, DimType::N}};
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} else if (llvm::isa<linalgx::Mm2DVnniOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::M, DimType::K},
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SmallVector<DimType>{DimType::N, DimType::K, DimType::K, DimType::N,
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DimType::K},
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SmallVector<DimType>{DimType::M, DimType::N, DimType::M, DimType::N}};
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} else if (llvm::isa<linalgx::Mm4DVnniOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::M, DimType::K, DimType::M, DimType::K},
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SmallVector<DimType>{DimType::N, DimType::K, DimType::K, DimType::N,
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DimType::K},
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SmallVector<DimType>{DimType::M, DimType::N, DimType::M, DimType::N}};
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} else if (llvm::isa<linalg::BatchMatmulOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::Batch, DimType::M, DimType::K},
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SmallVector<DimType>{DimType::Batch, DimType::K, DimType::N},
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SmallVector<DimType>{DimType::Batch, DimType::M, DimType::N}};
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} else if (llvm::isa<linalg::MatmulTransposeAOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::K, DimType::M},
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SmallVector<DimType>{DimType::K, DimType::N},
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SmallVector<DimType>{DimType::M, DimType::N}};
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} else if (llvm::isa<linalg::MatmulTransposeBOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::M, DimType::K},
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SmallVector<DimType>{DimType::N, DimType::K},
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SmallVector<DimType>{DimType::M, DimType::N}};
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} else if (llvm::isa<linalg::BatchMatmulTransposeAOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::Batch, DimType::K, DimType::M},
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SmallVector<DimType>{DimType::Batch, DimType::K, DimType::N},
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SmallVector<DimType>{DimType::Batch, DimType::M, DimType::N}};
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} else if (llvm::isa<linalg::BatchMatmulTransposeBOp>(linalgOp)) {
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return SmallVector<SmallVector<DimType>>{
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SmallVector<DimType>{DimType::Batch, DimType::M, DimType::K},
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SmallVector<DimType>{DimType::Batch, DimType::N, DimType::K},
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SmallVector<DimType>{DimType::Batch, DimType::M, DimType::N}};
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}
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return failure();
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}
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// The analysis to extract the matmul configuration from the given linalg op
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struct MatmulConfigAnalysis {
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public:
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explicit MatmulConfigAnalysis(Operation *root);
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MatmulConfig getConfig() { return config; }
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private:
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MatmulConfig config;
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};
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} // namespace gc
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} // namespace mlir
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#endif

‎include/gc/Transforms/Passes.td

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include "mlir/Pass/PassBase.td"
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def TileLinalgNamed : Pass<"tile-named-linalg", "func::FuncOp"> {
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let summary = "Tile linalg named operations.";
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let dependentDialects =
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["linalg::LinalgDialect", "scf::SCFDialect", "tensor::TensorDialect"];
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}
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#ifdef GC_HAS_ONEDNN_DIALECT
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def ConvertOneDNNGraphToLinalg : Pass<"convert-onednn-graph-to-linalg"> {
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let summary =
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"Decide if enable cost model to control iterative fusion.">,
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ListOption<"defaultTileSize", "default-tile-size", "std::string",
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"Set default TileSize for the certain type of op, saying `matmul:{32,32}`">,
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];
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}
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def DeepTileContractionNamedOp
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: Pass<"deep-tile-contraction-named-op", "func::FuncOp"> {
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let summary = "Tile linalg contraction named operation deeply";
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let description =
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[{The pass tries to tile the linalg contraction named op deeply.}];
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let dependentDialects = [
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"func::FuncDialect",
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"arith::ArithDialect",
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"tensor::TensorDialect",
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"linalg::LinalgDialect",
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];
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}
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];
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}
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def SinkOpIntoInnerLoop : Pass<"sink-op-into-inner-loop"> {
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let summary = "Sink operations into inner loops";
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let description = [{The pass tries to sink operations into inner loops as deep as possible to maximize the chance for outer loop optimization.
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}];
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let dependentDialects = [];
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}
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def MergeNestedForall : Pass<"merge-nested-forall"> {
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let summary = "Merge nested scf.forall operations";
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let description = [{The pass tries to merge nested forall operations.}];
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let dependentDialects = ["scf::SCFDialect"];
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}
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#endif // GC_DIALECT_GC_PASSES

‎lib/gc/Analysis/CMakeLists.txt

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gc_add_mlir_library(GcAnalysis
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TargetDescriptionAnalysis.cpp
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MatmulConfigAnalysis.cpp
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DEPENDS
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GraphCompilerPassIncGen
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${mlir_dialect_libs}
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${MLIR_LINK_COMPONENTS}
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GcInterface
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)
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)

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