diff --git a/.github/workflows/freebsd_build.yml b/.github/workflows/freebsd_build.yml
index ed07c46b..145e012f 100644
--- a/.github/workflows/freebsd_build.yml
+++ b/.github/workflows/freebsd_build.yml
@@ -32,11 +32,12 @@ jobs:
         operating_system: freebsd
         version: '14.2'
         run: |
+          export IGNORE_OSVERSION=yes
           sudo mkdir -p /usr/local/etc/pkg/repos
           sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf'
-          sudo pkg update -f
-          sudo pkg upgrade -y
-          sudo pkg install -y curl gmake cmake
+          sudo -E pkg update -f
+          sudo -E pkg upgrade -y
+          sudo -E pkg install -y curl gmake cmake
           pwd
           ls -lah
           whoami
diff --git a/.github/workflows/freebsd_scan_build.yml b/.github/workflows/freebsd_scan_build.yml
index 1446eb42..b9a4375e 100644
--- a/.github/workflows/freebsd_scan_build.yml
+++ b/.github/workflows/freebsd_scan_build.yml
@@ -32,11 +32,12 @@ jobs:
         operating_system: freebsd
         version: '14.2'
         run: |
+          export IGNORE_OSVERSION=yes
           sudo mkdir -p /usr/local/etc/pkg/repos
           sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf'
-          sudo pkg update -f
-          sudo pkg upgrade -y
-          sudo pkg install -y curl gmake cmake devel/llvm llvm
+          sudo -E pkg update -f
+          sudo -E pkg upgrade -y
+          sudo -E pkg install -y curl gmake cmake devel/llvm llvm
           pwd
           ls -lah
           whoami
diff --git a/.gitignore b/.gitignore
index 86e6584c..8aade9ba 100644
--- a/.gitignore
+++ b/.gitignore
@@ -34,3 +34,4 @@ latex/
 build
 src/simdjson
 .vscode/
+_codeql_build_dir/
diff --git a/_codeql_detected_source_root b/_codeql_detected_source_root
new file mode 120000
index 00000000..945c9b46
--- /dev/null
+++ b/_codeql_detected_source_root
@@ -0,0 +1 @@
+.
\ No newline at end of file
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 1c87ba30..aec24e1a 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -8,7 +8,7 @@ set(PROJECT_NAMES pcm pcm-numa pcm-latency pcm-power pcm-msr pcm-memory pcm-tsx
 
 set(MINIMUM_OPENSSL_VERSION 1.1.1)
 
-file(GLOB COMMON_SOURCES pcm-accel-common.cpp msr.cpp cpucounters.cpp pci.cpp mmio.cpp tpmi.cpp pmt.cpp bw.cpp utils.cpp topology.cpp debug.cpp threadpool.cpp uncore_pmu_discovery.cpp pcm-iio-pmu.cpp lspci.cpp ${PCM_PUGIXML_CPP})
+file(GLOB COMMON_SOURCES pcm-accel-common.cpp msr.cpp cpucounters.cpp pci.cpp mmio.cpp tpmi.cpp pmt.cpp bw.cpp utils.cpp topology.cpp debug.cpp threadpool.cpp uncore_pmu_discovery.cpp pcm-iio-pmu.cpp pcm-iio-topology.cpp lspci.cpp ${PCM_PUGIXML_CPP})
 
 if (APPLE)
   file(GLOB UNIX_SOURCES dashboard.cpp)
diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp
index 14d903f0..b45b5e78 100644
--- a/src/cpucounters.cpp
+++ b/src/cpucounters.cpp
@@ -717,6 +717,7 @@ void PCM::initCStateSupportTables()
         case MTL:
         case LNL:
         case ARL:
+        case PTL:
         case SNOWRIDGE:
         case ELKHART_LAKE:
         case JASPER_LAKE:
@@ -798,6 +799,7 @@ void PCM::initCStateSupportTables()
         case MTL:
         case LNL:
         case ARL:
+        case PTL:
         case SNOWRIDGE:
         case ELKHART_LAKE:
         case JASPER_LAKE:
@@ -1695,6 +1697,7 @@ bool PCM::detectNominalFrequency()
                || cpu_family_model == MTL
                || cpu_family_model == LNL
                || cpu_family_model == ARL
+               || cpu_family_model == PTL
                || cpu_family_model == SKX
                || cpu_family_model == ICX
                || cpu_family_model == SPR
@@ -1974,6 +1977,7 @@ void PCM::initUncoreObjects()
            case MTL: // TGLClientBW works fine for MTL
            case LNL: // TGLClientBW works fine for LNL
            case ARL: // TGLClientBW works fine for ARL
+           case PTL: // TGLClientBW works fine for PTL
                clientBW = std::make_shared<TGLClientBW>();
                break;
 /*         Disabled since ADLClientBW requires 2x multiplier for BW on top
@@ -3417,6 +3421,7 @@ bool PCM::isCPUModelSupported(const int model_)
             || model_ == MTL
             || model_ == LNL
             || model_ == ARL
+            || model_ == PTL
             || model_ == SKX
             || model_ == ICX
             || model_ == SPR
@@ -3599,6 +3604,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter
                        || cpu_family_model == MTL
                        || cpu_family_model == LNL
                        || cpu_family_model == ARL
+                       || cpu_family_model == PTL
                          ))
     {
         canUsePerf = false;
@@ -3688,6 +3694,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter
             case MTL:
             case LNL:
             case ARL:
+            case PTL:
                 LLCArchEventInit(hybridAtomEventDesc);
                 hybridAtomEventDesc[2].event_number = SKL_MEM_LOAD_RETIRED_L2_MISS_EVTNR;
                 hybridAtomEventDesc[2].umask_value = SKL_MEM_LOAD_RETIRED_L2_MISS_UMASK;
@@ -4980,12 +4987,8 @@ bool PCM::PMUinUse()
     return false;
 }
 
-const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const
+const char * PCM::cpuFamilyModelToUArchCodename(const int32 cpu_family_model_, const int32 cpu_stepping_)
 {
-    auto cpu_family_model_ = cpu_family_model_param;
-    if(cpu_family_model_ < 0)
-        cpu_family_model_ = this->cpu_family_model;
-
     switch(cpu_family_model_)
     {
         case CENTERTON:
@@ -5067,17 +5070,19 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const
             return "Lunar Lake";
         case ARL:
             return "Arrow Lake";
+        case PTL:
+            return "Panther Lake";
         case SKX:
-            if (cpu_family_model_param >= 0)
+            if (cpu_stepping_ < 0)
             {
-                // query for specified cpu_family_model_param, stepping not provided
+                // Stepping is not provided
                 return "Skylake-SP, Cascade Lake-SP";
             }
-            if (isCLX())
+            if (isCLX(cpu_family_model_, cpu_stepping_))
             {
                 return "Cascade Lake-SP";
             }
-            if (isCPX())
+            if (isCPX(cpu_family_model_, cpu_stepping_))
             {
                 return "Cooper Lake";
             }
@@ -5100,6 +5105,18 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const
     return "unknown";
 }
 
+const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const
+{
+    auto cpu_family_model_ = cpu_family_model_param;
+    auto cpu_stepping_ = -1;
+    if (cpu_family_model_ < 0) {
+        cpu_family_model_ = this->cpu_family_model;
+        cpu_stepping_ = this->cpu_stepping;
+    }
+
+    return cpuFamilyModelToUArchCodename(cpu_family_model_, cpu_stepping_);
+}
+
 #ifdef PCM_USE_PERF
 void PCM::closePerfHandles(const bool silent)
 {
@@ -10348,6 +10365,11 @@ uint32 PCM::getMaxNumOfIIOStacks() const
     return 0;
 }
 
+uint32 PCM::getMaxNumOfIOStacks() const
+{
+    return getMaxNumOfIIOStacks();
+}
+
 void PCM::programCboOpcodeFilter(const uint32 opc0, UncorePMU & pmu, const uint32 nc_, const uint32 opc1, const uint32 loc, const uint32 rem)
 {
     if (JAKETOWN == cpu_family_model)
diff --git a/src/cpucounters.h b/src/cpucounters.h
index 2aafa00c..0ca20ddb 100644
--- a/src/cpucounters.h
+++ b/src/cpucounters.h
@@ -313,7 +313,7 @@ class IDX_PMU
     std::vector<HWRegisterPtr> counterFilterENG;
     std::vector<HWRegisterPtr> counterFilterTC;
     std::vector<HWRegisterPtr> counterFilterPGSZ;
-    std::vector<HWRegisterPtr> counterFilterXFERSZ; 
+    std::vector<HWRegisterPtr> counterFilterXFERSZ;
 
     IDX_PMU(const bool perfMode_,
         const uint32 numaNode_,
@@ -570,7 +570,6 @@ class SimpleCounterState
     friend uint64 getNumberOfEvents(const T & before, const T & after);
     friend class PCM;
     uint64 data;
-
 public:
     SimpleCounterState() : data(0)
     { }
@@ -957,6 +956,7 @@ class PCM_API PCM
         THRESH,
         CH_MASK,
         FC_MASK,
+        UNIT_TYPE,
         /* Below are not part of perfmon definition */
         H_EVENT_NAME,
         V_EVENT_NAME,
@@ -1281,9 +1281,14 @@ class PCM_API PCM
     void programCXLCM(const uint64* events);
     void cleanupUncorePMUs(const bool silent = false);
 
+    static bool isCLX(int cpu_family_model_, int cpu_stepping_)
+    {
+        return (PCM::SKX == cpu_family_model_) && (cpu_stepping_ > 4 && cpu_stepping_ < 8);
+    }
+
     bool isCLX() const // Cascade Lake-SP
     {
-        return (PCM::SKX == cpu_family_model) && (cpu_stepping > 4 && cpu_stepping < 8);
+        return isCLX(cpu_family_model, cpu_stepping);
     }
 
     static bool isCPX(int cpu_family_model_, int cpu_stepping_) // Cooper Lake
@@ -1397,6 +1402,9 @@ class PCM_API PCM
     //! \brief Returns the number of IIO stacks per socket
     uint32 getMaxNumOfIIOStacks() const;
 
+    //! \brief Returns the number of IO stacks per socket
+    uint32 getMaxNumOfIOStacks() const;
+
     /*! \brief Returns the number of IDX accel devs
         \param accel index of IDX accel
     */
@@ -1682,6 +1690,7 @@ class PCM_API PCM
             case MTL:
             case LNL:
             case ARL:
+            case PTL:
                 if (topology[coreID].core_type == TopologyEntry::Atom)
                 {
                     return eCoreOCREvent;
@@ -1701,6 +1710,7 @@ class PCM_API PCM
        case MTL:
        case LNL:
        case ARL:
+       case PTL:
            useGLCOCREvent = true;
            break;
 
@@ -1753,7 +1763,7 @@ class PCM_API PCM
 
             One needs to call this method when your program finishes or/and you are not going to use the
             performance counting routines anymore.
-*/
+    */
     void cleanup(const bool silent = false);
 
     /*! \brief Forces PMU reset
@@ -1831,7 +1841,7 @@ class PCM_API PCM
             \return Number of sockets in the system
     */
     uint32 getNumSockets() const;
-    
+
     /*! \brief Reads  the accel type in the system
         \return acceltype
     */
@@ -1849,7 +1859,7 @@ class PCM_API PCM
 
     /*! \brief Sets the Number of AccelCounters in the system
         \return number of counters
-    */          
+    */
     void setNumberofAccelCounters(uint32 input);
 
     /*! \brief Reads number of online sockets (CPUs) in the system
@@ -1960,6 +1970,7 @@ class PCM_API PCM
         LNL =           PCM_CPU_FAMILY_MODEL(6, 0xBD),
         ARL =           PCM_CPU_FAMILY_MODEL(6, 197),
         ARL_1 =         PCM_CPU_FAMILY_MODEL(6, 198),
+        PTL =           PCM_CPU_FAMILY_MODEL(6, 204),
         BDX =           PCM_CPU_FAMILY_MODEL(6, 79),
         KNL =           PCM_CPU_FAMILY_MODEL(6, 87),
         SKL =           PCM_CPU_FAMILY_MODEL(6, 94),
@@ -2201,6 +2212,7 @@ class PCM_API PCM
             return 6;
         case LNL:
         case ARL:
+        case PTL:
             return 12;
         case SNOWRIDGE:
         case ELKHART_LAKE:
@@ -2422,19 +2434,18 @@ class PCM_API PCM
 
     //! \brief Control QAT telemetry service
     //! \param dev device index
-    //! \param operation control code 
+    //! \param operation control code
     void controlQATTelemetry(uint32 dev, uint32 operation);
 
     //! \brief Program IDX events
     //! \param events config of event to program
-    //! \param filters_wq filters(work queue) of event to program 
-    //! \param filters_eng filters(engine) of event to program 
-    //! \param filters_tc filters(traffic class) of event to program 
-    //! \param filters_pgsz filters(page size) of event to program 
-    //! \param filters_xfersz filters(transfer size) of event to program 
+    //! \param filters_wq filters(work queue) of event to program
+    //! \param filters_eng filters(engine) of event to program
+    //! \param filters_tc filters(traffic class) of event to program
+    //! \param filters_pgsz filters(page size) of event to program
+    //! \param filters_xfersz filters(transfer size) of event to program
     void programIDXAccelCounters(uint32 accel, std::vector<uint64_t> &events, std::vector<uint32> &filters_wq, std::vector<uint32> &filters_eng, std::vector<uint32> &filters_tc, std::vector<uint32> &filters_pgsz, std::vector<uint32> &filters_xfersz);
 
-
     //! \brief Get the state of IIO counter
     //! \param socket socket of the IIO stack
     //! \param IIOStack id of the IIO stack
@@ -2465,6 +2476,11 @@ class PCM_API PCM
     //! \param cpu_family_model_ cpu model (if no parameter provided the codename of the detected CPU is returned)
     const char * getUArchCodename(const int32 cpu_family_model_ = -1) const;
 
+    //! \brief Convert CPU Family/Model/Stepping to microarchitecture codename
+    //! \param cpu_family_model_ cpu family model
+    //! \param cpu_stepping necessary for some CPU models to distinguish between different microarchitectures
+    static const char * cpuFamilyModelToUArchCodename(const int32 cpu_family_model_, const int32 cpu_stepping_ = -1);
+
     //! \brief Get Brand string of processor
     static std::string getCPUBrandString();
     std::string getCPUFamilyModelString();
@@ -2553,6 +2569,7 @@ class PCM_API PCM
                  || cpu_family_model == PCM::MTL
                  || cpu_family_model == PCM::LNL
                  || cpu_family_model == PCM::ARL
+                 || cpu_family_model == PCM::PTL
                  || cpu_family_model == PCM::SPR
                  || cpu_family_model == PCM::EMR
                  || cpu_family_model == PCM::GNR
@@ -2593,6 +2610,7 @@ class PCM_API PCM
             || cpu_family_model == PCM::MTL
             || cpu_family_model == PCM::LNL
             || cpu_family_model == PCM::ARL
+            || cpu_family_model == PCM::PTL
             || cpu_family_model == PCM::SPR
             || cpu_family_model == PCM::EMR
             || cpu_family_model == PCM::GNR
@@ -2668,7 +2686,7 @@ class PCM_API PCM
             || cpu_family_model == PCM::GNR_D
             );
     }
-    
+
     bool memoryTrafficMetricsAvailable() const
     {
         return (!(isAtom() || cpu_family_model == PCM::CLARKDALE))
@@ -2893,6 +2911,7 @@ class PCM_API PCM
             || cpu_family_model == MTL
             || cpu_family_model == LNL
             || cpu_family_model == ARL
+            || cpu_family_model == PTL
             || useSKLPath()
             ;
     }
@@ -4458,6 +4477,7 @@ uint64 getL2CacheMisses(const CounterStateType & before, const CounterStateType
         || cpu_family_model == PCM::MTL
         || cpu_family_model == PCM::LNL
         || cpu_family_model == PCM::ARL
+        || cpu_family_model == PCM::PTL
         ) {
         return after.Event[BasicCounterState::SKLL2MissPos] - before.Event[BasicCounterState::SKLL2MissPos];
     }
@@ -4574,6 +4594,7 @@ uint64 getL3CacheHitsSnoop(const CounterStateType & before, const CounterStateTy
         || cpu_family_model == PCM::MTL
         || cpu_family_model == PCM::LNL
         || cpu_family_model == PCM::ARL
+        || cpu_family_model == PCM::PTL
         )
     {
         const int64 misses = getL3CacheMisses(before, after);
diff --git a/src/opCode-6-106.txt b/src/opCode-6-106.txt
index 8de50f50..2bd1077e 100644
--- a/src/opCode-6-106.txt
+++ b/src/opCode-6-106.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4)
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4)
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-108.txt b/src/opCode-6-108.txt
index 8de50f50..2bd1077e 100644
--- a/src/opCode-6-108.txt
+++ b/src/opCode-6-108.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4)
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4)
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-134.txt b/src/opCode-6-134.txt
index b5256ce7..4c8e744f 100644
--- a/src/opCode-6-134.txt
+++ b/src/opCode-6-134.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4)
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4)
-ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4)
-ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4)
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4)
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
\ No newline at end of file
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
\ No newline at end of file
diff --git a/src/opCode-6-143.txt b/src/opCode-6-143.txt
index f2360e2a..7a4dfc3d 100644
--- a/src/opCode-6-143.txt
+++ b/src/opCode-6-143.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-173.txt b/src/opCode-6-173.txt
index c3ccfbc9..821de1c2 100644
--- a/src/opCode-6-173.txt
+++ b/src/opCode-6-173.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-174.txt b/src/opCode-6-174.txt
index c3ccfbc9..821de1c2 100644
--- a/src/opCode-6-174.txt
+++ b/src/opCode-6-174.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-175.txt b/src/opCode-6-175.txt
index c3ccfbc9..821de1c2 100644
--- a/src/opCode-6-175.txt
+++ b/src/opCode-6-175.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-182.txt b/src/opCode-6-182.txt
index c3ccfbc9..821de1c2 100644
--- a/src/opCode-6-182.txt
+++ b/src/opCode-6-182.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-207.txt b/src/opCode-6-207.txt
index f2360e2a..7a4dfc3d 100644
--- a/src/opCode-6-207.txt
+++ b/src/opCode-6-207.txt
@@ -1,45 +1,45 @@
 #Clockticks
-#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total
+#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5
-ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6
-ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5
-ctr=2,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6
-ctr=3,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5
-ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6
-ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5
+ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6
+ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7
 # IOMMU events
-ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total
-ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total
-ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total
+ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total
+ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total
diff --git a/src/opCode-6-85.txt b/src/opCode-6-85.txt
index 34179b85..73d93176 100644
--- a/src/opCode-6-85.txt
+++ b/src/opCode-6-85.txt
@@ -1,26 +1,26 @@
 # Inbound (PCIe device DMA into system) payload events
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part3 (4th x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part1 (2nd x4)
-ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4)
-ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part3 (4th x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part1 (2nd x4)
+ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4)
+ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part3 (4th x4)
 # Outbound (CPU MMIO to the PCIe device) payload events
-ctr=2,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part1 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part3 (4th x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part1 (2nd x4)
-ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4)
-ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part3 (4th x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part1 (2nd x4)
+ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4)
+ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part3 (4th x4)
 # VTd events
-ctr=0,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Hit,vname=Total
-ctr=1,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total
-ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d CTXT Miss,vname=Total
-ctr=3,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L1 Miss,vname=Total
-ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L2 Miss,vname=Total
-ctr=1,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L3 Miss,vname=Total
-ctr=2,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d Mem Read,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Hit,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d CTXT Miss,vname=Total
+ctr=3,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d L1 Miss,vname=Total
+ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d L2 Miss,vname=Total
+ctr=1,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=VT-d L3 Miss,vname=Total
+ctr=2,unit=iio,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,hname=VT-d Mem Read,vname=Total
diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp
index e712fcc0..9b0dd49d 100644
--- a/src/pcm-iio-pmu.cpp
+++ b/src/pcm-iio-pmu.cpp
@@ -1,20 +1,21 @@
 // SPDX-License-Identifier: BSD-3-Clause
-// Copyright (c) 2017-2022, Intel Corporation
+// Copyright (c) 2017-2025, Intel Corporation
 
 // written by Patrick Lu,
 //            Aaron Cruz
+//            Alexander Antonov
 //            and others
+#include <numeric>
 
 #include "pcm-iio-pmu.h"
+#include "pcm-iio-topology.h"
 
-result_content results;
-
-vector<string> combine_stack_name_and_counter_names(string stack_name, const map<string,std::pair<h_id,std::map<string,v_id>>> &nameMap)
+vector<string> combine_stack_name_and_counter_names(string stack_name, const PCIeEventNameMap& nameMap)
 {
     vector<string> v;
     vector<string> tmp(nameMap.size());
     v.push_back(stack_name);
-    for (std::map<string,std::pair<h_id,std::map<string,v_id>>>::const_iterator iunit = nameMap.begin(); iunit != nameMap.end(); ++iunit) {
+    for (auto iunit = nameMap.begin(); iunit != nameMap.end(); ++iunit) {
         string h_name = iunit->first;
         int h_id = (iunit->second).first;
         tmp[h_id] = h_name;
@@ -80,75 +81,6 @@ void build_pci_tree(vector<string> &buffer, const PCIDB & pciDB, uint32_t column
     }
 }
 
-vector<string> build_display(vector<struct iio_stacks_on_socket>& iios, vector<struct iio_counter>& ctrs, const PCIDB& pciDB,
-                             const map<string,std::pair<h_id,std::map<string,v_id>>> &nameMap)
-{
-    vector<string> buffer;
-    vector<string> headers;
-    vector<struct data> data;
-    uint64_t header_width;
-    string row;
-    for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) {
-        buffer.push_back("Socket" + std::to_string(socket->socket_id));
-        for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) {
-            auto stack_id = stack->iio_unit_id;
-            headers = combine_stack_name_and_counter_names(stack->stack_name, nameMap);
-            //Print first row
-            row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer);
-            header_width = row.size();
-            buffer.push_back(row);
-            //Print a_title
-            row = std::accumulate(headers.begin(), headers.end(), string("|"), a_title);
-            buffer.push_back(row);
-            //Print deliminator
-            row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer);
-            buffer.push_back(row);
-            //Print data
-            std::map<uint32_t,map<uint32_t,struct iio_counter*>> v_sort;
-            //re-organize data collection to be row wise
-            for (std::vector<struct iio_counter>::iterator counter = ctrs.begin(); counter != ctrs.end(); ++counter) {
-                v_sort[counter->v_id][counter->h_id] = &(*counter);
-            }
-            for (std::map<uint32_t,map<uint32_t,struct iio_counter*>>::const_iterator vunit = v_sort.cbegin(); vunit != v_sort.cend(); ++vunit) {
-                map<uint32_t, struct iio_counter*> h_array = vunit->second;
-                uint32_t vv_id = vunit->first;
-                vector<uint64_t> h_data;
-                string v_name = h_array[0]->v_event_name;
-                for (map<uint32_t,struct iio_counter*>::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) {
-                    uint32_t hh_id = hunit->first;
-                    uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair<h_id,v_id>(hh_id,vv_id)];
-                    h_data.push_back(raw_data);
-                }
-                data = prepare_data(h_data, headers);
-                row = "| " + v_name;
-                row += string(abs(int(headers[0].size() - (row.size() - 1))), ' ');
-                row += std::accumulate(data.begin(), data.end(), string("|"), a_data);
-                buffer.push_back(row);
-            }
-            //Print deliminator
-            row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer);
-            buffer.push_back(row);
-            //Print pcie devices
-            for (const auto& part : stack->parts) {
-                uint8_t level = 1;
-                for (const auto& pci_device : part.child_pci_devs) {
-                    row = build_pci_header(pciDB, (uint32_t)header_width, pci_device, -1, level);
-                    buffer.push_back(row);
-                    if (pci_device.hasChildDevices()) {
-                        build_pci_tree(buffer, pciDB, (uint32_t)header_width, pci_device, -1, level + 1);
-                    } else if (pci_device.header_type == 1) {
-                            level++;
-                    }
-                }
-            }
-            //Print footer
-            row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer);
-            buffer.push_back(row);
-        }
-    }
-    return buffer;
-}
-
 std::string get_root_port_dev(const bool show_root_port, int part_id,  const pcm::iio_stack *stack)
 {
     char tmp[9] = "        ";
@@ -172,40 +104,51 @@ std::string get_root_port_dev(const bool show_root_port, int part_id,  const pcm
 
 }
 
-vector<string> build_csv(vector<struct iio_stacks_on_socket>& iios, vector<struct iio_counter>& ctrs,
-                         const bool human_readable, const bool show_root_port, const std::string& csv_delimiter,
-                         const map<string,std::pair<h_id,std::map<string,v_id>>> &nameMap)
+class PcmIioCsvBuilder : public PcmIioOutputBuilder {
+public:
+    PcmIioCsvBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {}
+
+    ~PcmIioCsvBuilder() = default;
+
+    vector<string> buildDisplayBuffer() override;
+private:
+    void insertTimeStamp(vector<string> & out, CsvOutputType type);
+};
+
+void PcmIioCsvBuilder::insertTimeStamp(vector<string> & out, CsvOutputType type)
+{
+    std::string dateTime;
+    printDateForCSV(type, m_config.display.csv_delimiter, &dateTime);
+    // remove last delimiter
+    dateTime.pop_back();
+    out.insert(out.begin(), dateTime);
+}
+
+vector<string> PcmIioCsvBuilder::buildDisplayBuffer()
 {
     vector<string> result;
     vector<string> current_row;
-    auto header = combine_stack_name_and_counter_names("Part", nameMap);
+    auto header = combine_stack_name_and_counter_names("Part", m_config.pmu_config.pcieEventNameMap);
     header.insert(header.begin(), "Name");
-    if (show_root_port)
+    if (m_config.display.show_root_port)
         header.insert(header.begin(), "Root Port");
     header.insert(header.begin(), "Socket");
-    auto insertDateTime = [&csv_delimiter](vector<string> & out, CsvOutputType type) {
-        std::string dateTime;
-        printDateForCSV(type, csv_delimiter, &dateTime);
-        // remove last delimiter
-        dateTime.pop_back();
-        out.insert(out.begin(), dateTime);
-    };
-    insertDateTime(header, CsvOutputType::Header2);
-    result.push_back(build_csv_row(header, csv_delimiter));
+    insertTimeStamp(header, CsvOutputType::Header2);
+    result.push_back(build_csv_row(header, m_config.display.csv_delimiter));
     std::map<uint32_t,map<uint32_t,struct iio_counter*>> v_sort;
     //re-organize data collection to be row wise
     size_t max_name_width = 0;
-    for (std::vector<struct iio_counter>::iterator counter = ctrs.begin(); counter != ctrs.end(); ++counter) {
+    for (auto counter = m_config.pmu_config.evt_ctx.ctrs.begin(); counter != m_config.pmu_config.evt_ctx.ctrs.end(); ++counter) {
         v_sort[counter->v_id][counter->h_id] = &(*counter);
         max_name_width = (std::max)(max_name_width, counter->v_event_name.size());
     }
 
-    for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) {
+    for (auto socket = m_config.pmu_config.iios.cbegin(); socket != m_config.pmu_config.iios.cend(); ++socket) {
         for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) {
             const std::string socket_name = "Socket" + std::to_string(socket->socket_id);
 
             std::string stack_name = stack->stack_name;
-            if (!human_readable) {
+            if (!m_config.display.human_readable) {
                 stack_name.erase(stack_name.find_last_not_of(' ') + 1);
             }
 
@@ -214,19 +157,19 @@ vector<string> build_csv(vector<struct iio_stacks_on_socket>& iios, vector<struc
             int part_id;
             std::map<uint32_t,map<uint32_t,struct iio_counter*>>::const_iterator vunit;
             for (vunit = v_sort.cbegin(), part_id = 0;
-                     vunit != v_sort.cend(); ++vunit, ++part_id) {
+                    vunit != v_sort.cend(); ++vunit, ++part_id) {
                 map<uint32_t, struct iio_counter*> h_array = vunit->second;
                 uint32_t vv_id = vunit->first;
                 vector<uint64_t> h_data;
                 string v_name = h_array[0]->v_event_name;
-                if (human_readable) {
+                if (m_config.display.human_readable) {
                     v_name += string(max_name_width - (v_name.size()), ' ');
                 }
 
                 current_row.clear();
                 current_row.push_back(socket_name);
-                if (show_root_port) {
-                    auto pci_dev = get_root_port_dev(show_root_port, part_id, &(*stack));
+                if (m_config.display.show_root_port) {
+                    auto pci_dev = get_root_port_dev(m_config.display.show_root_port, part_id, &(*stack));
                     current_row.push_back(pci_dev);
                 }
                 current_row.push_back(stack_name);
@@ -234,1102 +177,107 @@ vector<string> build_csv(vector<struct iio_stacks_on_socket>& iios, vector<struc
                 for (map<uint32_t,struct iio_counter*>::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) {
                     uint32_t hh_id = hunit->first;
                     uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair<h_id,v_id>(hh_id,vv_id)];
-                    current_row.push_back(human_readable ? unit_format(raw_data) : std::to_string(raw_data));
+                    current_row.push_back(m_config.display.human_readable ? unit_format(raw_data) : std::to_string(raw_data));
                 }
-                insertDateTime(current_row, CsvOutputType::Data);
-                result.push_back(build_csv_row(current_row, csv_delimiter));
+                insertTimeStamp(current_row, CsvOutputType::Data);
+                result.push_back(build_csv_row(current_row, m_config.display.csv_delimiter));
             }
         }
     }
     return result;
 }
 
-void PurleyPlatformMapping::getUboxBusNumbers(std::vector<uint32_t>& ubox)
-{
-    for (uint16_t bus = 0; bus < 256; bus++) {
-        for (uint8_t device = 0; device < 32; device++) {
-            for (uint8_t function = 0; function < 8; function++) {
-                struct pci pci_dev;
-                pci_dev.bdf.busno = (uint8_t)bus;
-                pci_dev.bdf.devno = device;
-                pci_dev.bdf.funcno = function;
-                if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SKX_SOCKETID_UBOX_DID)) {
-                    ubox.push_back(bus);
-                }
-            }
-        }
-    }
-}
-
-bool PurleyPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
-{
-    std::vector<uint32_t> ubox;
-    getUboxBusNumbers(ubox);
-    if (ubox.empty()) {
-        cerr << "UBOXs were not found! Program aborted" << endl;
-        return false;
-    }
-
-    for (uint32_t socket_id = 0; socket_id < socketsCount(); socket_id++) {
-        if (!PciHandleType::exists(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM)) {
-            cerr << "No access to PCICFG\n" << endl;
-            return false;
-        }
-        uint64 cpubusno = 0;
-        struct iio_stacks_on_socket iio_on_socket;
-        iio_on_socket.socket_id = socket_id;
-        PciHandleType h(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM);
-        h.read64(ROOT_BUSES_OFFSET, &cpubusno);
-
-        iio_on_socket.stacks.reserve(6);
-        for (int stack_id = 0; stack_id < 6; stack_id++) {
-            struct iio_stack stack;
-            stack.iio_unit_id = stack_id;
-            stack.busno = (uint8_t)(cpubusno >> (stack_id * SKX_BUS_NUM_STRIDE));
-            stack.stack_name = skx_iio_stack_names[stack_id];
-            for (uint8_t part_id = 0; part_id < 4; part_id++) {
-                struct iio_bifurcated_part part;
-                part.part_id = part_id;
-                struct pci *pci = &part.root_pci_dev;
-                struct bdf *bdf = &pci->bdf;
-                bdf->busno = stack.busno;
-                bdf->devno = part_id;
-                bdf->funcno = 0;
-                /* This is a workaround to catch some IIO stack does not exist */
-                if (stack_id != 0 && stack.busno == 0) {
-                    pci->exist = false;
-                }
-                else if (probe_pci(pci)) {
-                    /* FIXME: for 0:0.0, we may need to scan from secondary switch down; lgtm [cpp/fixme-comment] */
-                    for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) {
-                        for (uint8_t device = 0; device < 32; device++) {
-                            for (uint8_t function = 0; function < 8; function++) {
-                                struct pci child_pci_dev;
-                                child_pci_dev.bdf.busno = bus;
-                                child_pci_dev.bdf.devno = device;
-                                child_pci_dev.bdf.funcno = function;
-                                if (probe_pci(&child_pci_dev)) {
-                                    part.child_pci_devs.push_back(child_pci_dev);
-                                }
-                            }
-                        }
-                    }
-                }
-                stack.parts.push_back(part);
-            }
-
-            iio_on_socket.stacks.push_back(stack);
-        }
-        iios.push_back(iio_on_socket);
-    }
-
-    return true;
-}
-
-bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map<uint8_t, uint8_t>& sad_id_bus_map)
-{
-    for (uint16_t bus = 0; bus < 256; bus++) {
-        for (uint8_t device = 0; device < 32; device++) {
-            for (uint8_t function = 0; function < 8; function++) {
-                struct pci pci_dev;
-                pci_dev.bdf.busno = (uint8_t)bus;
-                pci_dev.bdf.devno = device;
-                pci_dev.bdf.funcno = function;
-                if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SNR_ICX_MESH2IIO_MMAP_DID)) {
-
-                    PciHandleType h(0, bus, device, function);
-                    std::uint32_t sad_ctrl_cfg;
-                    h.read32(SNR_ICX_SAD_CONTROL_CFG_OFFSET, &sad_ctrl_cfg);
-                    if (sad_ctrl_cfg == (std::numeric_limits<uint32_t>::max)()) {
-                        cerr << "Could not read SAD_CONTROL_CFG" << endl;
-                        return false;
-                    }
-
-                    if ((sad_ctrl_cfg & 0xf) == socket_id) {
-                        uint8_t sid = (sad_ctrl_cfg >> 4) & 0x7;
-                        sad_id_bus_map.insert(std::pair<uint8_t, uint8_t>(sid, (uint8_t)bus));
-                    }
-                }
-            }
-        }
-    }
+class PcmIioDisplayBuilder : public PcmIioOutputBuilder {
+public:
+    PcmIioDisplayBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {}
 
-    if (sad_id_bus_map.empty()) {
-        cerr << "Could not find Root Port bus numbers" << endl;
-        return false;
-    }
+    ~PcmIioDisplayBuilder() = default;
 
-    return true;
-}
+    vector<string> buildDisplayBuffer() override;
+};
 
-bool WhitleyPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+vector<string> PcmIioDisplayBuilder::buildDisplayBuffer()
 {
-    for (uint32_t socket = 0; socket < socketsCount(); socket++) {
-        struct iio_stacks_on_socket iio_on_socket;
-        iio_on_socket.socket_id = socket;
-        std::map<uint8_t, uint8_t> sad_id_bus_map;
-        if (!getSadIdRootBusMap(socket, sad_id_bus_map)) {
-            return false;
-        }
-
-        {
-            struct iio_stack stack;
-            stack.iio_unit_id = sad_to_pmu_id_mapping.at(ICX_MCP_SAD_ID);
-            stack.stack_name = iio_stack_names[stack.iio_unit_id];
-            iio_on_socket.stacks.push_back(stack);
-        }
-
-        for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) {
-            int sad_id = sad_id_bus_pair->first;
-            if (sad_to_pmu_id_mapping.find(sad_id) ==
-                sad_to_pmu_id_mapping.end()) {
-                cerr << "Unknown SAD ID: " << sad_id << endl;
-                return false;
-            }
-
-            if (sad_id == ICX_MCP_SAD_ID) {
-                continue;
-            }
-
-            struct iio_stack stack;
-            int root_bus = sad_id_bus_pair->second;
-            if (sad_id == ICX_CBDMA_DMI_SAD_ID) {
-                // There is one DMA Controller on each socket
-                stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id);
-                stack.busno = root_bus;
-                stack.stack_name = iio_stack_names[stack.iio_unit_id];
-
-                // PCH is on socket 0 only
-                if (socket == 0) {
-                    struct iio_bifurcated_part pch_part;
-                    struct pci *pci = &pch_part.root_pci_dev;
-                    struct bdf *bdf = &pci->bdf;
-                    pch_part.part_id = ICX_PCH_PART_ID;
-                    bdf->busno = root_bus;
-                    bdf->devno = 0x00;
-                    bdf->funcno = 0x00;
-                    if (probe_pci(pci)) {
-                        // Probe child devices only under PCH part.
-                        for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) {
-                            for (uint8_t device = 0; device < 32; device++) {
-                                for (uint8_t function = 0; function < 8; function++) {
-                                    struct pci child_pci_dev;
-                                    child_pci_dev.bdf.busno = bus;
-                                    child_pci_dev.bdf.devno = device;
-                                    child_pci_dev.bdf.funcno = function;
-                                    if (probe_pci(&child_pci_dev)) {
-                                        pch_part.child_pci_devs.push_back(child_pci_dev);
-                                    }
-                                }
-                            }
-                        }
-                        stack.parts.push_back(pch_part);
-                    }
-                }
-
-                struct iio_bifurcated_part part;
-                part.part_id = ICX_CBDMA_PART_ID;
-                struct pci *pci = &part.root_pci_dev;
-                struct bdf *bdf = &pci->bdf;
-                bdf->busno = root_bus;
-                bdf->devno = 0x01;
-                bdf->funcno = 0x00;
-                if (probe_pci(pci))
-                    stack.parts.push_back(part);
-
-                iio_on_socket.stacks.push_back(stack);
-                continue;
-            }
-            stack.busno = root_bus;
-            stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id);
-            stack.stack_name = iio_stack_names[stack.iio_unit_id];
-            for (int slot = 2; slot < 6; slot++) {
-                struct pci pci;
-                pci.bdf.busno = root_bus;
-                pci.bdf.devno = slot;
-                pci.bdf.funcno = 0x00;
-                if (!probe_pci(&pci)) {
-                    continue;
-                }
-                struct iio_bifurcated_part part;
-                part.part_id = slot - 2;
-                part.root_pci_dev = pci;
-
-                for (uint8_t bus = pci.secondary_bus_number; bus <= pci.subordinate_bus_number; bus++) {
-                    for (uint8_t device = 0; device < 32; device++) {
-                        for (uint8_t function = 0; function < 8; function++) {
-                            struct pci child_pci_dev;
-                            child_pci_dev.bdf.busno = bus;
-                            child_pci_dev.bdf.devno = device;
-                            child_pci_dev.bdf.funcno = function;
-                            if (probe_pci(&child_pci_dev)) {
-                                part.child_pci_devs.push_back(child_pci_dev);
-                            }
-                        }
-                    }
-                }
-                stack.parts.push_back(part);
-            }
-            iio_on_socket.stacks.push_back(stack);
-        }
-        std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
-        iios.push_back(iio_on_socket);
-    }
-    return true;
-}
-
-bool JacobsvillePlatformMapping::JacobsvilleAccelerators(const std::pair<uint8_t, uint8_t>& sad_id_bus_pair, struct iio_stack& stack)
-{
-    uint16_t expected_dev_id;
-    auto sad_id = sad_id_bus_pair.first;
-    switch (sad_id) {
-    case SNR_HQM_SAD_ID:
-        expected_dev_id = HQM_DID;
-        break;
-    case SNR_NIS_SAD_ID:
-        expected_dev_id = NIS_DID;
-        break;
-    case SNR_QAT_SAD_ID:
-        expected_dev_id = QAT_DID;
-        break;
-    default:
-        return false;
-    }
-    stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id);
-    stack.stack_name = snr_iio_stack_names[stack.iio_unit_id];
-    for (uint16_t bus = sad_id_bus_pair.second; bus < 256; bus++) {
-        for (uint8_t device = 0; device < 32; device++) {
-            for (uint8_t function = 0; function < 8; function++) {
-                struct pci pci_dev;
-                pci_dev.bdf.busno = (uint8_t)bus;
-                pci_dev.bdf.devno = device;
-                pci_dev.bdf.funcno = function;
-                if (probe_pci(&pci_dev)) {
-                    if (expected_dev_id == pci_dev.device_id) {
-                        struct iio_bifurcated_part part;
-                        part.part_id = SNR_ACCELERATOR_PART_ID;
-                        part.root_pci_dev = pci_dev;
-                        stack.busno = (uint8_t)bus;
-                        stack.parts.push_back(part);
-                        return true;
-                    }
-                }
-            }
-        }
-    }
-    return false;
-}
-
-bool JacobsvillePlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
-{
-    std::map<uint8_t, uint8_t> sad_id_bus_map;
-    if (!getSadIdRootBusMap(0, sad_id_bus_map)) {
-        return false;
-    }
-    struct iio_stacks_on_socket iio_on_socket;
-    iio_on_socket.socket_id = 0;
-    if (sad_id_bus_map.size() != snr_sad_to_pmu_id_mapping.size()) {
-        cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << snr_sad_to_pmu_id_mapping.size() << endl;
-        return false;
-    }
-
-    for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) {
-        int sad_id = sad_id_bus_pair->first;
-        struct iio_stack stack;
-        switch (sad_id) {
-        case SNR_CBDMA_DMI_SAD_ID:
-            {
-                int root_bus = sad_id_bus_pair->second;
-                stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id);
-                stack.stack_name = snr_iio_stack_names[stack.iio_unit_id];
-                stack.busno = root_bus;
-                // DMA Controller
-                struct iio_bifurcated_part part;
-                part.part_id = 0;
-                struct pci pci_dev;
-                pci_dev.bdf.busno = root_bus;
-                pci_dev.bdf.devno = 0x01;
-                pci_dev.bdf.funcno = 0x00;
-                if (probe_pci(&pci_dev)) {
-                    part.root_pci_dev = pci_dev;
-                    stack.parts.push_back(part);
-                }
-
-                part.part_id = 4;
-                pci_dev.bdf.busno = root_bus;
-                pci_dev.bdf.devno = 0x00;
-                pci_dev.bdf.funcno = 0x00;
-                if (probe_pci(&pci_dev)) {
-                    for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
-                        for (uint8_t device = 0; device < 32; device++) {
-                            for (uint8_t function = 0; function < 8; function++) {
-                                struct pci child_pci_dev;
-                                child_pci_dev.bdf.busno = bus;
-                                child_pci_dev.bdf.devno = device;
-                                child_pci_dev.bdf.funcno = function;
-                                if (probe_pci(&child_pci_dev)) {
-                                    part.child_pci_devs.push_back(child_pci_dev);
-                                }
-                            }
-                        }
-                    }
-                    part.root_pci_dev = pci_dev;
-                    stack.parts.push_back(part);
-                }
-            }
-            break;
-        case SNR_PCIE_GEN3_SAD_ID:
-            {
-                int root_bus = sad_id_bus_pair->second;
-                stack.busno = root_bus;
-                stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id);
-                stack.stack_name = snr_iio_stack_names[stack.iio_unit_id];
-                for (int slot = 4; slot < 8; slot++) {
-                    struct pci pci_dev;
-                    pci_dev.bdf.busno = root_bus;
-                    pci_dev.bdf.devno = slot;
-                    pci_dev.bdf.funcno = 0x00;
-                    if (!probe_pci(&pci_dev)) {
-                        continue;
-                    }
-                    int part_id = 4 + pci_dev.device_id - SNR_ROOT_PORT_A_DID;
-                    if ((part_id < 0) || (part_id > 4)) {
-                        cerr << "Invalid part ID " << part_id << endl;
-                        return false;
-                    }
-                    struct iio_bifurcated_part part;
-                    part.part_id = part_id;
-                    part.root_pci_dev = pci_dev;
-                    for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
-                        for (uint8_t device = 0; device < 32; device++) {
-                            for (uint8_t function = 0; function < 8; function++) {
-                                struct pci child_pci_dev;
-                                child_pci_dev.bdf.busno = bus;
-                                child_pci_dev.bdf.devno = device;
-                                child_pci_dev.bdf.funcno = function;
-                                if (probe_pci(&child_pci_dev)) {
-                                    part.child_pci_devs.push_back(child_pci_dev);
-                                }
-                            }
-                        }
-                    }
-                    stack.parts.push_back(part);
-                }
-            }
-            break;
-        case SNR_HQM_SAD_ID:
-        case SNR_NIS_SAD_ID:
-        case SNR_QAT_SAD_ID:
-            JacobsvilleAccelerators(*sad_id_bus_pair, stack);
-            break;
-        default:
-            cerr << "Unknown SAD ID: " << sad_id << endl;
-            return false;
-        }
-        iio_on_socket.stacks.push_back(stack);
-    }
-
-    std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
-
-    iios.push_back(iio_on_socket);
-
-    return true;
-}
-
-bool EagleStreamPlatformMapping::setChopValue()
-{
-    for (uint16_t b = 0; b < 256; b++) {
-        struct pci pci_dev(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION);
-        if (!(probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SPR_PCU_CR3_DID))) {
-            continue;
-        }
-
-        std::uint32_t capid4;
-        PciHandleType h(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION);
-        h.read32(SPR_CAPID4_OFFSET, &capid4);
-        if (capid4 == (std::numeric_limits<std::uint32_t>::max)()) {
-            std::cerr << "Cannot read PCU RC3 register" << std::endl;
-            return false;
-        }
-        capid4 = SPR_CAPID4_GET_PHYSICAL_CHOP(capid4);
-        if (capid4 == kXccChop || capid4 == kMccChop) {
-            m_chop = capid4;
-            m_es_type = cpuId() == PCM::SPR ? (m_chop == kXccChop ? estype::esSprXcc : estype::esSprMcc) : estype::esEmrXcc;
-        }
-        else {
-            std::cerr << "Unknown chop value " << capid4 << std::endl;
-            return false;
-        }
-        return true;
-    }
-    std::cerr << "Cannot find PCU RC3 registers on the system. Device ID is " << std::hex << SPR_PCU_CR3_DID << std::dec << std::endl;
-    return false;
-}
-
-bool EagleStreamPlatformMapping::getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses)
-{
-    bool mapped = true;
-    for (uint32_t domain = 0; mapped; domain++) {
-        mapped = false;
-        for (uint16_t b = 0; b < 256; b++) {
-            for (uint8_t d = 0; d < 32; d++) {
-                for (uint8_t f = 0; f < 8; f++) {
-                    struct pci pci_dev(domain, b, d, f);
-                    if (!probe_pci(&pci_dev)) {
-                        break;
-                    }
-                    if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) {
-                        continue;
-                    }
-
-                    std::uint32_t cpuBusValid;
-                    std::vector<std::uint32_t> cpuBusNo;
-                    int package_id;
-
-                    if (get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id) == false)
-                    {
-                        return false;
-                    }
-
-                    const auto& sad_to_pmu_id_mapping = es_sad_to_pmu_id_mapping.at(m_es_type);
-                    for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) {
-                        if (!((cpuBusValid >> cpuBusId) & 0x1))
-                        {
-                            cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl;
-                            continue;
-                        }
-                        if (sad_to_pmu_id_mapping.find(cpuBusId) == sad_to_pmu_id_mapping.end())
-                        {
-                            cerr << "Cannot map CPU bus " << cpuBusId << " to IO PMU ID" << endl;
-                            continue;
-                        }
-                        int pmuId = sad_to_pmu_id_mapping.at(cpuBusId);
-                        int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff;
-                        root_buses[package_id][pmuId] = bdf(domain, rootBus, 0, 0);
-                        cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ") to IO PMU #"
-                             << pmuId << " package " << package_id << endl;
-                        mapped = true;
-                    }
-                }
-            }
-        }
-    }
-    return !root_buses.empty();
-}
-
-bool EagleStreamPlatformMapping::eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    struct iio_stack stack;
-    stack.iio_unit_id = unit;
-    stack.stack_name = es_stack_names.at(m_es_type)[unit];
-    stack.busno = address.busno;
-    stack.domain = address.domainno;
-    struct iio_bifurcated_part pch_part;
-    struct pci *pci = &pch_part.root_pci_dev;
-    auto dmi_part_id = SPR_DMI_PART_ID;
-    pch_part.part_id = dmi_part_id;
-    pci->bdf = address;
-    if (!probe_pci(pci)) {
-        cerr << "Failed to probe DMI Stack: address: " << std::setw(4) << std::setfill('0') << std::hex << address.domainno <<
-                                                          std::setw(2) << std::setfill('0') << ":" << address.busno << ":" << address.devno <<
-                                                          "." << address.funcno << std::dec << endl;
-        return false;
-    }
-
-    /* Scan devices behind PCH port only */
-    if (!iio_on_socket.socket_id)
-        probeDeviceRange(pch_part.child_pci_devs, pci->bdf.domainno, pci->secondary_bus_number, pci->subordinate_bus_number);
-
-    pci->parts_no.push_back(dmi_part_id);
-
-    stack.parts.push_back(pch_part);
-    iio_on_socket.stacks.push_back(stack);
-    return true;
-}
-
-bool EagleStreamPlatformMapping::eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    /*
-     * Stacks that manage PCIe 4.0 (device 2,4,6,8) and 5.0 (device 1,3,5,7) Root Ports.
-     */
-    struct iio_stack stack;
-    stack.domain = address.domainno;
-    stack.busno = address.busno;
-    stack.iio_unit_id = unit;
-    stack.stack_name = es_stack_names.at(m_es_type)[unit];
-    for (int slot = 1; slot < 9; ++slot)
-    {
-        // Check if port is enabled
-        struct pci root_pci_dev;
-        root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0);
-        if (probe_pci(&root_pci_dev))
-        {
-            struct iio_bifurcated_part part;
-            // Bifurcated Root Ports to channel mapping on SPR
-            part.part_id = slot - 1;
-            part.root_pci_dev = root_pci_dev;
-            for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) {
-                for (uint8_t d = 0; d < 32; ++d) {
-                    for (uint8_t f = 0; f < 8; ++f) {
-                        struct pci child_pci_dev(address.domainno, b, d, f);
-                        if (probe_pci(&child_pci_dev)) {
-                            child_pci_dev.parts_no.push_back(part.part_id);
-                            part.child_pci_devs.push_back(child_pci_dev);
-                        }
-                    }
-                }
-            }
-            stack.parts.push_back(part);
-        }
-    }
-    iio_on_socket.stacks.push_back(stack);
-    return true;
-}
-
-bool EagleStreamPlatformMapping::eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    struct iio_stack stack;
-    stack.iio_unit_id = unit;
-    stack.domain = address.domainno;
-    stack.busno = address.busno;
-
-    // Channel mappings are checked on B0 stepping
-    auto rb = address.busno;
-    const std::vector<int> acceleratorBuses{ rb, rb + 1, rb + 2, rb + 3 };
-    stack.stack_name = es_stack_names.at(m_es_type)[unit];
-    for (auto& b : acceleratorBuses) {
-        for (auto d = 0; d < 32; ++d) {
-            for (auto f = 0; f < 8; ++f) {
-                struct iio_bifurcated_part part;
-                struct pci pci_dev(address.domainno, b, d, f);
-
-                if (probe_pci(&pci_dev)) {
-                    if (pci_dev.isIntelDevice()) {
-                        switch (pci_dev.device_id) {
-                        case DSA_DID:
-                            pci_dev.parts_no.push_back(0);
-                            pci_dev.parts_no.push_back(1);
-                            pci_dev.parts_no.push_back(2);
-                            break;
-                        case IAX_DID:
-                            pci_dev.parts_no.push_back(0);
-                            pci_dev.parts_no.push_back(1);
-                            pci_dev.parts_no.push_back(2);
-                            break;
-                        case HQMV2_DID:
-                            pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_HQM_PART_ID : SPR_MCC_HQM_PART_ID);
-                            break;
-                        case QATV2_DID:
-                            pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_QAT_PART_ID : SPR_MCC_QAT_PART_ID);
-                            break;
-                        default:
-                            continue;
-                        }
-                        part.child_pci_devs.push_back(pci_dev);
-                    }
-                    stack.parts.push_back(part);
-                }
-            }
-        }
-    }
-
-    iio_on_socket.stacks.push_back(stack);
-    return true;
-}
-
-bool EagleStreamPlatformMapping::isDmiStack(int unit)
-{
-    const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type);
-
-    return stacks_enumeration[esDMI] == unit;
-}
-
-bool EagleStreamPlatformMapping::isPcieStack(int unit)
-{
-    const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type);
-
-    return stacks_enumeration[esPCIe0] == unit || stacks_enumeration[esPCIe1] == unit ||
-           stacks_enumeration[esPCIe2] == unit || stacks_enumeration[esPCIe3] == unit ||
-           stacks_enumeration[esPCIe4] == unit;
-}
-
-bool EagleStreamPlatformMapping::isDinoStack(int unit)
-{
-    const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type);
-
-    return stacks_enumeration[esDINO0] == unit || stacks_enumeration[esDINO1] == unit ||
-           stacks_enumeration[esDINO2] == unit || stacks_enumeration[esDINO3] == unit;
-}
-
-bool EagleStreamPlatformMapping::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    if (isDmiStack(unit)) {
-        return eagleStreamDmiStackProbe(unit, address, iio_on_socket);
-    }
-    else if (isPcieStack(unit)) {
-        return eagleStreamPciStackProbe(unit, address, iio_on_socket);
-    }
-    else if (isDinoStack(unit)) {
-        return eagleStreamAcceleratorStackProbe(unit, address, iio_on_socket);
-    }
-
-    return false;
-}
-
-bool EagleStreamPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
-{
-    if (!setChopValue()) return false;
-
-    std::map<int, std::map<int, struct bdf>> root_buses;
-    if (!getRootBuses(root_buses))
-    {
-        return false;
-    }
-
-    for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) {
-        auto rbs_on_socket = iter->second;
-        struct iio_stacks_on_socket iio_on_socket;
-        iio_on_socket.socket_id = iter->first;
-        for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) {
-            if (!stackProbe(rb->first, rb->second, iio_on_socket)) {
-                return false;
-            }
-        }
-        std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
-        iios.push_back(iio_on_socket);
-    }
-
-    return true;
-}
-
-bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id)
-{
-    struct iio_stack stack;
-    stack.busno = root_bus;
-    stack.iio_unit_id = stack_pmon_id;
-    stack.stack_name = grr_iio_stack_names[stack_pmon_id];
-
-    struct iio_bifurcated_part pch_part;
-    pch_part.part_id = 7;
-    struct pci* pci_dev = &pch_part.root_pci_dev;
-    pci_dev->bdf.busno = root_bus;
-
-    if (probe_pci(pci_dev)) {
-        probeDeviceRange(pch_part.child_pci_devs, pci_dev->bdf.domainno, pci_dev->secondary_bus_number, pci_dev->subordinate_bus_number);
-        stack.parts.push_back(pch_part);
-        iio_on_socket.stacks.push_back(stack);
-        return true;
-    }
-
-    return false;
-}
-
-bool LoganvillePlatform::loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id)
-{
-    struct iio_stack stack;
-    stack.busno = root_bus;
-    stack.iio_unit_id = stack_pmon_id;
-    stack.stack_name = grr_iio_stack_names[stack_pmon_id];
-
-    struct iio_bifurcated_part dlb_part;
-    dlb_part.part_id = GRR_DLB_PART_ID;
-
-    for (uint8_t bus = root_bus; bus < 255; bus++) {
-        struct pci pci_dev(bus, 0x00, 0x00);
-        if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(HQMV25_DID)) {
-            dlb_part.root_pci_dev = pci_dev;
-            // Check Virtual RPs for DLB
-            for (uint8_t device = 0; device < 2; device++) {
-                for (uint8_t function = 0; function < 8; function++) {
-                    struct pci child_pci_dev(bus, device, function);
-                    if (probe_pci(&child_pci_dev)) {
-                        dlb_part.child_pci_devs.push_back(child_pci_dev);
-                    }
-                }
-            }
-            stack.parts.push_back(dlb_part);
-            iio_on_socket.stacks.push_back(stack);
-            return true;
-        }
-    }
-
-    return false;
-}
-
-bool LoganvillePlatform::loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id)
-{
-    struct iio_stack stack;
-    stack.busno = root_bus;
-    stack.iio_unit_id = stack_pmon_id;
-    stack.stack_name = grr_iio_stack_names[stack_pmon_id];
-
-    // Probe NIS
-    {
-        struct iio_bifurcated_part nis_part;
-        nis_part.part_id = GRR_NIS_PART_ID;
-        struct pci pci_dev(root_bus, 0x04, 0x00);
-        if (probe_pci(&pci_dev)) {
-            nis_part.root_pci_dev = pci_dev;
-            for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
-                for (uint8_t device = 0; device < 2; device++) {
-                    for (uint8_t function = 0; function < 8; function++) {
-                            struct pci child_pci_dev(bus, device, function);
-                            if (probe_pci(&child_pci_dev)) {
-                                nis_part.child_pci_devs.push_back(child_pci_dev);
-                            }
-                    }
-                }
-            }
-            stack.parts.push_back(nis_part);
-        }
-    }
-
-    // Probe QAT
-    {
-        struct iio_bifurcated_part qat_part;
-        qat_part.part_id = GRR_QAT_PART_ID;
-        struct pci pci_dev(root_bus, 0x05, 0x00);
-        if (probe_pci(&pci_dev)) {
-            qat_part.root_pci_dev = pci_dev;
-            for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
-                for (uint8_t device = 0; device < 17; device++) {
-                    for (uint8_t function = 0; function < 8; function++) {
-                            struct pci child_pci_dev(bus, device, function);
-                            if (probe_pci(&child_pci_dev)) {
-                                qat_part.child_pci_devs.push_back(child_pci_dev);
-                            }
-                    }
-                }
-            }
-            stack.parts.push_back(qat_part);
-        }
-    }
-
-    iio_on_socket.stacks.push_back(stack);
-    return true;
-}
-
-bool LoganvillePlatform::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
-{
-    std::map<uint8_t, uint8_t> sad_id_bus_map;
-    if (!getSadIdRootBusMap(0, sad_id_bus_map)) {
-        return false;
-    }
-
-    if (sad_id_bus_map.size() != grr_sad_to_pmu_id_mapping.size()) {
-        cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << grr_sad_to_pmu_id_mapping.size() << endl;
-        return false;
-    }
-
-    struct iio_stacks_on_socket iio_on_socket;
-    iio_on_socket.socket_id = 0;
-
-    for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) {
-        if (grr_sad_to_pmu_id_mapping.find(sad_id_bus_pair->first) == grr_sad_to_pmu_id_mapping.end()) {
-            cerr << "Cannot map SAD ID to PMON ID. Unknown ID: " << sad_id_bus_pair->first << endl;
-            return false;
-        }
-        int stack_pmon_id = grr_sad_to_pmu_id_mapping.at(sad_id_bus_pair->first);
-        int root_bus = sad_id_bus_pair->second;
-        switch (stack_pmon_id) {
-        case GRR_PCH_DSA_GEN4_PMON_ID:
-            if (!loganvillePchDsaPciStackProbe(iio_on_socket, root_bus, stack_pmon_id)) {
-                return false;
-            }
-            break;
-        case GRR_DLB_PMON_ID:
-            if (!loganvilleDlbStackProbe(iio_on_socket, root_bus, stack_pmon_id)) {
-                return false;
-            }
-            break;
-        case GRR_NIS_QAT_PMON_ID:
-            if (!loganvilleNacStackProbe(iio_on_socket, root_bus, stack_pmon_id)) {
-                return false;
-            }
-            break;
-        default:
-            return false;
-        }
-    }
-
-    std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
-
-    iios.push_back(iio_on_socket);
-
-    return true;
-}
-
-bool Xeon6thNextGenPlatform::getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses)
-{
-    bool mapped = true;
-    for (uint32_t domain = 0; mapped; domain++) {
-        mapped = false;
-        for (uint16_t b = 0; b < 256; b++) {
-            for (uint8_t d = 0; d < 32; d++) {
-                for (uint8_t f = 0; f < 8; f++) {
-                    struct pci pci_dev(domain, b, d, f);
-                    if (!probe_pci(&pci_dev)) {
-                        break;
-                    }
-                    if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) {
-                        continue;
-                    }
-
-                    std::uint32_t cpuBusValid;
-                    std::vector<std::uint32_t> cpuBusNo;
-                    int package_id;
-
-                    if (!get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id)) {
-                        return false;
-                    }
-
-                    for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) {
-                        if (!((cpuBusValid >> cpuBusId) & 0x1)) {
-                            cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl;
-                            continue;
-                        }
-                        int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff;
-                        root_buses[package_id][cpuBusId] = bdf(domain, rootBus, 0, 0);
-                        cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ")"
-                             << " package " << package_id << endl;
-                        mapped = true;
-                    }
-                }
-            }
-        }
-    }
-    return !root_buses.empty();
-}
-
-bool Xeon6thNextGenPlatform::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
-{
-    std::map<int, std::map<int, struct bdf>> root_buses;
-    if (!getRootBuses(root_buses))
-    {
-        return false;
-    }
-
-    for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) {
-        auto rbs_on_socket = iter->second;
-        struct iio_stacks_on_socket iio_on_socket;
-        iio_on_socket.socket_id = iter->first;
-        for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) {
-            if (!stackProbe(rb->first, rb->second, iio_on_socket)) {
-                return false;
+    vector<string> buffer;
+    vector<string> headers;
+    vector<struct data> data;
+    uint64_t header_width;
+    string row;
+    for (auto socket = m_config.pmu_config.iios.cbegin(); socket != m_config.pmu_config.iios.cend(); ++socket) {
+        buffer.push_back("Socket" + std::to_string(socket->socket_id));
+        for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) {
+            auto stack_id = stack->iio_unit_id;
+            headers = combine_stack_name_and_counter_names(stack->stack_name, m_config.pmu_config.pcieEventNameMap);
+            //Print first row
+            row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer);
+            header_width = row.size();
+            buffer.push_back(row);
+            //Print a_title
+            row = std::accumulate(headers.begin(), headers.end(), string("|"), a_title);
+            buffer.push_back(row);
+            //Print deliminator
+            row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer);
+            buffer.push_back(row);
+            //Print data
+            std::map<uint32_t,map<uint32_t,struct iio_counter*>> v_sort;
+            //re-organize data collection to be row wise
+            for (std::vector<struct iio_counter>::iterator counter = m_config.pmu_config.evt_ctx.ctrs.begin(); counter != m_config.pmu_config.evt_ctx.ctrs.end(); ++counter) {
+                v_sort[counter->v_id][counter->h_id] = &(*counter);
             }
-        }
-        std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
-        iios.push_back(iio_on_socket);
-    }
-
-    return true;
-}
-
-bool BirchStreamPlatform::birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    /*
-     * All stacks manage PCIe 5.0 Root Ports. Bifurcated Root Ports A-H appear as devices 2-9.
-     */
-    struct iio_stack stack;
-    stack.domain = address.domainno;
-    stack.busno = address.busno;
-    stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit);
-    stack.stack_name = srf_iio_stack_names[stack.iio_unit_id];
-    for (int slot = 2; slot < 9; ++slot)
-    {
-        struct pci root_pci_dev;
-        root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0);
-        if (probe_pci(&root_pci_dev))
-        {
-            struct iio_bifurcated_part part;
-            part.part_id = slot - 2;
-            part.root_pci_dev = root_pci_dev;
-            for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) {
-                for (uint8_t d = 0; d < 32; ++d) {
-                    for (uint8_t f = 0; f < 8; ++f) {
-                        struct pci child_pci_dev(address.domainno, b, d, f);
-                        if (probe_pci(&child_pci_dev)) {
-                            child_pci_dev.parts_no.push_back(part.part_id);
-                            part.child_pci_devs.push_back(child_pci_dev);
-                        }
-                    }
+            for (std::map<uint32_t,map<uint32_t,struct iio_counter*>>::const_iterator vunit = v_sort.cbegin(); vunit != v_sort.cend(); ++vunit) {
+                map<uint32_t, struct iio_counter*> h_array = vunit->second;
+                uint32_t vv_id = vunit->first;
+                vector<uint64_t> h_data;
+                string v_name = h_array[0]->v_event_name;
+                for (map<uint32_t,struct iio_counter*>::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) {
+                    uint32_t hh_id = hunit->first;
+                    uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair<h_id,v_id>(hh_id,vv_id)];
+                    h_data.push_back(raw_data);
                 }
+                data = prepare_data(h_data, headers);
+                row = "| " + v_name;
+                row += string(abs(int(headers[0].size() - (row.size() - 1))), ' ');
+                row += std::accumulate(data.begin(), data.end(), string("|"), a_data);
+                buffer.push_back(row);
             }
-            stack.parts.push_back(part);
-        }
-    }
-    iio_on_socket.stacks.push_back(stack);
-    return true;
-}
-
-bool BirchStreamPlatform::birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    struct iio_stack stack;
-    stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit);
-    stack.domain = address.domainno;
-    stack.busno = address.busno;
-    stack.stack_name = srf_iio_stack_names[stack.iio_unit_id];
-
-    /*
-     * Instance of DSA(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 1, function 0
-     * Instance of IAX(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 2, function 0
-     * Instance of QAT(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (9, 13, 21, 17), device 0, function 0
-     * Instance of HQM(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (10, 14, 22, 18), device 0, function 0
-     */
-    auto process_pci_dev = [](int domainno, int busno, int devno, int part_number, iio_bifurcated_part& part)
-    {
-        struct pci pci_dev(domainno, busno, devno, 0);
-        if (probe_pci(&pci_dev) && pci_dev.isIntelDevice()) {
-            part.part_id = part_number;
-            pci_dev.parts_no.push_back(part_number);
-            part.child_pci_devs.push_back(pci_dev);
-            return true;
-        }
-        return false;
-    };
-
-    auto add_pci_part = [&](int domainno, int busno, int devno, int part_number) {
-        struct iio_bifurcated_part part;
-        if (process_pci_dev(domainno, busno, devno, part_number, part)) {
-            stack.parts.push_back(part);
-        }
-    };
-
-    add_pci_part(address.domainno, address.busno, 1, SRF_DSA_IAX_PART_NUMBER);
-    add_pci_part(address.domainno, address.busno, 2, SRF_DSA_IAX_PART_NUMBER);
-
-    add_pci_part(address.domainno, address.busno + 1, 0, SRF_QAT_PART_NUMBER);
-
-    /* Bus number for HQM is higher on 3 than DSA bus number */
-    add_pci_part(address.domainno, address.busno + 3, 0, SRF_HQM_PART_NUMBER);
-
-    if (!stack.parts.empty()) {
-        iio_on_socket.stacks.push_back(stack);
-    }
-
-    return true;
-}
-
-bool BirchStreamPlatform::isPcieStack(int unit)
-{
-    return srf_pcie_stacks.find(unit) != srf_pcie_stacks.end();
-}
-
-/*
- * HC is the name of DINO stacks as we had on SPR
- */
-bool BirchStreamPlatform::isRootHcStack(int unit)
-{
-    return SRF_HC0_SAD_BUS_ID == unit || SRF_HC1_SAD_BUS_ID == unit ||
-           SRF_HC2_SAD_BUS_ID == unit || SRF_HC3_SAD_BUS_ID == unit;
-}
-
-bool BirchStreamPlatform::isPartHcStack(int unit)
-{
-    return isRootHcStack(unit - 1) || isRootHcStack(unit - 2);
-}
-
-bool BirchStreamPlatform::isUboxStack(int unit)
-{
-    return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit;
-}
-
-bool BirchStreamPlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    if (isPcieStack(unit)) {
-        return birchStreamPciStackProbe(unit, address, iio_on_socket);
-    }
-    else if (isRootHcStack(unit)) {
-        return birchStreamAcceleratorStackProbe(unit, address, iio_on_socket);
-    }
-    else if (isPartHcStack(unit)) {
-        cout << "Found a part of HC stack. Stack ID - " << unit << " domain " << address.domainno
-             << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << ". Don't probe it again." << endl;
-        return true;
-    }
-    else if (isUboxStack(unit)) {
-        cout << "Found UBOX stack. Stack ID - " << unit << " domain " << address.domainno
-             << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl;
-        return true;
-    }
-
-    cout << "Unknown stack ID " << unit << " domain " << address.domainno << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl;
-
-    return false;
-}
-
-const std::string generate_stack_str(const int unit)
-{
-    static const std::string stack_str = "Stack ";
-    std::stringstream ss;
-    ss << stack_str << std::setw(2) << unit;
-    return ss.str();
-}
-
-bool KasseyvillePlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
-{
-    // Skip UBOX buses
-    if (isUboxStack(unit)) return true;
-
-    // To suppress compilation warning
-    (void)address;
-
-    struct iio_stack stack;
-    stack.iio_unit_id = unit;
-    stack.stack_name = generate_stack_str(unit);
-    iio_on_socket.stacks.push_back(stack);
-    return true;
-}
-
-void IPlatformMapping::probeDeviceRange(std::vector<struct pci> &pci_devs, int domain, int secondary, int subordinate)
-{
-    for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) {
-        for (uint8_t device = 0; device < 32; device++) {
-            for (uint8_t function = 0; function < 8; function++) {
-                struct pci child_dev;
-                child_dev.bdf.domainno = domain;
-                child_dev.bdf.busno = bus;
-                child_dev.bdf.devno = device;
-                child_dev.bdf.funcno = function;
-                if (probe_pci(&child_dev)) {
-                    if (secondary < child_dev.secondary_bus_number && subordinate < child_dev.subordinate_bus_number) {
-                        probeDeviceRange(child_dev.child_pci_devs, domain, child_dev.secondary_bus_number, child_dev.subordinate_bus_number);
+            //Print deliminator
+            row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer);
+            buffer.push_back(row);
+            //Print pcie devices
+            for (const auto& part : stack->parts) {
+                uint8_t level = 1;
+                for (const auto& pci_device : part.child_pci_devs) {
+                    row = build_pci_header(m_config.pciDB, (uint32_t)header_width, pci_device, -1, level);
+                    buffer.push_back(row);
+                    if (pci_device.hasChildDevices()) {
+                        build_pci_tree(buffer, m_config.pciDB, (uint32_t)header_width, pci_device, -1, level + 1);
+                    } else if (pci_device.header_type == 1) {
+                            level++;
                     }
-                    pci_devs.push_back(child_dev);
                 }
             }
+            //Print footer
+            row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer);
+            buffer.push_back(row);
         }
     }
+    return buffer;
 }
 
-std::unique_ptr<IPlatformMapping> IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count)
+std::unique_ptr<PcmIioOutputBuilder> getDisplayBuilder(struct pcm_iio_config& config)
 {
-    switch (cpu_family_model) {
-    case PCM::SKX:
-        return std::unique_ptr<IPlatformMapping>{new PurleyPlatformMapping(cpu_family_model, sockets_count)};
-    case PCM::ICX:
-        return std::unique_ptr<IPlatformMapping>{new WhitleyPlatformMapping(cpu_family_model, sockets_count)};
-    case PCM::SNOWRIDGE:
-        return std::unique_ptr<IPlatformMapping>{new JacobsvillePlatformMapping(cpu_family_model, sockets_count)};
-    case PCM::SPR:
-    case PCM::EMR:
-        return std::unique_ptr<IPlatformMapping>{new EagleStreamPlatformMapping(cpu_family_model, sockets_count)};
-    case PCM::GRR:
-        return std::unique_ptr<IPlatformMapping>{new LoganvillePlatform(cpu_family_model, sockets_count)};
-    case PCM::SRF:
-    case PCM::GNR:
-        return std::unique_ptr<IPlatformMapping>{new BirchStreamPlatform(cpu_family_model, sockets_count)};
-    case PCM::GNR_D:
-        std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for Graniterapids-D is provided" << std::endl;
-        return std::unique_ptr<IPlatformMapping>{new KasseyvillePlatform(cpu_family_model, sockets_count)};
-    default:
-        return nullptr;
+    std::unique_ptr<PcmIioOutputBuilder> displayBuilder;
+    if (config.display.csv) {
+        displayBuilder = std::make_unique<PcmIioCsvBuilder>(config);
+    } else {
+        displayBuilder = std::make_unique<PcmIioDisplayBuilder>(config);
     }
+    return displayBuilder;
 }
 
-ccr* get_ccr(PCM* m, uint64_t& ccr)
+ccr* get_ccr(uint32 cpu_family_model, uint64_t& ccr)
 {
-    switch (m->getCPUFamilyModel())
+    switch (cpu_family_model)
     {
         case PCM::SKX:
             return new pcm::ccr(ccr, ccr::ccr_type::skx);
@@ -1343,7 +291,7 @@ ccr* get_ccr(PCM* m, uint64_t& ccr)
         case PCM::GNR_D:
             return new pcm::ccr(ccr, ccr::ccr_type::icx);
         default:
-            cerr << m->getCPUFamilyModelString() << " is not supported! Program aborted" << endl;
+            std::cerr << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is not supported! Program aborted" << std::endl;
             exit(EXIT_FAILURE);
     }
 }
@@ -1351,7 +299,6 @@ ccr* get_ccr(PCM* m, uint64_t& ccr)
 int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map<std::string, uint32_t> &ofm, std::string key, uint64 numValue)
 {
     iio_evt_parse_context *context = (iio_evt_parse_context *)cb_ctx;
-    PCM *m = context->m;
 
     if (cb_type == EVT_LINE_START) //this event will be called per line(start)
     {
@@ -1359,7 +306,7 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr,
     }
     else if (cb_type == EVT_LINE_FIELD) //this event will be called per field of line
     {
-        std::unique_ptr<ccr> pccr(get_ccr(m, context->ctr.ccr));
+        std::unique_ptr<ccr> pccr(get_ccr(context->cpu_family_model, context->ctr.ccr));
         switch (ofm[key])
         {
             case PCM::OPCODE:
@@ -1408,74 +355,120 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr,
         context->ctr.v_event_name = base_ctr.v_event_name;
         context->ctr.idx = base_ctr.idx;
         context->ctr.multiplier = base_ctr.multiplier;
-        context->ctr.divider = base_ctr.divider;
         context->ctr.h_id = base_ctr.h_id;
         context->ctr.v_id = base_ctr.v_id;
+        context->ctr.type = base_ctr.type;
         DBG(4, "line parse OK, ctrcfg=0x", std::hex, context->ctr.ccr, ", h_event_name=",  base_ctr.h_event_name, ", v_event_name=", base_ctr.v_event_name);
         DBG(4, ", h_id=0x", std::hex, base_ctr.h_id, ", v_id=0x", std::hex, base_ctr.v_id);
-        DBG(4, ", idx=0x", std::hex, base_ctr.idx, ", multiplier=0x", std::hex, base_ctr.multiplier, ", divider=0x", std::hex, base_ctr.divider, std::dec, "\n");
+        DBG(4, ", idx=0x", std::hex, base_ctr.idx, ", multiplier=0x", std::hex, base_ctr.multiplier, std::dec, ", counter type = ", static_cast<int>(base_ctr.type), "\n");
         context->ctrs.push_back(context->ctr);
     }
 
     return 0;
 }
 
-result_content get_IIO_Samples(PCM *m, const std::vector<struct iio_stacks_on_socket>& iios, const struct iio_counter & ctr, uint32_t delay_ms)
-{
-    IIOCounterState *before, *after;
-    uint64 rawEvents[4] = {0};
-    std::unique_ptr<ccr> pccr(get_ccr(m, const_cast<struct iio_counter&>(ctr).ccr));
-    rawEvents[ctr.idx] = pccr->get_ccr_value();
-    const int stacks_count = (int)m->getMaxNumOfIIOStacks();
-    before = new IIOCounterState[iios.size() * stacks_count];
-    after = new IIOCounterState[iios.size() * stacks_count];
+class CounterHandlerStrategy {
+public:
+    CounterHandlerStrategy(PCM* pcm) : m_pcm(pcm) {}
+    virtual ~CounterHandlerStrategy() = default;
 
-    m->programIIOCounters(rawEvents);
-    for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) {
-        for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) {
-            auto iio_unit_id = stack->iio_unit_id;
-            uint32_t idx = (uint32_t)stacks_count * socket->socket_id + iio_unit_id;
-            before[idx] = m->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx);
-        }
+    virtual void programCounters(uint64 rawEvents[4]) = 0;
+
+    virtual SimpleCounterState getCounterState(uint32_t socket_id, uint32_t unit_id, uint32_t counter_idx) = 0;
+
+protected:
+    PCM* m_pcm;
+};
+
+class IIOCounterStrategy : public CounterHandlerStrategy {
+public:
+    IIOCounterStrategy(PCM* pcm) : CounterHandlerStrategy(pcm) {}
+
+    void programCounters(uint64 rawEvents[4]) override
+    {
+        m_pcm->programIIOCounters(rawEvents);
     }
-    MySleepMs(delay_ms);
-    for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) {
-        for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) {
-            auto iio_unit_id = stack->iio_unit_id;
-            uint32_t idx = (uint32_t)stacks_count * socket->socket_id + iio_unit_id;
-            after[idx] = m->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx);
-            uint64_t raw_result = getNumberOfEvents(before[idx], after[idx]);
-            uint64_t trans_result = uint64_t (raw_result * ctr.multiplier / (double) ctr.divider * (1000 / (double) delay_ms));
-            results[socket->socket_id][iio_unit_id][std::pair<h_id,v_id>(ctr.h_id,ctr.v_id)] = trans_result;
-        }
+
+    SimpleCounterState getCounterState(uint32_t socket_id, uint32_t unit_id, uint32_t counter_idx) override
+    {
+        return m_pcm->getIIOCounterState(socket_id, unit_id, counter_idx);
+    }
+};
+
+std::shared_ptr<CounterHandlerStrategy> createCounterStrategy(PCM* pcm, CounterType type)
+{
+    switch (type)
+    {
+    case CounterType::iio:
+        return std::make_shared<IIOCounterStrategy>(pcm);
+    default:
+        std::cerr << "Unsupported counter type: " << static_cast<int>(type) << std::endl;
+        exit(EXIT_FAILURE);
     }
-    deleteAndNullifyArray(before);
-    deleteAndNullifyArray(after);
-    return results;
 }
 
-void collect_data(PCM *m, const double delay, vector<struct iio_stacks_on_socket>& iios, vector<struct iio_counter>& ctrs)
+void PcmIioDataCollector::initializeCounterHandlers()
 {
-    const uint32_t delay_ms = uint32_t(delay * 1000 / ctrs.size());
-    for (auto counter = ctrs.begin(); counter != ctrs.end(); ++counter) {
-        counter->data.clear();
-        result_content sample = get_IIO_Samples(m, iios, *counter, delay_ms);
-        counter->data.push_back(sample);
+    for (const auto& counter : m_config.evt_ctx.ctrs) {
+        if (!m_strategies[static_cast<size_t>(counter.type)]) {
+            m_strategies[static_cast<size_t>(counter.type)] = createCounterStrategy(m_pcm, counter.type);
+        }
     }
 }
 
-void initializeIIOStructure( std::vector<struct iio_stacks_on_socket>& iios )
+PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) :
+    m_config(config), m_strategies(static_cast<size_t>(CounterType::COUNTER_TYPES_COUNT), nullptr)
 {
-    PCM * m = PCM::getInstance();
-    auto mapping = IPlatformMapping::getPlatformMapping(m->getCPUFamilyModel(), m->getNumSockets());
-    if (!mapping) {
-        cerr << "Failed to discover pci tree: unknown platform" << endl;
-        exit(EXIT_FAILURE);
+    m_pcm = PCM::getInstance();
+    m_delay_ms = static_cast<uint32_t>(m_config.delay * 1000 / m_config.evt_ctx.ctrs.size());
+    m_stacks_count = m_pcm->getMaxNumOfIOStacks();
+    m_time_scaling_factor = 1000.0 / m_delay_ms;
+
+    m_before = std::make_unique<SimpleCounterState[]>(m_config.iios.size() * m_stacks_count);
+    m_after = std::make_unique<SimpleCounterState[]>(m_config.iios.size() * m_stacks_count);
+
+    m_results.resize(m_pcm->getNumSockets(), stack_content(m_stacks_count, ctr_data()));
+
+    initializeCounterHandlers();
+}
+
+void PcmIioDataCollector::collectData()
+{
+    for (auto& counter : m_config.evt_ctx.ctrs) {
+        counter.data.clear();
+        result_content sample = getSample(counter);
+        counter.data.push_back(sample);
     }
+}
 
-    if (!mapping->pciTreeDiscover(iios)) {
-        exit(EXIT_FAILURE);
+result_content PcmIioDataCollector::getSample(struct iio_counter & ctr)
+{
+    uint64 rawEvents[COUNTERS_NUMBER] = {0};
+    std::unique_ptr<ccr> pccr(get_ccr(m_pcm->getCPUFamilyModel(), ctr.ccr));
+    rawEvents[ctr.idx] = pccr->get_ccr_value();
+
+    auto strategy = m_strategies[static_cast<size_t>(ctr.type)];
+
+    strategy->programCounters(rawEvents);
+    for (const auto& socket : m_config.iios) {
+        for (const auto& stack : socket.stacks) {
+            auto iio_unit_id = stack.iio_unit_id;
+            uint32_t idx = getStackIndex(socket.socket_id, iio_unit_id);
+            m_before[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx);
+        }
     }
+    MySleepMs(m_delay_ms);
+    for (const auto& socket : m_config.iios) {
+        for (const auto& stack : socket.stacks) {
+            auto iio_unit_id = stack.iio_unit_id;
+            uint32_t idx = getStackIndex(socket.socket_id, iio_unit_id);
+            m_after[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx);
+            uint64_t raw_result = getNumberOfEvents(m_before[idx], m_after[idx]);
+            uint64_t trans_result = static_cast<uint64_t>(raw_result * ctr.multiplier * m_time_scaling_factor);
+            m_results[socket.socket_id][iio_unit_id][std::pair<h_id,v_id>(ctr.h_id, ctr.v_id)] = trans_result;
+        }
+    }
+    return m_results;
 }
 
 void fillOpcodeFieldMapForPCIeEvents(map<string,uint32_t>& opcodeFieldMap)
@@ -1492,41 +485,40 @@ void fillOpcodeFieldMapForPCIeEvents(map<string,uint32_t>& opcodeFieldMap)
     opcodeFieldMap["thresh"] = PCM::THRESH;
     opcodeFieldMap["ch_mask"] = PCM::CH_MASK;
     opcodeFieldMap["fc_mask"] = PCM::FC_MASK;
-    opcodeFieldMap["hname"] =PCM::H_EVENT_NAME;
-    opcodeFieldMap["vname"] =PCM::V_EVENT_NAME;
+    opcodeFieldMap["hname"] = PCM::H_EVENT_NAME;
+    opcodeFieldMap["vname"] = PCM::V_EVENT_NAME;
     opcodeFieldMap["multiplier"] = PCM::MULTIPLIER;
-    opcodeFieldMap["divider"] = PCM::DIVIDER;
     opcodeFieldMap["ctr"] = PCM::COUNTER_INDEX;
+    opcodeFieldMap["unit"] = PCM::UNIT_TYPE;
 }
 
-void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap)
+bool setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap)
 {
     PCM * m = PCM::getInstance();
 
-    string ev_file_name;
-        ev_file_name = "opCode-" + std::to_string(m->getCPUFamily()) + "-" + std::to_string(m->getInternalCPUModel()) + ".txt";
+    string ev_file_name = "opCode-" + std::to_string(m->getCPUFamily()) + "-" + std::to_string(m->getInternalCPUModel()) + ".txt";
 
     map<string,uint32_t> opcodeFieldMap;
     fillOpcodeFieldMapForPCIeEvents( opcodeFieldMap );
 
-    evt_ctx.m = m;
+    evt_ctx.cpu_family_model = m->getCPUFamilyModel();
     evt_ctx.ctrs.clear();//fill the ctrs by evt_handler call back func.
 
     try
     {
         load_events(ev_file_name, opcodeFieldMap, iio_evt_parse_handler, (void *)&evt_ctx, nameMap);
     }
-    catch (std::exception & e)
+    catch (const std::exception & e)
     {
-        std::cerr << "Error info:" << e.what() << "\n";
-        std::cerr << "The event configuration file (" << ev_file_name << ") cannot be loaded. Please verify the file. Exiting.\n";
-        exit(EXIT_FAILURE);
+        std::cerr << "Error info:" << e.what() << std::endl;
+        std::cerr << "The event configuration file (" << ev_file_name << ") cannot be loaded. Please verify the file. Exiting." << std::endl;
+        return false;
     }
 
-    results.resize(m->getNumSockets(), stack_content(m->getMaxNumOfIIOStacks(), ctr_data()));
+    return true;
 }
 
-bool initializeIIOCounters( std::vector<struct iio_stacks_on_socket>& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap )
+bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config)
 {
     PCM * m = PCM::getInstance();
     if (!m->IIOEventsAvailable())
@@ -1535,9 +527,7 @@ bool initializeIIOCounters( std::vector<struct iio_stacks_on_socket>& iios, iio_
         return false;
     }
 
-    initializeIIOStructure( iios );
-
-    setupPCIeEventContextAndNameMap( evt_ctx, nameMap );
+    if (!IPlatformMapping::initializeIOStacksStructure(pmu_config.iios, m->getCPUFamilyModel(), m->getNumSockets(), m->getMaxNumOfIOStacks())) return false;
 
-    return true;
+    return setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap);
 }
diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h
index df194c45..25bc0ab9 100644
--- a/src/pcm-iio-pmu.h
+++ b/src/pcm-iio-pmu.h
@@ -1,10 +1,11 @@
 // SPDX-License-Identifier: BSD-3-Clause
-// Copyright (c) 2017-2022, Intel Corporation
+// Copyright (c) 2017-2025, Intel Corporation
 
 // written by Patrick Lu,
 //            Aaron Cruz
+//            Alexander Antonov
 //            and others
-#include "cpucounters.h"
+#pragma once
 
 #ifdef _MSC_VER
     #include <windows.h>
@@ -14,14 +15,8 @@
 #endif
 
 #include <memory>
-#include <fstream>
-#include <stdlib.h>
-#include <limits>
-#include <stdexcept>      // std::length_error
 #include <cstdint>
-#include <numeric>
 #include <algorithm>
-#include <set>
 
 #ifdef _MSC_VER
     #include "freegetopt/getopt.h"
@@ -29,637 +24,98 @@
 
 #include "lspci.h"
 #include "utils.h"
+#include "cpucounters.h"
 
 using namespace std;
 using namespace pcm;
 
 #define PCM_DELAY_DEFAULT 3.0 // in seconds
 
-#define QAT_DID 0x18DA
-#define NIS_DID 0x18D1
-#define HQM_DID 0x270B
-
-#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT)
-#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS)
-
-#define ROOT_BUSES_OFFSET   0xCC
-#define ROOT_BUSES_OFFSET_2 0xD0
-
-#define SKX_SOCKETID_UBOX_DID 0x2014
-#define SKX_UBOX_DEVICE_NUM   0x08
-#define SKX_UBOX_FUNCTION_NUM 0x02
-#define SKX_BUS_NUM_STRIDE    8
-//the below LNID and GID applies to Skylake Server
-#define SKX_UNC_SOCKETID_UBOX_LNID_OFFSET 0xC0
-#define SKX_UNC_SOCKETID_UBOX_GID_OFFSET  0xD4
-
-static const std::string iio_stack_names[6] = {
-    "IIO Stack 0 - CBDMA/DMI      ",
-    "IIO Stack 1 - PCIe0          ",
-    "IIO Stack 2 - PCIe1          ",
-    "IIO Stack 3 - PCIe2          ",
-    "IIO Stack 4 - MCP0           ",
-    "IIO Stack 5 - MCP1           "
-};
-
-static const std::string skx_iio_stack_names[6] = {
-    "IIO Stack 0 - CBDMA/DMI      ",
-    "IIO Stack 1 - PCIe0          ",
-    "IIO Stack 2 - PCIe1          ",
-    "IIO Stack 3 - PCIe2          ",
-    "IIO Stack 4 - MCP0           ",
-    "IIO Stack 5 - MCP1           "
-};
-
-static const std::string icx_iio_stack_names[6] = {
-    "IIO Stack 0 - PCIe0          ",
-    "IIO Stack 1 - PCIe1          ",
-    "IIO Stack 2 - MCP            ",
-    "IIO Stack 3 - PCIe2          ",
-    "IIO Stack 4 - PCIe3          ",
-    "IIO Stack 5 - CBDMA/DMI      "
-};
-
-static const std::string icx_d_iio_stack_names[6] = {
-    "IIO Stack 0 - MCP            ",
-    "IIO Stack 1 - PCIe0          ",
-    "IIO Stack 2 - CBDMA/DMI      ",
-    "IIO Stack 3 - PCIe2          ",
-    "IIO Stack 4 - PCIe3          ",
-    "IIO Stack 5 - PCIe1          "
-};
-
-static const std::string snr_iio_stack_names[5] = {
-    "IIO Stack 0 - QAT            ",
-    "IIO Stack 1 - CBDMA/DMI      ",
-    "IIO Stack 2 - NIS            ",
-    "IIO Stack 3 - HQM            ",
-    "IIO Stack 4 - PCIe           "
-};
-
-#define ICX_CBDMA_DMI_SAD_ID 0
-#define ICX_MCP_SAD_ID       3
-
-#define ICX_PCH_PART_ID   0
-#define ICX_CBDMA_PART_ID 3
-
-#define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4
-#define SNR_ICX_MESH2IIO_MMAP_DID      0x09A2
-
-#define ICX_VMD_PCI_DEVNO   0x00
-#define ICX_VMD_PCI_FUNCNO  0x05
-
-static const std::map<int, int> icx_sad_to_pmu_id_mapping = {
-    { ICX_CBDMA_DMI_SAD_ID, 5 },
-    { 1,                    0 },
-    { 2,                    1 },
-    { ICX_MCP_SAD_ID,       2 },
-    { 4,                    3 },
-    { 5,                    4 }
-};
-
-static const std::map<int, int> icx_d_sad_to_pmu_id_mapping = {
-    { ICX_CBDMA_DMI_SAD_ID, 2 },
-    { 1,                    5 },
-    { 2,                    1 },
-    { ICX_MCP_SAD_ID,       0 },
-    { 4,                    3 },
-    { 5,                    4 }
-};
-
-#define SNR_ACCELERATOR_PART_ID 4
-
-#define SNR_ROOT_PORT_A_DID 0x334A
-
-#define SNR_CBDMA_DMI_SAD_ID 0
-#define SNR_PCIE_GEN3_SAD_ID 1
-#define SNR_HQM_SAD_ID       2
-#define SNR_NIS_SAD_ID       3
-#define SNR_QAT_SAD_ID       4
-
-static const std::map<int, int> snr_sad_to_pmu_id_mapping = {
-    { SNR_CBDMA_DMI_SAD_ID, 1 },
-    { SNR_PCIE_GEN3_SAD_ID, 4 },
-    { SNR_HQM_SAD_ID      , 3 },
-    { SNR_NIS_SAD_ID      , 2 },
-    { SNR_QAT_SAD_ID      , 0 }
-};
-
-#define HQMV2_DID   0x2710 // Hardware Queue Manager v2
-#define HQMV25_DID  0x2714 // Hardware Queue Manager v2.5
-#define DSA_DID     0x0b25 // Data Streaming Accelerator (DSA)
-#define IAX_DID     0x0cfe // In-Memory Database Analytics Accelerator (IAX)
-#define QATV2_DID   0x4940 // QuickAssist (CPM) v2
-
-#define SPR_DMI_PART_ID                7
-#define SPR_XCC_HQM_PART_ID            5
-#define SPR_MCC_HQM_PART_ID            4
-#define SPR_XCC_QAT_PART_ID            4
-#define SPR_MCC_QAT_PART_ID            5
-#define SPR_SAD_CONTROL_CFG_OFFSET     SNR_ICX_SAD_CONTROL_CFG_OFFSET
-
-#define SPR_PCU_CR3_DID 0x325b
-#define SPR_PCU_CR3_REG_DEVICE 0x1e
-#define SPR_PCU_CR3_REG_FUNCTION 0x03
-#define SPR_CAPID4_OFFSET 0x94
-#define SPR_CAPID4_GET_PHYSICAL_CHOP(capid4) ((capid4 >> 6) & 3)
-#define SPR_PHYSICAL_CHOP_XCC 0b11
-#define SPR_PHYSICAL_CHOP_MCC 0b01
-
-#define SPR_XCC_DMI_PMON_ID         1
-#define SPR_XCC_PCIE_GEN5_0_PMON_ID 2
-#define SPR_XCC_PCIE_GEN5_1_PMON_ID 4
-#define SPR_XCC_PCIE_GEN5_2_PMON_ID 6
-#define SPR_XCC_PCIE_GEN5_3_PMON_ID 7
-#define SPR_XCC_PCIE_GEN5_4_PMON_ID 9
-#define SPR_XCC_IDX0_PMON_ID        0
-#define SPR_XCC_IDX1_PMON_ID        3
-#define SPR_XCC_IDX2_PMON_ID        5
-#define SPR_XCC_IDX3_PMON_ID        8
-
-const std::map<int, int> spr_xcc_sad_to_pmu_id_mapping = {
-    { 0,  SPR_XCC_DMI_PMON_ID         },
-    { 1,  SPR_XCC_PCIE_GEN5_0_PMON_ID },
-    { 2,  SPR_XCC_PCIE_GEN5_1_PMON_ID },
-    { 3,  SPR_XCC_PCIE_GEN5_2_PMON_ID },
-    { 4,  SPR_XCC_PCIE_GEN5_3_PMON_ID },
-    { 5,  SPR_XCC_PCIE_GEN5_4_PMON_ID },
-    { 8,  SPR_XCC_IDX0_PMON_ID        },
-    { 9,  SPR_XCC_IDX1_PMON_ID        },
-    { 10, SPR_XCC_IDX2_PMON_ID        },
-    { 11, SPR_XCC_IDX3_PMON_ID        }
-};
-
-#define SPR_MCC_DMI_PMON_ID         10
-#define SPR_MCC_PCIE_GEN5_0_PMON_ID 0 // assumption
-#define SPR_MCC_PCIE_GEN5_1_PMON_ID 1
-#define SPR_MCC_PCIE_GEN5_2_PMON_ID 2
-#define SPR_MCC_PCIE_GEN5_3_PMON_ID 4 // assumption
-#define SPR_MCC_PCIE_GEN5_4_PMON_ID 5
-#define SPR_MCC_IDX0_PMON_ID        3
-
-const std::map<int, int> spr_mcc_sad_to_pmu_id_mapping = {
-    { 0, SPR_MCC_PCIE_GEN5_0_PMON_ID },
-    { 1, SPR_MCC_PCIE_GEN5_1_PMON_ID },
-    { 2, SPR_MCC_PCIE_GEN5_2_PMON_ID },
-    { 3, SPR_MCC_DMI_PMON_ID         },
-    { 4, SPR_MCC_PCIE_GEN5_3_PMON_ID },
-    { 5, SPR_MCC_PCIE_GEN5_4_PMON_ID },
-    { 8, SPR_MCC_IDX0_PMON_ID        },
-};
-
-static const std::string spr_xcc_iio_stack_names[] = {
-    "IIO Stack 0 - IDX0  ",
-    "IIO Stack 1 - DMI   ",
-    "IIO Stack 2 - PCIe0 ",
-    "IIO Stack 3 - IDX1  ",
-    "IIO Stack 4 - PCIe1 ",
-    "IIO Stack 5 - IDX2  ",
-    "IIO Stack 6 - PCIe2 ",
-    "IIO Stack 7  - PCIe3",
-    "IIO Stack 8  - IDX3 ",
-    "IIO Stack 9  - PCIe4",
-    "IIO Stack 10 - NONE ",
-    "IIO Stack 11 - NONE ",
-};
-
-/*
- * SPR MCC has 7 I/O stacks but PMON block for DMI has ID number 10.
- * And just to follow such enumeration keep Stack 10 for DMI.
- */
-static const std::string spr_mcc_iio_stack_names[] = {
-    "IIO Stack 0 - PCIe0 ",
-    "IIO Stack 1 - PCIe1 ",
-    "IIO Stack 2 - PCIe2 ",
-    "IIO Stack 3 - IDX0  ",
-    "IIO Stack 4 - PCIe3 ",
-    "IIO Stack 5 - PCIe4 ",
-    "IIO Stack 6 - NONE  ",
-    "IIO Stack 7 - NONE  ",
-    "IIO Stack 8 - NONE  ",
-    "IIO Stack 9 - NONE  ",
-    "IIO Stack 10 - DMI  ",
-};
-
-// MS2IOSF stack IDs in CHA notation
-#define GRR_PCH_DSA_GEN4_SAD_ID 0
-#define GRR_DLB_SAD_ID          1
-#define GRR_NIS_QAT_SAD_ID      2
-
-#define GRR_PCH_DSA_GEN4_PMON_ID 2
-#define GRR_DLB_PMON_ID          1
-#define GRR_NIS_QAT_PMON_ID      0
-
-// Stack 0 contains PCH, DSA and CPU PCIe Gen4 Complex
-const std::map<int, int> grr_sad_to_pmu_id_mapping = {
-    { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID },
-    { GRR_DLB_SAD_ID,          GRR_DLB_PMON_ID          },
-    { GRR_NIS_QAT_SAD_ID,      GRR_NIS_QAT_PMON_ID      },
-};
-
-#define GRR_DLB_PART_ID 0
-#define GRR_NIS_PART_ID 0
-#define GRR_QAT_PART_ID 1
-
-static const std::string grr_iio_stack_names[3] = {
-    "IIO Stack 0 - NIS/QAT        ",
-    "IIO Stack 1 - HQM            ",
-    "IIO Stack 2 - PCH/DSA/PCIe   "
-};
-
-#define EMR_DMI_PMON_ID         7
-#define EMR_PCIE_GEN5_0_PMON_ID 1
-#define EMR_PCIE_GEN5_1_PMON_ID 2
-#define EMR_PCIE_GEN5_2_PMON_ID 3
-#define EMR_PCIE_GEN5_3_PMON_ID 8
-#define EMR_PCIE_GEN5_4_PMON_ID 6
-#define EMR_IDX0_PMON_ID        0
-#define EMR_IDX1_PMON_ID        4
-#define EMR_IDX2_PMON_ID        5
-#define EMR_IDX3_PMON_ID        9
-
-const std::map<int, int> emr_sad_to_pmu_id_mapping = {
-    { 0,  EMR_DMI_PMON_ID         },
-    { 1,  EMR_PCIE_GEN5_0_PMON_ID },
-    { 2,  EMR_PCIE_GEN5_1_PMON_ID },
-    { 3,  EMR_PCIE_GEN5_2_PMON_ID },
-    { 4,  EMR_PCIE_GEN5_3_PMON_ID },
-    { 5,  EMR_PCIE_GEN5_4_PMON_ID },
-    { 8,  EMR_IDX0_PMON_ID        },
-    { 9,  EMR_IDX1_PMON_ID        },
-    { 10, EMR_IDX2_PMON_ID        },
-    { 11, EMR_IDX3_PMON_ID        }
-};
-
-static const std::string emr_iio_stack_names[] = {
-    "IIO Stack 0 - IDX0  ",
-    "IIO Stack 1 - PCIe3 ",
-    "IIO Stack 2 - PCIe0 ",
-    "IIO Stack 3 - IDX1  ",
-    "IIO Stack 4 - PCIe1 ",
-    "IIO Stack 5 - IDX2  ",
-    "IIO Stack 6 - PCIe2 ",
-    "IIO Stack 7  - DMI",
-    "IIO Stack 8  - IDX3 ",
-    "IIO Stack 9  - PCIe4",
-    "IIO Stack 10 - NONE ",
-    "IIO Stack 11 - NONE ",
-};
-
-enum EagleStreamPlatformStacks
-{
-    esDMI = 0,
-    esPCIe0,
-    esPCIe1,
-    esPCIe2,
-    esPCIe3,
-    esPCIe4,
-    esDINO0,
-    esDINO1,
-    esDINO2,
-    esDINO3,
-    esEndOfList
-};
-
-const std::vector<int> spr_xcc_stacks_enumeration = {
-    /* esDMI   */ SPR_XCC_DMI_PMON_ID,
-    /* esPCIe0 */ SPR_XCC_PCIE_GEN5_0_PMON_ID,
-    /* esPCIe1 */ SPR_XCC_PCIE_GEN5_1_PMON_ID,
-    /* esPCIe2 */ SPR_XCC_PCIE_GEN5_2_PMON_ID,
-    /* esPCIe3 */ SPR_XCC_PCIE_GEN5_3_PMON_ID,
-    /* esPCIe4 */ SPR_XCC_PCIE_GEN5_4_PMON_ID,
-    /* esDINO0 */ SPR_XCC_IDX0_PMON_ID,
-    /* esDINO1 */ SPR_XCC_IDX1_PMON_ID,
-    /* esDINO2 */ SPR_XCC_IDX2_PMON_ID,
-    /* esDINO3 */ SPR_XCC_IDX3_PMON_ID,
-};
-
-const std::vector<int> spr_mcc_stacks_enumeration = {
-    /* esDMI   */ SPR_MCC_DMI_PMON_ID,
-    /* esPCIe0 */ SPR_MCC_PCIE_GEN5_0_PMON_ID,
-    /* esPCIe1 */ SPR_MCC_PCIE_GEN5_1_PMON_ID,
-    /* esPCIe2 */ SPR_MCC_PCIE_GEN5_2_PMON_ID,
-    /* esPCIe3 */ SPR_MCC_PCIE_GEN5_3_PMON_ID,
-    /* esPCIe4 */ SPR_MCC_PCIE_GEN5_4_PMON_ID,
-    /* esDINO0 */ SPR_MCC_IDX0_PMON_ID,
-};
-
-const std::vector<int> emr_stacks_enumeration = {
-    /* esDMI   */ EMR_DMI_PMON_ID,
-    /* esPCIe0 */ EMR_PCIE_GEN5_0_PMON_ID,
-    /* esPCIe1 */ EMR_PCIE_GEN5_1_PMON_ID,
-    /* esPCIe2 */ EMR_PCIE_GEN5_2_PMON_ID,
-    /* esPCIe3 */ EMR_PCIE_GEN5_3_PMON_ID,
-    /* esPCIe4 */ EMR_PCIE_GEN5_4_PMON_ID,
-    /* esDINO0 */ EMR_IDX0_PMON_ID,
-    /* esDINO1 */ EMR_IDX1_PMON_ID,
-    /* esDINO2 */ EMR_IDX2_PMON_ID,
-    /* esDINO3 */ EMR_IDX3_PMON_ID,
-};
-
-enum class EagleStreamSupportedTypes
-{
-    esInvalid = -1,
-    esSprXcc,
-    esSprMcc,
-    esEmrXcc
-};
-
-typedef EagleStreamSupportedTypes estype;
-
-const std::map<estype, std::vector<int>> es_stacks_enumeration = {
-    {estype::esSprXcc, spr_xcc_stacks_enumeration},
-    {estype::esSprMcc, spr_mcc_stacks_enumeration},
-    {estype::esEmrXcc, emr_stacks_enumeration    },
-};
-
-const std::map<estype, const std::string *> es_stack_names = {
-    {estype::esSprXcc, spr_xcc_iio_stack_names},
-    {estype::esSprMcc, spr_mcc_iio_stack_names},
-    {estype::esEmrXcc, emr_iio_stack_names    },
-};
-
-const std::map<estype, std::map<int, int>> es_sad_to_pmu_id_mapping = {
-    {estype::esSprXcc, spr_xcc_sad_to_pmu_id_mapping},
-    {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping},
-    {estype::esEmrXcc, emr_sad_to_pmu_id_mapping    },
-};
-
-#define SRF_PE0_PMON_ID         3
-#define SRF_PE1_PMON_ID         4
-#define SRF_PE2_PMON_ID         2
-#define SRF_PE3_PMON_ID         5
-/*
- * There are platform configuration when FlexUPI stacks (stacks 5 and 6) are enabled as
- * PCIe stack and PCIe ports are disabled (ports 2 and 3) and vice sersa. See details here:
- * In these cases the PMON IDs are different.
- * So, defines with _FLEX_ are applicable for cases when FlexUPI stacks
- * are working as PCIe ports.
- */
-#define SRF_PE4_PMON_ID             11
-#define SRF_FLEX_PE4_PMON_ID        13
-#define SRF_PE5_PMON_ID             12
-#define SRF_FLEX_PE5_PMON_ID        10
-
-#define SRF_PE6_PMON_ID             0
-#define SRF_PE7_PMON_ID             7
-#define SRF_PE8_PMON_ID             8
-#define SRF_HC0_PMON_ID             1
-#define SRF_HC1_PMON_ID             6
-#define SRF_HC2_PMON_ID             9
-#define SRF_HC3_PMON_ID             14
-
-#define SRF_PE0_SAD_BUS_ID         2
-#define SRF_PE1_SAD_BUS_ID         3
-#define SRF_PE2_SAD_BUS_ID         1
-#define SRF_PE3_SAD_BUS_ID         4
-#define SRF_PE4_SAD_BUS_ID         29
-#define SRF_FLEX_PE4_SAD_BUS_ID    SRF_PE4_SAD_BUS_ID
-#define SRF_PE5_SAD_BUS_ID         26
-#define SRF_FLEX_PE5_SAD_BUS_ID    SRF_PE5_SAD_BUS_ID
-#define SRF_PE6_SAD_BUS_ID         0  // UPI0
-#define SRF_PE7_SAD_BUS_ID         5  // UPI1
-#define SRF_PE8_SAD_BUS_ID         28 // UPI2
-#define SRF_UBOXA_SAD_BUS_ID       30
-#define SRF_UBOXB_SAD_BUS_ID       31
-
-const std::set<int> srf_pcie_stacks({
-    SRF_PE0_SAD_BUS_ID,
-    SRF_PE1_SAD_BUS_ID,
-    SRF_PE2_SAD_BUS_ID,
-    SRF_PE3_SAD_BUS_ID,
-    SRF_PE4_SAD_BUS_ID,
-    SRF_FLEX_PE4_SAD_BUS_ID,
-    SRF_PE5_SAD_BUS_ID,
-    SRF_FLEX_PE5_SAD_BUS_ID,
-    SRF_PE6_SAD_BUS_ID,
-    SRF_PE7_SAD_BUS_ID,
-    SRF_PE8_SAD_BUS_ID,
-});
-
-#define SRF_HC0_SAD_BUS_ID         8
-#define SRF_HC1_SAD_BUS_ID         12
-#define SRF_HC2_SAD_BUS_ID         20
-#define SRF_HC3_SAD_BUS_ID         16
-
-const std::map<int, int> srf_sad_to_pmu_id_mapping = {
-    { SRF_PE0_SAD_BUS_ID,      SRF_PE0_PMON_ID      },
-    { SRF_PE1_SAD_BUS_ID,      SRF_PE1_PMON_ID      },
-    { SRF_PE2_SAD_BUS_ID,      SRF_PE2_PMON_ID      },
-    { SRF_PE3_SAD_BUS_ID,      SRF_PE3_PMON_ID      },
-    { SRF_PE4_SAD_BUS_ID,      SRF_PE4_PMON_ID      },
-    { SRF_FLEX_PE4_SAD_BUS_ID, SRF_FLEX_PE4_PMON_ID },
-    { SRF_PE5_SAD_BUS_ID,      SRF_PE5_PMON_ID      },
-    { SRF_FLEX_PE5_SAD_BUS_ID, SRF_FLEX_PE5_PMON_ID },
-    { SRF_PE6_SAD_BUS_ID,      SRF_PE6_PMON_ID      },
-    { SRF_PE7_SAD_BUS_ID,      SRF_PE7_PMON_ID      },
-    { SRF_PE8_SAD_BUS_ID,      SRF_PE8_PMON_ID      },
-    { SRF_HC0_SAD_BUS_ID,      SRF_HC0_PMON_ID      },
-    { SRF_HC1_SAD_BUS_ID,      SRF_HC1_PMON_ID      },
-    { SRF_HC2_SAD_BUS_ID,      SRF_HC2_PMON_ID      },
-    { SRF_HC3_SAD_BUS_ID,      SRF_HC3_PMON_ID      },
-};
-
-#define SRF_DSA_IAX_PART_NUMBER 0
-#define SRF_HQM_PART_NUMBER     5
-#define SRF_QAT_PART_NUMBER     4
-
-static const std::string srf_iio_stack_names[] = {
-    "IIO Stack 0  - PCIe6     ", // SRF_PE6_PMON_ID      0
-    "IIO Stack 1  - HCx0      ", // SRF_HC0_PMON_ID      1
-    "IIO Stack 2  - PCIe2     ", // SRF_PE2_PMON_ID      2
-    "IIO Stack 3  - PCIe0     ", // SRF_PE0_PMON_ID      3
-    "IIO Stack 4  - PCIe1     ", // SRF_PE1_PMON_ID      4
-    "IIO Stack 5  - PCIe3     ", // SRF_PE3_PMON_ID      5
-    "IIO Stack 6  - HCx1      ", // SRF_HC1_PMON_ID      6
-    "IIO Stack 7  - PCIe7     ", // SRF_PE7_PMON_ID      7
-    "IIO Stack 8  - PCIe8     ", // SRF_PE8_PMON_ID      8
-    "IIO Stack 9  - HCx3      ", // SRF_HC3_PMON_ID      9
-    "IIO Stack 10 - Flex PCIe5", // SRF_FLEX_PE5_PMON_ID 10
-    "IIO Stack 11 - PCIe4     ", // SRF_PE4_PMON_ID      11
-    "IIO Stack 12 - PCIe5     ", // SRF_PE5_PMON_ID      12
-    "IIO Stack 13 - Flex PCIe4", // SRF_FLEX_PE4_PMON_ID 13
-    "IIO Stack 14 - HCx2      ", // SRF_HC2_PMON_ID      14
-};
-
 struct iio_counter : public counter {
   std::vector<result_content> data;
 };
 
-extern result_content results;
-
 typedef struct
 {
-    PCM *m;
+    uint32 cpu_family_model;
     iio_counter ctr;
     vector<struct iio_counter> ctrs;
 } iio_evt_parse_context;
 
-vector<string> combine_stack_name_and_counter_names(string stack_name, const map<string,std::pair<h_id,std::map<string,v_id>>> &nameMap);
+vector<string> combine_stack_name_and_counter_names(string stack_name, const PCIeEventNameMap& nameMap);
 
 string build_pci_header(const PCIDB & pciDB, uint32_t column_width, const struct pci &p, int part = -1, uint32_t level = 0);
 
 void build_pci_tree(vector<string> &buffer, const PCIDB & pciDB, uint32_t column_width, const struct pci &p, int part, uint32_t level = 0);
 
-vector<string> build_display(vector<struct iio_stacks_on_socket>& iios, vector<struct iio_counter>& ctrs, const PCIDB& pciDB,
-                             const map<string,std::pair<h_id,std::map<string,v_id>>> &nameMap);
-
 std::string get_root_port_dev(const bool show_root_port, int part_id,  const pcm::iio_stack *stack);
 
-vector<string> build_csv(vector<struct iio_stacks_on_socket>& iios, vector<struct iio_counter>& ctrs,
-                         const bool human_readable, const bool show_root_port, const std::string& csv_delimiter,
-                         const map<string,std::pair<h_id,std::map<string,v_id>>> &nameMap);
-
-class IPlatformMapping {
-private:
-    uint32_t m_sockets;
-    uint32_t m_model;
-protected:
-    void probeDeviceRange(std::vector<struct pci> &child_pci_devs, int domain, int secondary, int subordinate);
-public:
-    IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {}
-    virtual ~IPlatformMapping() {};
-    static std::unique_ptr<IPlatformMapping> getPlatformMapping(int cpu_model, uint32_t sockets_count);
-    virtual bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) = 0;
-
-    uint32_t socketsCount() const { return m_sockets; }
-    uint32_t cpuId() const { return m_model; }
-};
-
-// Mapping for SkyLake Server.
-class PurleyPlatformMapping: public IPlatformMapping {
-private:
-    void getUboxBusNumbers(std::vector<uint32_t>& ubox);
-public:
-    PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {}
-    ~PurleyPlatformMapping() = default;
-    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
-};
-
-class IPlatformMapping10Nm: public IPlatformMapping {
-private:
-public:
-    IPlatformMapping10Nm(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {}
-    ~IPlatformMapping10Nm() = default;
-    bool getSadIdRootBusMap(uint32_t socket_id, std::map<uint8_t, uint8_t>& sad_id_bus_map);
+struct pcm_iio_display_config {
+    bool csv            = false;
+    bool human_readable = false;
+    bool show_root_port = false;
+    bool list           = false;
+    std::string csv_delimiter = ",";
+    std::string output_file   = "";
 };
 
-// Mapping for IceLake Server.
-class WhitleyPlatformMapping: public IPlatformMapping10Nm {
-private:
-    const bool icx_d;
-    const std::map<int, int>& sad_to_pmu_id_mapping;
-    const std::string * iio_stack_names;
-public:
-    WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count),
-        icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D),
-        sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping),
-        iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names)
-    {
-    }
-    ~WhitleyPlatformMapping() = default;
-    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+struct pcm_iio_pmu_config {
+    double delay = PCM_DELAY_DEFAULT;
+    // Map with metrics names.
+    PCIeEventNameMap pcieEventNameMap;
+    vector<struct iio_stacks_on_socket> iios;
+    iio_evt_parse_context evt_ctx;
 };
 
-// Mapping for Snowridge.
-class JacobsvillePlatformMapping: public IPlatformMapping10Nm {
-private:
-public:
-    JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {}
-    ~JacobsvillePlatformMapping() = default;
-    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
-    bool JacobsvilleAccelerators(const std::pair<uint8_t, uint8_t>& sad_id_bus_pair, struct iio_stack& stack);
+struct pcm_iio_config {
+    struct pcm_iio_display_config display;
+    struct pcm_iio_pmu_config pmu_config;
+    PCIDB pciDB;
 };
 
-class EagleStreamPlatformMapping: public IPlatformMapping
-{
-private:
-    bool getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses);
-    bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-    bool eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-    bool eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-    bool eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-    bool isDmiStack(int unit);
-    bool isPcieStack(int unit);
-    bool isDinoStack(int unit);
-    std::uint32_t m_chop;
-    EagleStreamSupportedTypes m_es_type;
+class PcmIioOutputBuilder {
 public:
-    EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {}
-    ~EagleStreamPlatformMapping() = default;
-    bool setChopValue();
-    bool isXccPlatform() const { return m_chop == kXccChop; }
+    PcmIioOutputBuilder(struct pcm_iio_config& config) : m_config(config) {}
 
-    const std::uint32_t kXccChop = 0b11;
-    const std::uint32_t kMccChop = 0b01;
+    virtual ~PcmIioOutputBuilder() = default;
 
-    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+    virtual vector<string> buildDisplayBuffer() = 0;
+protected:
+    struct pcm_iio_config& m_config;
 };
 
-class LoganvillePlatform: public IPlatformMapping10Nm {
-private:
-    bool loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id);
-    bool loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id);
-    bool loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id);
-public:
-    LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {}
-    ~LoganvillePlatform() = default;
-    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
-};
+std::unique_ptr<PcmIioOutputBuilder> getDisplayBuilder(struct pcm_iio_config& config);
 
-class Xeon6thNextGenPlatform: public IPlatformMapping {
-private:
-    bool getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses);
-protected:
-    virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0;
-public:
-    Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {}
-    virtual ~Xeon6thNextGenPlatform() = default;
-
-    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
-};
+int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map<std::string, uint32_t> &ofm, std::string key, uint64 numValue);
 
-class BirchStreamPlatform: public Xeon6thNextGenPlatform {
-private:
-    bool isPcieStack(int unit);
-    bool isRootHcStack(int unit);
-    bool isPartHcStack(int unit);
-    bool isUboxStack(int unit);
+class CounterHandlerStrategy;
 
-    bool birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-    bool birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-protected:
-    bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override;
+class PcmIioDataCollector {
 public:
-    BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {}
-    ~BirchStreamPlatform() = default;
-};
+    PcmIioDataCollector(struct pcm_iio_pmu_config& config);
+    ~PcmIioDataCollector() = default;
 
-class KasseyvillePlatform: public Xeon6thNextGenPlatform {
+    void collectData();
 private:
-    bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
-    bool isUboxStack(int unit)
-    {
-        return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit;
-    }
-public:
-    KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {}
-    ~KasseyvillePlatform() = default;
-};
-
-int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map<std::string, uint32_t> &ofm, std::string key, uint64 numValue);
+    struct pcm_iio_pmu_config& m_config;
+    PCM *m_pcm;
+    uint32_t m_delay_ms;
+    uint32_t m_stacks_count;
+    double m_time_scaling_factor;
+    std::unique_ptr<SimpleCounterState[]> m_before;
+    std::unique_ptr<SimpleCounterState[]> m_after;
+    result_content m_results;
+    std::vector<std::shared_ptr<CounterHandlerStrategy>> m_strategies;
 
-result_content get_IIO_Samples(PCM *m, const std::vector<struct iio_stacks_on_socket>& iios, const struct iio_counter & ctr, uint32_t delay_ms);
+    result_content getSample(struct iio_counter & ctr);
+    void initializeCounterHandlers();
 
-void collect_data(PCM *m, const double delay, vector<struct iio_stacks_on_socket>& iios, vector<struct iio_counter>& ctrs);
+    uint32_t getStackIndex(uint32_t socket_id, uint32_t io_unit_id) const { return m_stacks_count * socket_id + io_unit_id; }
 
-void initializeIIOStructure( std::vector<struct iio_stacks_on_socket>& iios );
+    static constexpr int COUNTERS_NUMBER = 4;
+};
 
 void fillOpcodeFieldMapForPCIeEvents(map<string,uint32_t>& opcodeFieldMap);
 
-typedef map<string,std::pair<h_id,std::map<string,v_id>>> PCIeEventNameMap_t;
-
-void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap);
-
-bool initializeIIOCounters( std::vector<struct iio_stacks_on_socket>& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap );
+bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config);
 
diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp
new file mode 100644
index 00000000..f53df228
--- /dev/null
+++ b/src/pcm-iio-topology.cpp
@@ -0,0 +1,1671 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2025, Intel Corporation
+
+// written by Patrick Lu,
+//            Aaron Cruz
+//            Alexander Antonov
+//            and others
+#include <limits>
+#include <numeric>
+#include <set>
+#include <unordered_map>
+#include <unordered_set>
+
+#include "pcm-iio-topology.h"
+
+#define QAT_DID 0x18DA
+#define NIS_DID 0x18D1
+#define HQM_DID 0x270B
+
+#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT)
+#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS)
+
+#define ROOT_BUSES_OFFSET   0xCC
+#define ROOT_BUSES_OFFSET_2 0xD0
+
+#define SKX_SOCKETID_UBOX_DID 0x2014
+#define SKX_UBOX_DEVICE_NUM   0x08
+#define SKX_UBOX_FUNCTION_NUM 0x02
+#define SKX_BUS_NUM_STRIDE    8
+//the below LNID and GID applies to Skylake Server
+#define SKX_UNC_SOCKETID_UBOX_LNID_OFFSET 0xC0
+#define SKX_UNC_SOCKETID_UBOX_GID_OFFSET  0xD4
+
+#define ICX_CBDMA_DMI_SAD_ID 0
+#define ICX_MCP_SAD_ID       3
+
+#define ICX_PCH_PART_ID   0
+#define ICX_CBDMA_PART_ID 3
+
+#define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4
+#define SNR_ICX_MESH2IIO_MMAP_DID      0x09A2
+
+#define ICX_VMD_PCI_DEVNO   0x00
+#define ICX_VMD_PCI_FUNCNO  0x05
+
+#define SNR_ACCELERATOR_PART_ID 4
+
+#define SNR_ROOT_PORT_A_DID 0x334A
+
+#define SNR_CBDMA_DMI_SAD_ID 0
+#define SNR_PCIE_GEN3_SAD_ID 1
+#define SNR_HQM_SAD_ID       2
+#define SNR_NIS_SAD_ID       3
+#define SNR_QAT_SAD_ID       4
+
+#define HQMV2_DID   0x2710 // Hardware Queue Manager v2
+#define HQMV25_DID  0x2714 // Hardware Queue Manager v2.5
+#define DSA_DID     0x0b25 // Data Streaming Accelerator (DSA)
+#define IAX_DID     0x0cfe // In-Memory Database Analytics Accelerator (IAX)
+#define QATV2_DID   0x4940 // QuickAssist (CPM) v2
+
+#define SPR_DMI_PART_ID                7
+#define SPR_XCC_HQM_PART_ID            5
+#define SPR_MCC_HQM_PART_ID            4
+#define SPR_XCC_QAT_PART_ID            4
+#define SPR_MCC_QAT_PART_ID            5
+#define SPR_SAD_CONTROL_CFG_OFFSET     SNR_ICX_SAD_CONTROL_CFG_OFFSET
+
+#define SPR_PCU_CR3_DID 0x325b
+#define SPR_PCU_CR3_REG_DEVICE 0x1e
+#define SPR_PCU_CR3_REG_FUNCTION 0x03
+#define SPR_CAPID4_OFFSET 0x94
+#define SPR_CAPID4_GET_PHYSICAL_CHOP(capid4) ((capid4 >> 6) & 3)
+#define SPR_PHYSICAL_CHOP_XCC 0b11
+#define SPR_PHYSICAL_CHOP_MCC 0b01
+
+#define SPR_XCC_DMI_PMON_ID         1
+#define SPR_XCC_PCIE_GEN5_0_PMON_ID 2
+#define SPR_XCC_PCIE_GEN5_1_PMON_ID 4
+#define SPR_XCC_PCIE_GEN5_2_PMON_ID 6
+#define SPR_XCC_PCIE_GEN5_3_PMON_ID 7
+#define SPR_XCC_PCIE_GEN5_4_PMON_ID 9
+#define SPR_XCC_IDX0_PMON_ID        0
+#define SPR_XCC_IDX1_PMON_ID        3
+#define SPR_XCC_IDX2_PMON_ID        5
+#define SPR_XCC_IDX3_PMON_ID        8
+
+#define SPR_MCC_DMI_PMON_ID         10
+#define SPR_MCC_PCIE_GEN5_0_PMON_ID 0 // assumption
+#define SPR_MCC_PCIE_GEN5_1_PMON_ID 1
+#define SPR_MCC_PCIE_GEN5_2_PMON_ID 2
+#define SPR_MCC_PCIE_GEN5_3_PMON_ID 4 // assumption
+#define SPR_MCC_PCIE_GEN5_4_PMON_ID 5
+#define SPR_MCC_IDX0_PMON_ID        3
+
+// MS2IOSF stack IDs in CHA notation
+#define GRR_PCH_DSA_GEN4_SAD_ID 0
+#define GRR_DLB_SAD_ID          1
+#define GRR_NIS_QAT_SAD_ID      2
+
+#define GRR_PCH_DSA_GEN4_PMON_ID 2
+#define GRR_DLB_PMON_ID          1
+#define GRR_NIS_QAT_PMON_ID      0
+
+#define GRR_DLB_PART_ID 0
+#define GRR_NIS_PART_ID 0
+#define GRR_QAT_PART_ID 1
+
+#define EMR_DMI_PMON_ID         7
+#define EMR_PCIE_GEN5_0_PMON_ID 1
+#define EMR_PCIE_GEN5_1_PMON_ID 2
+#define EMR_PCIE_GEN5_2_PMON_ID 3
+#define EMR_PCIE_GEN5_3_PMON_ID 8
+#define EMR_PCIE_GEN5_4_PMON_ID 6
+#define EMR_IDX0_PMON_ID        0
+#define EMR_IDX1_PMON_ID        4
+#define EMR_IDX2_PMON_ID        5
+#define EMR_IDX3_PMON_ID        9
+
+#define SRF_PE0_PMON_ID         3
+#define SRF_PE1_PMON_ID         4
+#define SRF_PE2_PMON_ID         2
+#define SRF_PE3_PMON_ID         5
+/*
+ * There are platform configuration when FlexUPI stacks (stacks 5 and 6) are enabled as
+ * PCIe stack and PCIe ports are disabled (ports 2 and 3) and vice sersa. See details here:
+ * In these cases the PMON IDs are different.
+ * So, defines with _FLEX_ are applicable for cases when FlexUPI stacks
+ * are working as PCIe ports.
+ */
+#define SRF_PE4_PMON_ID             11
+#define SRF_FLEX_PE4_PMON_ID        13
+#define SRF_PE5_PMON_ID             12
+#define SRF_FLEX_PE5_PMON_ID        10
+
+#define SRF_PE6_PMON_ID             0
+#define SRF_PE7_PMON_ID             7
+#define SRF_PE8_PMON_ID             8
+#define SRF_HC0_PMON_ID             1
+#define SRF_HC1_PMON_ID             6
+#define SRF_HC2_PMON_ID             9
+#define SRF_HC3_PMON_ID             14
+
+#define SRF_PE0_SAD_BUS_ID         2
+#define SRF_PE1_SAD_BUS_ID         3
+#define SRF_PE2_SAD_BUS_ID         1
+#define SRF_PE3_SAD_BUS_ID         4
+#define SRF_PE4_SAD_BUS_ID         29
+#define SRF_FLEX_PE4_SAD_BUS_ID    SRF_PE4_SAD_BUS_ID
+#define SRF_PE5_SAD_BUS_ID         26
+#define SRF_FLEX_PE5_SAD_BUS_ID    SRF_PE5_SAD_BUS_ID
+#define SRF_PE6_SAD_BUS_ID         0  // UPI0
+#define SRF_PE7_SAD_BUS_ID         5  // UPI1
+#define SRF_PE8_SAD_BUS_ID         28 // UPI2
+#define SRF_UBOXA_SAD_BUS_ID       30
+#define SRF_UBOXB_SAD_BUS_ID       31
+
+#define SRF_HC0_SAD_BUS_ID         8
+#define SRF_HC1_SAD_BUS_ID         12
+#define SRF_HC2_SAD_BUS_ID         20
+#define SRF_HC3_SAD_BUS_ID         16
+
+#define SRF_DSA_IAX_PART_NUMBER 0
+#define SRF_HQM_PART_NUMBER     5
+#define SRF_QAT_PART_NUMBER     4
+
+// Mapping for SkyLake Server.
+class PurleyPlatformMapping: public IPlatformMapping {
+private:
+    void getUboxBusNumbers(std::vector<uint32_t>& ubox);
+
+    const std::string skx_iio_stack_names[6] = {
+        "IIO Stack 0 - CBDMA/DMI      ",
+        "IIO Stack 1 - PCIe0          ",
+        "IIO Stack 2 - PCIe1          ",
+        "IIO Stack 3 - PCIe2          ",
+        "IIO Stack 4 - MCP0           ",
+        "IIO Stack 5 - MCP1           "
+    };
+protected:
+    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    PurleyPlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets) {}
+    ~PurleyPlatformMapping() = default;
+};
+
+void PurleyPlatformMapping::getUboxBusNumbers(std::vector<uint32_t>& ubox)
+{
+    for (uint16_t bus = 0; bus < 256; bus++) {
+        for (uint8_t device = 0; device < 32; device++) {
+            for (uint8_t function = 0; function < 8; function++) {
+                struct pci pci_dev;
+                pci_dev.bdf.busno = (uint8_t)bus;
+                pci_dev.bdf.devno = device;
+                pci_dev.bdf.funcno = function;
+                if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SKX_SOCKETID_UBOX_DID)) {
+                    ubox.push_back(bus);
+                }
+            }
+        }
+    }
+}
+
+bool PurleyPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    std::vector<uint32_t> ubox;
+    getUboxBusNumbers(ubox);
+    if (ubox.empty()) {
+        cerr << "UBOXs were not found! Program aborted" << endl;
+        return false;
+    }
+
+    for (uint32_t socket_id = 0; socket_id < socketsCount(); socket_id++) {
+        if (!PciHandleType::exists(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM)) {
+            cerr << "No access to PCICFG\n" << endl;
+            return false;
+        }
+        uint64 cpubusno = 0;
+        struct iio_stacks_on_socket iio_on_socket;
+        iio_on_socket.socket_id = socket_id;
+        PciHandleType h(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM);
+        h.read64(ROOT_BUSES_OFFSET, &cpubusno);
+
+        iio_on_socket.stacks.reserve(6);
+        for (int stack_id = 0; stack_id < 6; stack_id++) {
+            struct iio_stack stack;
+            stack.iio_unit_id = stack_id;
+            stack.busno = (uint8_t)(cpubusno >> (stack_id * SKX_BUS_NUM_STRIDE));
+            stack.stack_name = skx_iio_stack_names[stack_id];
+            for (uint8_t part_id = 0; part_id < 4; part_id++) {
+                struct iio_bifurcated_part part;
+                part.part_id = part_id;
+                struct pci *pci = &part.root_pci_dev;
+                struct bdf *bdf = &pci->bdf;
+                bdf->busno = stack.busno;
+                bdf->devno = part_id;
+                bdf->funcno = 0;
+                /* This is a workaround to catch some IIO stack does not exist */
+                if (stack_id != 0 && stack.busno == 0) {
+                    pci->exist = false;
+                }
+                else if (probe_pci(pci)) {
+                    /* FIXME: for 0:0.0, we may need to scan from secondary switch down; lgtm [cpp/fixme-comment] */
+                    for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) {
+                        for (uint8_t device = 0; device < 32; device++) {
+                            for (uint8_t function = 0; function < 8; function++) {
+                                struct pci child_pci_dev;
+                                child_pci_dev.bdf.busno = bus;
+                                child_pci_dev.bdf.devno = device;
+                                child_pci_dev.bdf.funcno = function;
+                                if (probe_pci(&child_pci_dev)) {
+                                    part.child_pci_devs.push_back(child_pci_dev);
+                                }
+                            }
+                        }
+                    }
+                }
+                stack.parts.push_back(part);
+            }
+
+            iio_on_socket.stacks.push_back(stack);
+        }
+        iios.push_back(iio_on_socket);
+    }
+
+    return true;
+}
+
+class IPlatformMapping10Nm: public IPlatformMapping {
+private:
+public:
+    IPlatformMapping10Nm(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets) {}
+    ~IPlatformMapping10Nm() = default;
+    bool getSadIdRootBusMap(uint32_t socket_id, std::map<uint8_t, uint8_t>& sad_id_bus_map);
+};
+
+bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map<uint8_t, uint8_t>& sad_id_bus_map)
+{
+    for (uint16_t bus = 0; bus < 256; bus++) {
+        for (uint8_t device = 0; device < 32; device++) {
+            for (uint8_t function = 0; function < 8; function++) {
+                struct pci pci_dev;
+                pci_dev.bdf.busno = (uint8_t)bus;
+                pci_dev.bdf.devno = device;
+                pci_dev.bdf.funcno = function;
+                if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SNR_ICX_MESH2IIO_MMAP_DID)) {
+
+                    PciHandleType h(0, bus, device, function);
+                    std::uint32_t sad_ctrl_cfg;
+                    h.read32(SNR_ICX_SAD_CONTROL_CFG_OFFSET, &sad_ctrl_cfg);
+                    if (sad_ctrl_cfg == (std::numeric_limits<uint32_t>::max)()) {
+                        cerr << "Could not read SAD_CONTROL_CFG" << endl;
+                        return false;
+                    }
+
+                    if ((sad_ctrl_cfg & 0xf) == socket_id) {
+                        uint8_t sid = (sad_ctrl_cfg >> 4) & 0x7;
+                        sad_id_bus_map.insert(std::pair<uint8_t, uint8_t>(sid, (uint8_t)bus));
+                    }
+                }
+            }
+        }
+    }
+
+    if (sad_id_bus_map.empty()) {
+        cerr << "Could not find Root Port bus numbers" << endl;
+        return false;
+    }
+
+    return true;
+}
+
+// Mapping for IceLake Server.
+class WhitleyPlatformMapping: public IPlatformMapping10Nm {
+private:
+    const bool icx_d;
+    const std::map<int, int>& sad_to_pmu_id_mapping;
+    const std::string * iio_stack_names;
+
+    const std::string icx_iio_stack_names[6] = {
+        "IIO Stack 0 - PCIe0          ",
+        "IIO Stack 1 - PCIe1          ",
+        "IIO Stack 2 - MCP            ",
+        "IIO Stack 3 - PCIe2          ",
+        "IIO Stack 4 - PCIe3          ",
+        "IIO Stack 5 - CBDMA/DMI      "
+    };
+
+    const std::string icx_d_iio_stack_names[6] = {
+        "IIO Stack 0 - MCP            ",
+        "IIO Stack 1 - PCIe0          ",
+        "IIO Stack 2 - CBDMA/DMI      ",
+        "IIO Stack 3 - PCIe2          ",
+        "IIO Stack 4 - PCIe3          ",
+        "IIO Stack 5 - PCIe1          "
+    };
+
+    const std::map<int, int> icx_sad_to_pmu_id_mapping = {
+        { ICX_CBDMA_DMI_SAD_ID, 5 },
+        { 1,                    0 },
+        { 2,                    1 },
+        { ICX_MCP_SAD_ID,       2 },
+        { 4,                    3 },
+        { 5,                    4 }
+    };
+
+    const std::map<int, int> icx_d_sad_to_pmu_id_mapping = {
+        { ICX_CBDMA_DMI_SAD_ID, 2 },
+        { 1,                    5 },
+        { 2,                    1 },
+        { ICX_MCP_SAD_ID,       0 },
+        { 4,                    3 },
+        { 5,                    4 }
+    };
+protected:
+    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    WhitleyPlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets),
+        icx_d(model == PCM::ICX_D),
+        sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping),
+        iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names)
+    {
+    }
+    ~WhitleyPlatformMapping() = default;
+};
+
+bool WhitleyPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    for (uint32_t socket = 0; socket < socketsCount(); socket++) {
+        struct iio_stacks_on_socket iio_on_socket;
+        iio_on_socket.socket_id = socket;
+        std::map<uint8_t, uint8_t> sad_id_bus_map;
+        if (!getSadIdRootBusMap(socket, sad_id_bus_map)) {
+            return false;
+        }
+
+        {
+            struct iio_stack stack;
+            stack.iio_unit_id = sad_to_pmu_id_mapping.at(ICX_MCP_SAD_ID);
+            stack.stack_name = iio_stack_names[stack.iio_unit_id];
+            iio_on_socket.stacks.push_back(stack);
+        }
+
+        for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) {
+            int sad_id = sad_id_bus_pair->first;
+            if (sad_to_pmu_id_mapping.find(sad_id) ==
+                sad_to_pmu_id_mapping.end()) {
+                cerr << "Unknown SAD ID: " << sad_id << endl;
+                return false;
+            }
+
+            if (sad_id == ICX_MCP_SAD_ID) {
+                continue;
+            }
+
+            struct iio_stack stack;
+            int root_bus = sad_id_bus_pair->second;
+            if (sad_id == ICX_CBDMA_DMI_SAD_ID) {
+                // There is one DMA Controller on each socket
+                stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id);
+                stack.busno = root_bus;
+                stack.stack_name = iio_stack_names[stack.iio_unit_id];
+
+                // PCH is on socket 0 only
+                if (socket == 0) {
+                    struct iio_bifurcated_part pch_part;
+                    struct pci *pci = &pch_part.root_pci_dev;
+                    struct bdf *bdf = &pci->bdf;
+                    pch_part.part_id = ICX_PCH_PART_ID;
+                    bdf->busno = root_bus;
+                    bdf->devno = 0x00;
+                    bdf->funcno = 0x00;
+                    if (probe_pci(pci)) {
+                        // Probe child devices only under PCH part.
+                        for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) {
+                            for (uint8_t device = 0; device < 32; device++) {
+                                for (uint8_t function = 0; function < 8; function++) {
+                                    struct pci child_pci_dev;
+                                    child_pci_dev.bdf.busno = bus;
+                                    child_pci_dev.bdf.devno = device;
+                                    child_pci_dev.bdf.funcno = function;
+                                    if (probe_pci(&child_pci_dev)) {
+                                        pch_part.child_pci_devs.push_back(child_pci_dev);
+                                    }
+                                }
+                            }
+                        }
+                        stack.parts.push_back(pch_part);
+                    }
+                }
+
+                struct iio_bifurcated_part part;
+                part.part_id = ICX_CBDMA_PART_ID;
+                struct pci *pci = &part.root_pci_dev;
+                struct bdf *bdf = &pci->bdf;
+                bdf->busno = root_bus;
+                bdf->devno = 0x01;
+                bdf->funcno = 0x00;
+                if (probe_pci(pci))
+                    stack.parts.push_back(part);
+
+                iio_on_socket.stacks.push_back(stack);
+                continue;
+            }
+            stack.busno = root_bus;
+            stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id);
+            stack.stack_name = iio_stack_names[stack.iio_unit_id];
+            for (int slot = 2; slot < 6; slot++) {
+                struct pci pci;
+                pci.bdf.busno = root_bus;
+                pci.bdf.devno = slot;
+                pci.bdf.funcno = 0x00;
+                if (!probe_pci(&pci)) {
+                    continue;
+                }
+                struct iio_bifurcated_part part;
+                part.part_id = slot - 2;
+                part.root_pci_dev = pci;
+
+                for (uint8_t bus = pci.secondary_bus_number; bus <= pci.subordinate_bus_number; bus++) {
+                    for (uint8_t device = 0; device < 32; device++) {
+                        for (uint8_t function = 0; function < 8; function++) {
+                            struct pci child_pci_dev;
+                            child_pci_dev.bdf.busno = bus;
+                            child_pci_dev.bdf.devno = device;
+                            child_pci_dev.bdf.funcno = function;
+                            if (probe_pci(&child_pci_dev)) {
+                                part.child_pci_devs.push_back(child_pci_dev);
+                            }
+                        }
+                    }
+                }
+                stack.parts.push_back(part);
+            }
+            iio_on_socket.stacks.push_back(stack);
+        }
+        std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
+        iios.push_back(iio_on_socket);
+    }
+    return true;
+}
+
+// Mapping for Snowridge.
+class JacobsvillePlatformMapping: public IPlatformMapping10Nm {
+private:
+    const std::map<int, int> snr_sad_to_pmu_id_mapping = {
+        { SNR_CBDMA_DMI_SAD_ID, 1 },
+        { SNR_PCIE_GEN3_SAD_ID, 4 },
+        { SNR_HQM_SAD_ID      , 3 },
+        { SNR_NIS_SAD_ID      , 2 },
+        { SNR_QAT_SAD_ID      , 0 }
+    };
+
+    const std::string snr_iio_stack_names[5] = {
+        "IIO Stack 0 - QAT            ",
+        "IIO Stack 1 - CBDMA/DMI      ",
+        "IIO Stack 2 - NIS            ",
+        "IIO Stack 3 - HQM            ",
+        "IIO Stack 4 - PCIe           "
+    };
+protected:
+    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    JacobsvillePlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {}
+    ~JacobsvillePlatformMapping() = default;
+    bool JacobsvilleAccelerators(const std::pair<uint8_t, uint8_t>& sad_id_bus_pair, struct iio_stack& stack);
+};
+
+bool JacobsvillePlatformMapping::JacobsvilleAccelerators(const std::pair<uint8_t, uint8_t>& sad_id_bus_pair, struct iio_stack& stack)
+{
+    uint16_t expected_dev_id;
+    auto sad_id = sad_id_bus_pair.first;
+    switch (sad_id) {
+    case SNR_HQM_SAD_ID:
+        expected_dev_id = HQM_DID;
+        break;
+    case SNR_NIS_SAD_ID:
+        expected_dev_id = NIS_DID;
+        break;
+    case SNR_QAT_SAD_ID:
+        expected_dev_id = QAT_DID;
+        break;
+    default:
+        return false;
+    }
+    stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id);
+    stack.stack_name = snr_iio_stack_names[stack.iio_unit_id];
+    for (uint16_t bus = sad_id_bus_pair.second; bus < 256; bus++) {
+        for (uint8_t device = 0; device < 32; device++) {
+            for (uint8_t function = 0; function < 8; function++) {
+                struct pci pci_dev;
+                pci_dev.bdf.busno = (uint8_t)bus;
+                pci_dev.bdf.devno = device;
+                pci_dev.bdf.funcno = function;
+                if (probe_pci(&pci_dev)) {
+                    if (expected_dev_id == pci_dev.device_id) {
+                        struct iio_bifurcated_part part;
+                        part.part_id = SNR_ACCELERATOR_PART_ID;
+                        part.root_pci_dev = pci_dev;
+                        stack.busno = (uint8_t)bus;
+                        stack.parts.push_back(part);
+                        return true;
+                    }
+                }
+            }
+        }
+    }
+    return false;
+}
+
+bool JacobsvillePlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    std::map<uint8_t, uint8_t> sad_id_bus_map;
+    if (!getSadIdRootBusMap(0, sad_id_bus_map)) {
+        return false;
+    }
+    struct iio_stacks_on_socket iio_on_socket;
+    iio_on_socket.socket_id = 0;
+    if (sad_id_bus_map.size() != snr_sad_to_pmu_id_mapping.size()) {
+        cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << snr_sad_to_pmu_id_mapping.size() << endl;
+        return false;
+    }
+
+    for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) {
+        int sad_id = sad_id_bus_pair->first;
+        struct iio_stack stack;
+        switch (sad_id) {
+        case SNR_CBDMA_DMI_SAD_ID:
+            {
+                int root_bus = sad_id_bus_pair->second;
+                stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id);
+                stack.stack_name = snr_iio_stack_names[stack.iio_unit_id];
+                stack.busno = root_bus;
+                // DMA Controller
+                struct iio_bifurcated_part part;
+                part.part_id = 0;
+                struct pci pci_dev;
+                pci_dev.bdf.busno = root_bus;
+                pci_dev.bdf.devno = 0x01;
+                pci_dev.bdf.funcno = 0x00;
+                if (probe_pci(&pci_dev)) {
+                    part.root_pci_dev = pci_dev;
+                    stack.parts.push_back(part);
+                }
+
+                part.part_id = 4;
+                pci_dev.bdf.busno = root_bus;
+                pci_dev.bdf.devno = 0x00;
+                pci_dev.bdf.funcno = 0x00;
+                if (probe_pci(&pci_dev)) {
+                    for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
+                        for (uint8_t device = 0; device < 32; device++) {
+                            for (uint8_t function = 0; function < 8; function++) {
+                                struct pci child_pci_dev;
+                                child_pci_dev.bdf.busno = bus;
+                                child_pci_dev.bdf.devno = device;
+                                child_pci_dev.bdf.funcno = function;
+                                if (probe_pci(&child_pci_dev)) {
+                                    part.child_pci_devs.push_back(child_pci_dev);
+                                }
+                            }
+                        }
+                    }
+                    part.root_pci_dev = pci_dev;
+                    stack.parts.push_back(part);
+                }
+            }
+            break;
+        case SNR_PCIE_GEN3_SAD_ID:
+            {
+                int root_bus = sad_id_bus_pair->second;
+                stack.busno = root_bus;
+                stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id);
+                stack.stack_name = snr_iio_stack_names[stack.iio_unit_id];
+                for (int slot = 4; slot < 8; slot++) {
+                    struct pci pci_dev;
+                    pci_dev.bdf.busno = root_bus;
+                    pci_dev.bdf.devno = slot;
+                    pci_dev.bdf.funcno = 0x00;
+                    if (!probe_pci(&pci_dev)) {
+                        continue;
+                    }
+                    int part_id = 4 + pci_dev.device_id - SNR_ROOT_PORT_A_DID;
+                    if ((part_id < 0) || (part_id > 4)) {
+                        cerr << "Invalid part ID " << part_id << endl;
+                        return false;
+                    }
+                    struct iio_bifurcated_part part;
+                    part.part_id = part_id;
+                    part.root_pci_dev = pci_dev;
+                    for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
+                        for (uint8_t device = 0; device < 32; device++) {
+                            for (uint8_t function = 0; function < 8; function++) {
+                                struct pci child_pci_dev;
+                                child_pci_dev.bdf.busno = bus;
+                                child_pci_dev.bdf.devno = device;
+                                child_pci_dev.bdf.funcno = function;
+                                if (probe_pci(&child_pci_dev)) {
+                                    part.child_pci_devs.push_back(child_pci_dev);
+                                }
+                            }
+                        }
+                    }
+                    stack.parts.push_back(part);
+                }
+            }
+            break;
+        case SNR_HQM_SAD_ID:
+        case SNR_NIS_SAD_ID:
+        case SNR_QAT_SAD_ID:
+            JacobsvilleAccelerators(*sad_id_bus_pair, stack);
+            break;
+        default:
+            cerr << "Unknown SAD ID: " << sad_id << endl;
+            return false;
+        }
+        iio_on_socket.stacks.push_back(stack);
+    }
+
+    std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
+
+    iios.push_back(iio_on_socket);
+
+    return true;
+}
+
+class EagleStreamPlatformMapping: public IPlatformMapping
+{
+private:
+    bool getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses);
+    bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
+    bool eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
+    bool eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
+    bool eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
+    bool isDmiStack(int unit);
+    bool isPcieStack(int unit);
+    bool isDinoStack(int unit);
+    std::uint32_t m_chop;
+
+    enum class EagleStreamSupportedTypes
+    {
+        esInvalid = -1,
+        esSprXcc,
+        esSprMcc,
+        esEmrXcc
+    };
+
+    typedef EagleStreamSupportedTypes estype;
+    EagleStreamSupportedTypes m_es_type;
+
+    const std::map<int, int> spr_xcc_sad_to_pmu_id_mapping = {
+        { 0,  SPR_XCC_DMI_PMON_ID         },
+        { 1,  SPR_XCC_PCIE_GEN5_0_PMON_ID },
+        { 2,  SPR_XCC_PCIE_GEN5_1_PMON_ID },
+        { 3,  SPR_XCC_PCIE_GEN5_2_PMON_ID },
+        { 4,  SPR_XCC_PCIE_GEN5_3_PMON_ID },
+        { 5,  SPR_XCC_PCIE_GEN5_4_PMON_ID },
+        { 8,  SPR_XCC_IDX0_PMON_ID        },
+        { 9,  SPR_XCC_IDX1_PMON_ID        },
+        { 10, SPR_XCC_IDX2_PMON_ID        },
+        { 11, SPR_XCC_IDX3_PMON_ID        }
+    };
+
+    const std::map<int, int> spr_mcc_sad_to_pmu_id_mapping = {
+        { 0, SPR_MCC_PCIE_GEN5_0_PMON_ID },
+        { 1, SPR_MCC_PCIE_GEN5_1_PMON_ID },
+        { 2, SPR_MCC_PCIE_GEN5_2_PMON_ID },
+        { 3, SPR_MCC_DMI_PMON_ID         },
+        { 4, SPR_MCC_PCIE_GEN5_3_PMON_ID },
+        { 5, SPR_MCC_PCIE_GEN5_4_PMON_ID },
+        { 8, SPR_MCC_IDX0_PMON_ID        },
+    };
+
+    const std::string spr_xcc_iio_stack_names[12] = {
+        "IIO Stack 0 - IDX0  ",
+        "IIO Stack 1 - DMI   ",
+        "IIO Stack 2 - PCIe0 ",
+        "IIO Stack 3 - IDX1  ",
+        "IIO Stack 4 - PCIe1 ",
+        "IIO Stack 5 - IDX2  ",
+        "IIO Stack 6 - PCIe2 ",
+        "IIO Stack 7  - PCIe3",
+        "IIO Stack 8  - IDX3 ",
+        "IIO Stack 9  - PCIe4",
+        "IIO Stack 10 - NONE ",
+        "IIO Stack 11 - NONE ",
+    };
+
+    /*
+    * SPR MCC has 7 I/O stacks but PMON block for DMI has ID number 10.
+    * And just to follow such enumeration keep Stack 10 for DMI.
+    */
+    const std::string spr_mcc_iio_stack_names[11] = {
+        "IIO Stack 0 - PCIe0 ",
+        "IIO Stack 1 - PCIe1 ",
+        "IIO Stack 2 - PCIe2 ",
+        "IIO Stack 3 - IDX0  ",
+        "IIO Stack 4 - PCIe3 ",
+        "IIO Stack 5 - PCIe4 ",
+        "IIO Stack 6 - NONE  ",
+        "IIO Stack 7 - NONE  ",
+        "IIO Stack 8 - NONE  ",
+        "IIO Stack 9 - NONE  ",
+        "IIO Stack 10 - DMI  ",
+    };
+
+    const std::map<int, int> emr_sad_to_pmu_id_mapping = {
+        { 0,  EMR_DMI_PMON_ID         },
+        { 1,  EMR_PCIE_GEN5_0_PMON_ID },
+        { 2,  EMR_PCIE_GEN5_1_PMON_ID },
+        { 3,  EMR_PCIE_GEN5_2_PMON_ID },
+        { 4,  EMR_PCIE_GEN5_3_PMON_ID },
+        { 5,  EMR_PCIE_GEN5_4_PMON_ID },
+        { 8,  EMR_IDX0_PMON_ID        },
+        { 9,  EMR_IDX1_PMON_ID        },
+        { 10, EMR_IDX2_PMON_ID        },
+        { 11, EMR_IDX3_PMON_ID        }
+    };
+
+    const std::string emr_iio_stack_names[12] = {
+        "IIO Stack 0 - IDX0  ",
+        "IIO Stack 1 - PCIe3 ",
+        "IIO Stack 2 - PCIe0 ",
+        "IIO Stack 3 - IDX1  ",
+        "IIO Stack 4 - PCIe1 ",
+        "IIO Stack 5 - IDX2  ",
+        "IIO Stack 6 - PCIe2 ",
+        "IIO Stack 7  - DMI",
+        "IIO Stack 8  - IDX3 ",
+        "IIO Stack 9  - PCIe4",
+        "IIO Stack 10 - NONE ",
+        "IIO Stack 11 - NONE ",
+    };
+
+    enum EagleStreamPlatformStacks
+    {
+        esDMI = 0,
+        esPCIe0,
+        esPCIe1,
+        esPCIe2,
+        esPCIe3,
+        esPCIe4,
+        esDINO0,
+        esDINO1,
+        esDINO2,
+        esDINO3,
+        esEndOfList
+    };
+
+    const std::vector<int> spr_xcc_stacks_enumeration = {
+        /* esDMI   */ SPR_XCC_DMI_PMON_ID,
+        /* esPCIe0 */ SPR_XCC_PCIE_GEN5_0_PMON_ID,
+        /* esPCIe1 */ SPR_XCC_PCIE_GEN5_1_PMON_ID,
+        /* esPCIe2 */ SPR_XCC_PCIE_GEN5_2_PMON_ID,
+        /* esPCIe3 */ SPR_XCC_PCIE_GEN5_3_PMON_ID,
+        /* esPCIe4 */ SPR_XCC_PCIE_GEN5_4_PMON_ID,
+        /* esDINO0 */ SPR_XCC_IDX0_PMON_ID,
+        /* esDINO1 */ SPR_XCC_IDX1_PMON_ID,
+        /* esDINO2 */ SPR_XCC_IDX2_PMON_ID,
+        /* esDINO3 */ SPR_XCC_IDX3_PMON_ID,
+    };
+
+    const std::vector<int> spr_mcc_stacks_enumeration = {
+        /* esDMI   */ SPR_MCC_DMI_PMON_ID,
+        /* esPCIe0 */ SPR_MCC_PCIE_GEN5_0_PMON_ID,
+        /* esPCIe1 */ SPR_MCC_PCIE_GEN5_1_PMON_ID,
+        /* esPCIe2 */ SPR_MCC_PCIE_GEN5_2_PMON_ID,
+        /* esPCIe3 */ SPR_MCC_PCIE_GEN5_3_PMON_ID,
+        /* esPCIe4 */ SPR_MCC_PCIE_GEN5_4_PMON_ID,
+        /* esDINO0 */ SPR_MCC_IDX0_PMON_ID,
+    };
+
+    const std::vector<int> emr_stacks_enumeration = {
+        /* esDMI   */ EMR_DMI_PMON_ID,
+        /* esPCIe0 */ EMR_PCIE_GEN5_0_PMON_ID,
+        /* esPCIe1 */ EMR_PCIE_GEN5_1_PMON_ID,
+        /* esPCIe2 */ EMR_PCIE_GEN5_2_PMON_ID,
+        /* esPCIe3 */ EMR_PCIE_GEN5_3_PMON_ID,
+        /* esPCIe4 */ EMR_PCIE_GEN5_4_PMON_ID,
+        /* esDINO0 */ EMR_IDX0_PMON_ID,
+        /* esDINO1 */ EMR_IDX1_PMON_ID,
+        /* esDINO2 */ EMR_IDX2_PMON_ID,
+        /* esDINO3 */ EMR_IDX3_PMON_ID,
+    };
+
+    const std::map<estype, std::vector<int>> es_stacks_enumeration = {
+        {estype::esSprXcc, spr_xcc_stacks_enumeration},
+        {estype::esSprMcc, spr_mcc_stacks_enumeration},
+        {estype::esEmrXcc, emr_stacks_enumeration    },
+    };
+
+    const std::map<estype, const std::string *> es_stack_names = {
+        {estype::esSprXcc, spr_xcc_iio_stack_names},
+        {estype::esSprMcc, spr_mcc_iio_stack_names},
+        {estype::esEmrXcc, emr_iio_stack_names    },
+    };
+
+    const std::map<estype, std::map<int, int>> es_sad_to_pmu_id_mapping = {
+        {estype::esSprXcc, spr_xcc_sad_to_pmu_id_mapping},
+        {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping},
+        {estype::esEmrXcc, emr_sad_to_pmu_id_mapping    },
+    };
+protected:
+    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    EagleStreamPlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets), m_chop(0), m_es_type(estype::esInvalid) {}
+    ~EagleStreamPlatformMapping() = default;
+    bool setChopValue();
+    bool isXccPlatform() const { return m_chop == kXccChop; }
+
+    const std::uint32_t kXccChop = 0b11;
+    const std::uint32_t kMccChop = 0b01;
+};
+
+bool EagleStreamPlatformMapping::setChopValue()
+{
+    for (uint16_t b = 0; b < 256; b++) {
+        struct pci pci_dev(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION);
+        if (!(probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SPR_PCU_CR3_DID))) {
+            continue;
+        }
+
+        std::uint32_t capid4;
+        PciHandleType h(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION);
+        h.read32(SPR_CAPID4_OFFSET, &capid4);
+        if (capid4 == (std::numeric_limits<std::uint32_t>::max)()) {
+            std::cerr << "Cannot read PCU RC3 register" << std::endl;
+            return false;
+        }
+        capid4 = SPR_CAPID4_GET_PHYSICAL_CHOP(capid4);
+        if (capid4 == kXccChop || capid4 == kMccChop) {
+            m_chop = capid4;
+            m_es_type = cpuId() == PCM::SPR ? (m_chop == kXccChop ? estype::esSprXcc : estype::esSprMcc) : estype::esEmrXcc;
+        }
+        else {
+            std::cerr << "Unknown chop value " << capid4 << std::endl;
+            return false;
+        }
+        return true;
+    }
+    std::cerr << "Cannot find PCU RC3 registers on the system. Device ID is " << std::hex << SPR_PCU_CR3_DID << std::dec << std::endl;
+    return false;
+}
+
+bool EagleStreamPlatformMapping::getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses)
+{
+    bool mapped = true;
+    for (uint32_t domain = 0; mapped; domain++) {
+        mapped = false;
+        for (uint16_t b = 0; b < 256; b++) {
+            for (uint8_t d = 0; d < 32; d++) {
+                for (uint8_t f = 0; f < 8; f++) {
+                    struct pci pci_dev(domain, b, d, f);
+                    if (!probe_pci(&pci_dev)) {
+                        break;
+                    }
+                    if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) {
+                        continue;
+                    }
+
+                    std::uint32_t cpuBusValid;
+                    std::vector<std::uint32_t> cpuBusNo;
+                    int package_id;
+
+                    if (get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id) == false)
+                    {
+                        return false;
+                    }
+
+                    const auto& sad_to_pmu_id_mapping = es_sad_to_pmu_id_mapping.at(m_es_type);
+                    for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) {
+                        if (!((cpuBusValid >> cpuBusId) & 0x1))
+                        {
+                            cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl;
+                            continue;
+                        }
+                        if (sad_to_pmu_id_mapping.find(cpuBusId) == sad_to_pmu_id_mapping.end())
+                        {
+                            cerr << "Cannot map CPU bus " << cpuBusId << " to IO PMU ID" << endl;
+                            continue;
+                        }
+                        int pmuId = sad_to_pmu_id_mapping.at(cpuBusId);
+                        int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff;
+                        root_buses[package_id][pmuId] = bdf(domain, rootBus, 0, 0);
+                        cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ") to IO PMU #"
+                             << pmuId << " package " << package_id << endl;
+                        mapped = true;
+                    }
+                }
+            }
+        }
+    }
+    return !root_buses.empty();
+}
+
+bool EagleStreamPlatformMapping::eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    struct iio_stack stack;
+    stack.iio_unit_id = unit;
+    stack.stack_name = es_stack_names.at(m_es_type)[unit];
+    stack.busno = address.busno;
+    stack.domain = address.domainno;
+    struct iio_bifurcated_part pch_part;
+    struct pci *pci = &pch_part.root_pci_dev;
+    auto dmi_part_id = SPR_DMI_PART_ID;
+    pch_part.part_id = dmi_part_id;
+    pci->bdf = address;
+    if (!probe_pci(pci)) {
+        cerr << "Failed to probe DMI Stack: address: " << std::setw(4) << std::setfill('0') << std::hex << address.domainno <<
+                                                          std::setw(2) << std::setfill('0') << ":" << address.busno << ":" << address.devno <<
+                                                          "." << address.funcno << std::dec << endl;
+        return false;
+    }
+
+    /* Scan devices behind PCH port only */
+    if (!iio_on_socket.socket_id)
+        probeDeviceRange(pch_part.child_pci_devs, pci->bdf.domainno, pci->secondary_bus_number, pci->subordinate_bus_number);
+
+    pci->parts_no.push_back(dmi_part_id);
+
+    stack.parts.push_back(pch_part);
+    iio_on_socket.stacks.push_back(stack);
+    return true;
+}
+
+bool EagleStreamPlatformMapping::eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    /*
+     * Stacks that manage PCIe 4.0 (device 2,4,6,8) and 5.0 (device 1,3,5,7) Root Ports.
+     */
+    struct iio_stack stack;
+    stack.domain = address.domainno;
+    stack.busno = address.busno;
+    stack.iio_unit_id = unit;
+    stack.stack_name = es_stack_names.at(m_es_type)[unit];
+    for (int slot = 1; slot < 9; ++slot)
+    {
+        // Check if port is enabled
+        struct pci root_pci_dev;
+        root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0);
+        if (probe_pci(&root_pci_dev))
+        {
+            struct iio_bifurcated_part part;
+            // Bifurcated Root Ports to channel mapping on SPR
+            part.part_id = slot - 1;
+            part.root_pci_dev = root_pci_dev;
+            for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) {
+                for (uint8_t d = 0; d < 32; ++d) {
+                    for (uint8_t f = 0; f < 8; ++f) {
+                        struct pci child_pci_dev(address.domainno, b, d, f);
+                        if (probe_pci(&child_pci_dev)) {
+                            child_pci_dev.parts_no.push_back(part.part_id);
+                            part.child_pci_devs.push_back(child_pci_dev);
+                        }
+                    }
+                }
+            }
+            stack.parts.push_back(part);
+        }
+    }
+    iio_on_socket.stacks.push_back(stack);
+    return true;
+}
+
+bool EagleStreamPlatformMapping::eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    struct iio_stack stack;
+    stack.iio_unit_id = unit;
+    stack.domain = address.domainno;
+    stack.busno = address.busno;
+
+    // Channel mappings are checked on B0 stepping
+    auto rb = address.busno;
+    const std::vector<int> acceleratorBuses{ rb, rb + 1, rb + 2, rb + 3 };
+    stack.stack_name = es_stack_names.at(m_es_type)[unit];
+    for (auto& b : acceleratorBuses) {
+        for (auto d = 0; d < 32; ++d) {
+            for (auto f = 0; f < 8; ++f) {
+                struct iio_bifurcated_part part;
+                struct pci pci_dev(address.domainno, b, d, f);
+
+                if (probe_pci(&pci_dev)) {
+                    if (pci_dev.isIntelDevice()) {
+                        switch (pci_dev.device_id) {
+                        case DSA_DID:
+                            pci_dev.parts_no.push_back(0);
+                            pci_dev.parts_no.push_back(1);
+                            pci_dev.parts_no.push_back(2);
+                            break;
+                        case IAX_DID:
+                            pci_dev.parts_no.push_back(0);
+                            pci_dev.parts_no.push_back(1);
+                            pci_dev.parts_no.push_back(2);
+                            break;
+                        case HQMV2_DID:
+                            pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_HQM_PART_ID : SPR_MCC_HQM_PART_ID);
+                            break;
+                        case QATV2_DID:
+                            pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_QAT_PART_ID : SPR_MCC_QAT_PART_ID);
+                            break;
+                        default:
+                            continue;
+                        }
+                        part.child_pci_devs.push_back(pci_dev);
+                    }
+                    stack.parts.push_back(part);
+                }
+            }
+        }
+    }
+
+    iio_on_socket.stacks.push_back(stack);
+    return true;
+}
+
+bool EagleStreamPlatformMapping::isDmiStack(int unit)
+{
+    const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type);
+
+    return stacks_enumeration[esDMI] == unit;
+}
+
+bool EagleStreamPlatformMapping::isPcieStack(int unit)
+{
+    const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type);
+
+    return stacks_enumeration[esPCIe0] == unit || stacks_enumeration[esPCIe1] == unit ||
+           stacks_enumeration[esPCIe2] == unit || stacks_enumeration[esPCIe3] == unit ||
+           stacks_enumeration[esPCIe4] == unit;
+}
+
+bool EagleStreamPlatformMapping::isDinoStack(int unit)
+{
+    const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type);
+
+    return stacks_enumeration[esDINO0] == unit || stacks_enumeration[esDINO1] == unit ||
+           stacks_enumeration[esDINO2] == unit || stacks_enumeration[esDINO3] == unit;
+}
+
+bool EagleStreamPlatformMapping::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    if (isDmiStack(unit)) {
+        return eagleStreamDmiStackProbe(unit, address, iio_on_socket);
+    }
+    else if (isPcieStack(unit)) {
+        return eagleStreamPciStackProbe(unit, address, iio_on_socket);
+    }
+    else if (isDinoStack(unit)) {
+        return eagleStreamAcceleratorStackProbe(unit, address, iio_on_socket);
+    }
+
+    return false;
+}
+
+bool EagleStreamPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    if (!setChopValue()) return false;
+
+    std::map<int, std::map<int, struct bdf>> root_buses;
+    if (!getRootBuses(root_buses))
+    {
+        return false;
+    }
+
+    for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) {
+        auto rbs_on_socket = iter->second;
+        struct iio_stacks_on_socket iio_on_socket;
+        iio_on_socket.socket_id = iter->first;
+        for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) {
+            if (!stackProbe(rb->first, rb->second, iio_on_socket)) {
+                return false;
+            }
+        }
+        std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
+        iios.push_back(iio_on_socket);
+    }
+
+    return true;
+}
+
+class LoganvillePlatform: public IPlatformMapping10Nm {
+private:
+    bool loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id);
+    bool loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id);
+    bool loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id);
+
+    const std::string grr_iio_stack_names[3] = {
+        "IIO Stack 0 - NIS/QAT        ",
+        "IIO Stack 1 - HQM            ",
+        "IIO Stack 2 - PCH/DSA/PCIe   "
+    };
+
+    // Stack 0 contains PCH, DSA and CPU PCIe Gen4 Complex
+    const std::map<int, int> grr_sad_to_pmu_id_mapping = {
+        { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID },
+        { GRR_DLB_SAD_ID,          GRR_DLB_PMON_ID          },
+        { GRR_NIS_QAT_SAD_ID,      GRR_NIS_QAT_PMON_ID      },
+    };
+protected:
+    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    LoganvillePlatform(uint32_t model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {}
+    ~LoganvillePlatform() = default;
+};
+
+bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id)
+{
+    struct iio_stack stack;
+    stack.busno = root_bus;
+    stack.iio_unit_id = stack_pmon_id;
+    stack.stack_name = grr_iio_stack_names[stack_pmon_id];
+
+    struct iio_bifurcated_part pch_part;
+    pch_part.part_id = 7;
+    struct pci* pci_dev = &pch_part.root_pci_dev;
+    pci_dev->bdf.busno = root_bus;
+
+    if (probe_pci(pci_dev)) {
+        probeDeviceRange(pch_part.child_pci_devs, pci_dev->bdf.domainno, pci_dev->secondary_bus_number, pci_dev->subordinate_bus_number);
+        stack.parts.push_back(pch_part);
+        iio_on_socket.stacks.push_back(stack);
+        return true;
+    }
+
+    return false;
+}
+
+bool LoganvillePlatform::loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id)
+{
+    struct iio_stack stack;
+    stack.busno = root_bus;
+    stack.iio_unit_id = stack_pmon_id;
+    stack.stack_name = grr_iio_stack_names[stack_pmon_id];
+
+    struct iio_bifurcated_part dlb_part;
+    dlb_part.part_id = GRR_DLB_PART_ID;
+
+    for (uint8_t bus = root_bus; bus < 255; bus++) {
+        struct pci pci_dev(bus, 0x00, 0x00);
+        if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(HQMV25_DID)) {
+            dlb_part.root_pci_dev = pci_dev;
+            // Check Virtual RPs for DLB
+            for (uint8_t device = 0; device < 2; device++) {
+                for (uint8_t function = 0; function < 8; function++) {
+                    struct pci child_pci_dev(bus, device, function);
+                    if (probe_pci(&child_pci_dev)) {
+                        dlb_part.child_pci_devs.push_back(child_pci_dev);
+                    }
+                }
+            }
+            stack.parts.push_back(dlb_part);
+            iio_on_socket.stacks.push_back(stack);
+            return true;
+        }
+    }
+
+    return false;
+}
+
+bool LoganvillePlatform::loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id)
+{
+    struct iio_stack stack;
+    stack.busno = root_bus;
+    stack.iio_unit_id = stack_pmon_id;
+    stack.stack_name = grr_iio_stack_names[stack_pmon_id];
+
+    // Probe NIS
+    {
+        struct iio_bifurcated_part nis_part;
+        nis_part.part_id = GRR_NIS_PART_ID;
+        struct pci pci_dev(root_bus, 0x04, 0x00);
+        if (probe_pci(&pci_dev)) {
+            nis_part.root_pci_dev = pci_dev;
+            for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
+                for (uint8_t device = 0; device < 2; device++) {
+                    for (uint8_t function = 0; function < 8; function++) {
+                            struct pci child_pci_dev(bus, device, function);
+                            if (probe_pci(&child_pci_dev)) {
+                                nis_part.child_pci_devs.push_back(child_pci_dev);
+                            }
+                    }
+                }
+            }
+            stack.parts.push_back(nis_part);
+        }
+    }
+
+    // Probe QAT
+    {
+        struct iio_bifurcated_part qat_part;
+        qat_part.part_id = GRR_QAT_PART_ID;
+        struct pci pci_dev(root_bus, 0x05, 0x00);
+        if (probe_pci(&pci_dev)) {
+            qat_part.root_pci_dev = pci_dev;
+            for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) {
+                for (uint8_t device = 0; device < 17; device++) {
+                    for (uint8_t function = 0; function < 8; function++) {
+                            struct pci child_pci_dev(bus, device, function);
+                            if (probe_pci(&child_pci_dev)) {
+                                qat_part.child_pci_devs.push_back(child_pci_dev);
+                            }
+                    }
+                }
+            }
+            stack.parts.push_back(qat_part);
+        }
+    }
+
+    iio_on_socket.stacks.push_back(stack);
+    return true;
+}
+
+bool LoganvillePlatform::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    std::map<uint8_t, uint8_t> sad_id_bus_map;
+    if (!getSadIdRootBusMap(0, sad_id_bus_map)) {
+        return false;
+    }
+
+    if (sad_id_bus_map.size() != grr_sad_to_pmu_id_mapping.size()) {
+        cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << grr_sad_to_pmu_id_mapping.size() << endl;
+        return false;
+    }
+
+    struct iio_stacks_on_socket iio_on_socket;
+    iio_on_socket.socket_id = 0;
+
+    for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) {
+        if (grr_sad_to_pmu_id_mapping.find(sad_id_bus_pair->first) == grr_sad_to_pmu_id_mapping.end()) {
+            cerr << "Cannot map SAD ID to PMON ID. Unknown ID: " << sad_id_bus_pair->first << endl;
+            return false;
+        }
+        int stack_pmon_id = grr_sad_to_pmu_id_mapping.at(sad_id_bus_pair->first);
+        int root_bus = sad_id_bus_pair->second;
+        switch (stack_pmon_id) {
+        case GRR_PCH_DSA_GEN4_PMON_ID:
+            if (!loganvillePchDsaPciStackProbe(iio_on_socket, root_bus, stack_pmon_id)) {
+                return false;
+            }
+            break;
+        case GRR_DLB_PMON_ID:
+            if (!loganvilleDlbStackProbe(iio_on_socket, root_bus, stack_pmon_id)) {
+                return false;
+            }
+            break;
+        case GRR_NIS_QAT_PMON_ID:
+            if (!loganvilleNacStackProbe(iio_on_socket, root_bus, stack_pmon_id)) {
+                return false;
+            }
+            break;
+        default:
+            return false;
+        }
+    }
+
+    std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
+
+    iios.push_back(iio_on_socket);
+
+    return true;
+}
+
+class Xeon6thNextGenPlatform: public IPlatformMapping {
+private:
+    bool getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses);
+protected:
+    virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0;
+    virtual bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    Xeon6thNextGenPlatform(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets) {}
+    virtual ~Xeon6thNextGenPlatform() = default;
+};
+
+bool Xeon6thNextGenPlatform::getRootBuses(std::map<int, std::map<int, struct bdf>> &root_buses)
+{
+    bool mapped = true;
+    for (uint32_t domain = 0; mapped; domain++) {
+        mapped = false;
+        for (uint16_t b = 0; b < 256; b++) {
+            for (uint8_t d = 0; d < 32; d++) {
+                for (uint8_t f = 0; f < 8; f++) {
+                    struct pci pci_dev(domain, b, d, f);
+                    if (!probe_pci(&pci_dev)) {
+                        break;
+                    }
+                    if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) {
+                        continue;
+                    }
+
+                    std::uint32_t cpuBusValid;
+                    std::vector<std::uint32_t> cpuBusNo;
+                    int package_id;
+
+                    if (!get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id)) {
+                        return false;
+                    }
+
+                    for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) {
+                        if (!((cpuBusValid >> cpuBusId) & 0x1)) {
+                            cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl;
+                            continue;
+                        }
+                        int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff;
+                        root_buses[package_id][cpuBusId] = bdf(domain, rootBus, 0, 0);
+                        cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ")"
+                             << " package " << package_id << endl;
+                        mapped = true;
+                    }
+                }
+            }
+        }
+    }
+    return !root_buses.empty();
+}
+
+bool Xeon6thNextGenPlatform::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    std::map<int, std::map<int, struct bdf>> root_buses;
+    if (!getRootBuses(root_buses))
+    {
+        return false;
+    }
+
+    for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) {
+        auto rbs_on_socket = iter->second;
+        struct iio_stacks_on_socket iio_on_socket;
+        iio_on_socket.socket_id = iter->first;
+        for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) {
+            if (!stackProbe(rb->first, rb->second, iio_on_socket)) {
+                return false;
+            }
+        }
+        std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end());
+        iios.push_back(iio_on_socket);
+    }
+
+    return true;
+}
+
+class BirchStreamPlatform: public Xeon6thNextGenPlatform {
+private:
+    bool isPcieStack(int unit);
+    bool isRootHcStack(int unit);
+    bool isPartHcStack(int unit);
+    bool isUboxStack(int unit);
+
+    bool birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
+    bool birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket);
+
+    const std::string srf_iio_stack_names[15] = {
+        "IIO Stack 0  - PCIe6     ", // SRF_PE6_PMON_ID      0
+        "IIO Stack 1  - HCx0      ", // SRF_HC0_PMON_ID      1
+        "IIO Stack 2  - PCIe2     ", // SRF_PE2_PMON_ID      2
+        "IIO Stack 3  - PCIe0     ", // SRF_PE0_PMON_ID      3
+        "IIO Stack 4  - PCIe1     ", // SRF_PE1_PMON_ID      4
+        "IIO Stack 5  - PCIe3     ", // SRF_PE3_PMON_ID      5
+        "IIO Stack 6  - HCx1      ", // SRF_HC1_PMON_ID      6
+        "IIO Stack 7  - PCIe7     ", // SRF_PE7_PMON_ID      7
+        "IIO Stack 8  - PCIe8     ", // SRF_PE8_PMON_ID      8
+        "IIO Stack 9  - HCx3      ", // SRF_HC3_PMON_ID      9
+        "IIO Stack 10 - Flex PCIe5", // SRF_FLEX_PE5_PMON_ID 10
+        "IIO Stack 11 - PCIe4     ", // SRF_PE4_PMON_ID      11
+        "IIO Stack 12 - PCIe5     ", // SRF_PE5_PMON_ID      12
+        "IIO Stack 13 - Flex PCIe4", // SRF_FLEX_PE4_PMON_ID 13
+        "IIO Stack 14 - HCx2      ", // SRF_HC2_PMON_ID      14
+    };
+
+    const std::unordered_map<int, int> srf_sad_to_pmu_id_mapping = {
+        { SRF_PE0_SAD_BUS_ID,      SRF_PE0_PMON_ID      },
+        { SRF_PE1_SAD_BUS_ID,      SRF_PE1_PMON_ID      },
+        { SRF_PE2_SAD_BUS_ID,      SRF_PE2_PMON_ID      },
+        { SRF_PE3_SAD_BUS_ID,      SRF_PE3_PMON_ID      },
+        { SRF_PE4_SAD_BUS_ID,      SRF_PE4_PMON_ID      },
+        { SRF_FLEX_PE4_SAD_BUS_ID, SRF_FLEX_PE4_PMON_ID },
+        { SRF_PE5_SAD_BUS_ID,      SRF_PE5_PMON_ID      },
+        { SRF_FLEX_PE5_SAD_BUS_ID, SRF_FLEX_PE5_PMON_ID },
+        { SRF_PE6_SAD_BUS_ID,      SRF_PE6_PMON_ID      },
+        { SRF_PE7_SAD_BUS_ID,      SRF_PE7_PMON_ID      },
+        { SRF_PE8_SAD_BUS_ID,      SRF_PE8_PMON_ID      },
+        { SRF_HC0_SAD_BUS_ID,      SRF_HC0_PMON_ID      },
+        { SRF_HC1_SAD_BUS_ID,      SRF_HC1_PMON_ID      },
+        { SRF_HC2_SAD_BUS_ID,      SRF_HC2_PMON_ID      },
+        { SRF_HC3_SAD_BUS_ID,      SRF_HC3_PMON_ID      },
+    };
+
+    const std::unordered_set<int> srf_pcie_stacks = {
+        SRF_PE0_SAD_BUS_ID,
+        SRF_PE1_SAD_BUS_ID,
+        SRF_PE2_SAD_BUS_ID,
+        SRF_PE3_SAD_BUS_ID,
+        SRF_PE4_SAD_BUS_ID,
+        SRF_FLEX_PE4_SAD_BUS_ID,
+        SRF_PE5_SAD_BUS_ID,
+        SRF_FLEX_PE5_SAD_BUS_ID,
+        SRF_PE6_SAD_BUS_ID,
+        SRF_PE7_SAD_BUS_ID,
+        SRF_PE8_SAD_BUS_ID
+    };
+protected:
+    bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override;
+public:
+    BirchStreamPlatform(uint32_t model, uint32_t sockets) : Xeon6thNextGenPlatform(model, sockets) {}
+    ~BirchStreamPlatform() = default;
+};
+
+bool BirchStreamPlatform::birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    /*
+     * All stacks manage PCIe 5.0 Root Ports. Bifurcated Root Ports A-H appear as devices 2-9.
+     */
+    struct iio_stack stack;
+    stack.domain = address.domainno;
+    stack.busno = address.busno;
+    stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit);
+    stack.stack_name = srf_iio_stack_names[stack.iio_unit_id];
+    for (int slot = 2; slot < 9; ++slot)
+    {
+        struct pci root_pci_dev;
+        root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0);
+        if (probe_pci(&root_pci_dev))
+        {
+            struct iio_bifurcated_part part;
+            part.part_id = slot - 2;
+            part.root_pci_dev = root_pci_dev;
+            for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) {
+                for (uint8_t d = 0; d < 32; ++d) {
+                    for (uint8_t f = 0; f < 8; ++f) {
+                        struct pci child_pci_dev(address.domainno, b, d, f);
+                        if (probe_pci(&child_pci_dev)) {
+                            child_pci_dev.parts_no.push_back(part.part_id);
+                            part.child_pci_devs.push_back(child_pci_dev);
+                        }
+                    }
+                }
+            }
+            stack.parts.push_back(part);
+        }
+    }
+    iio_on_socket.stacks.push_back(stack);
+    return true;
+}
+
+bool BirchStreamPlatform::birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    struct iio_stack stack;
+    stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit);
+    stack.domain = address.domainno;
+    stack.busno = address.busno;
+    stack.stack_name = srf_iio_stack_names[stack.iio_unit_id];
+
+    /*
+     * Instance of DSA(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 1, function 0
+     * Instance of IAX(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 2, function 0
+     * Instance of QAT(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (9, 13, 21, 17), device 0, function 0
+     * Instance of HQM(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (10, 14, 22, 18), device 0, function 0
+     */
+    auto process_pci_dev = [](int domainno, int busno, int devno, int part_number, iio_bifurcated_part& part)
+    {
+        struct pci pci_dev(domainno, busno, devno, 0);
+        if (probe_pci(&pci_dev) && pci_dev.isIntelDevice()) {
+            part.part_id = part_number;
+            pci_dev.parts_no.push_back(part_number);
+            part.child_pci_devs.push_back(pci_dev);
+            return true;
+        }
+        return false;
+    };
+
+    auto add_pci_part = [&](int domainno, int busno, int devno, int part_number) {
+        struct iio_bifurcated_part part;
+        if (process_pci_dev(domainno, busno, devno, part_number, part)) {
+            stack.parts.push_back(part);
+        }
+    };
+
+    add_pci_part(address.domainno, address.busno, 1, SRF_DSA_IAX_PART_NUMBER);
+    add_pci_part(address.domainno, address.busno, 2, SRF_DSA_IAX_PART_NUMBER);
+
+    add_pci_part(address.domainno, address.busno + 1, 0, SRF_QAT_PART_NUMBER);
+
+    /* Bus number for HQM is higher on 3 than DSA bus number */
+    add_pci_part(address.domainno, address.busno + 3, 0, SRF_HQM_PART_NUMBER);
+
+    if (!stack.parts.empty()) {
+        iio_on_socket.stacks.push_back(stack);
+    }
+
+    return true;
+}
+
+bool BirchStreamPlatform::isPcieStack(int unit)
+{
+    return srf_pcie_stacks.find(unit) != srf_pcie_stacks.end();
+}
+
+/*
+ * HC is the name of DINO stacks as we had on SPR
+ */
+bool BirchStreamPlatform::isRootHcStack(int unit)
+{
+    return SRF_HC0_SAD_BUS_ID == unit || SRF_HC1_SAD_BUS_ID == unit ||
+           SRF_HC2_SAD_BUS_ID == unit || SRF_HC3_SAD_BUS_ID == unit;
+}
+
+bool BirchStreamPlatform::isPartHcStack(int unit)
+{
+    return isRootHcStack(unit - 1) || isRootHcStack(unit - 2);
+}
+
+bool BirchStreamPlatform::isUboxStack(int unit)
+{
+    return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit;
+}
+
+bool BirchStreamPlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket)
+{
+    if (isPcieStack(unit)) {
+        return birchStreamPciStackProbe(unit, address, iio_on_socket);
+    }
+    else if (isRootHcStack(unit)) {
+        return birchStreamAcceleratorStackProbe(unit, address, iio_on_socket);
+    }
+    else if (isPartHcStack(unit)) {
+        cout << "Found a part of HC stack. Stack ID - " << unit << " domain " << address.domainno
+             << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << ". Don't probe it again." << endl;
+        return true;
+    }
+    else if (isUboxStack(unit)) {
+        cout << "Found UBOX stack. Stack ID - " << unit << " domain " << address.domainno
+             << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl;
+        return true;
+    }
+
+    cout << "Unknown stack ID " << unit << " domain " << address.domainno << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl;
+
+    return false;
+}
+
+class DefaultPlatformMapping : public IPlatformMapping {
+protected:
+    const std::string stackIdToString(const int unit)
+    {
+        char buffer[64];
+        snprintf(buffer, sizeof(buffer), "Stack %2d", unit);
+        return std::string(buffer);
+    }
+
+    bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) override;
+public:
+    DefaultPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks)
+        : IPlatformMapping(model, sockets, stacks) {}
+};
+
+bool DefaultPlatformMapping::pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios)
+{
+    for (uint32_t socket = 0; socket < socketsCount(); socket++)
+    {
+        struct iio_stacks_on_socket iio_on_socket;
+        iio_on_socket.socket_id = socket;
+        for (uint32_t unit = 0; unit < stacksCount(); unit++)
+        {
+            struct iio_stack stack;
+            stack.iio_unit_id = unit;
+            stack.stack_name = stackIdToString(unit);
+            iio_on_socket.stacks.push_back(stack);
+        }
+        iios.push_back(iio_on_socket);
+    }
+
+    return true;
+}
+
+void IPlatformMapping::probeDeviceRange(std::vector<struct pci> &pci_devs, int domain, int secondary, int subordinate)
+{
+    for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) {
+        for (uint8_t device = 0; device < 32; device++) {
+            for (uint8_t function = 0; function < 8; function++) {
+                struct pci child_dev;
+                child_dev.bdf.domainno = domain;
+                child_dev.bdf.busno = bus;
+                child_dev.bdf.devno = device;
+                child_dev.bdf.funcno = function;
+                if (probe_pci(&child_dev)) {
+                    if (secondary < child_dev.secondary_bus_number && subordinate < child_dev.subordinate_bus_number) {
+                        probeDeviceRange(child_dev.child_pci_devs, domain, child_dev.secondary_bus_number, child_dev.subordinate_bus_number);
+                    }
+                    pci_devs.push_back(child_dev);
+                }
+            }
+        }
+    }
+}
+
+std::unique_ptr<IPlatformMapping> IPlatformMapping::getPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks)
+{
+    switch (model) {
+    case PCM::SKX:
+        return std::make_unique<PurleyPlatformMapping>(model, sockets);
+    case PCM::ICX:
+        return std::make_unique<WhitleyPlatformMapping>(model, sockets);
+    case PCM::SNOWRIDGE:
+        return std::make_unique<JacobsvillePlatformMapping>(model, sockets);
+    case PCM::SPR:
+    case PCM::EMR:
+        return std::make_unique<EagleStreamPlatformMapping>(model, sockets);
+    case PCM::GRR:
+        return std::make_unique<LoganvillePlatform>(model, sockets);
+    case PCM::SRF:
+    case PCM::GNR:
+        return std::make_unique<BirchStreamPlatform>(model, sockets);
+    default:
+        std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(model) << " is provided" << std::endl;
+        return std::make_unique<DefaultPlatformMapping>(model, sockets, stacks);
+    }
+}
+
+bool IPlatformMapping::initializeIOStacksStructure(std::vector<struct iio_stacks_on_socket>& iios, uint32_t model, uint32_t sockets, uint32_t stacks)
+{
+    std::unique_ptr<IPlatformMapping> mapping = nullptr;
+    try
+    {
+        mapping = getPlatformMapping(model, sockets, stacks);
+    }
+    catch (const std::exception & e)
+    {
+        std::cerr << "Error info:" << e.what() << std::endl;
+        return false;
+    }
+
+    return mapping->pciTreeDiscover(iios);
+}
\ No newline at end of file
diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h
new file mode 100644
index 00000000..fa2cd425
--- /dev/null
+++ b/src/pcm-iio-topology.h
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2025, Intel Corporation
+
+// written by Patrick Lu,
+//            Aaron Cruz
+//            Alexander Antonov
+//            and others
+#pragma once
+
+#ifdef _MSC_VER
+    #include <windows.h>
+    #include "windows/windriver.h"
+#else
+    #include <unistd.h>
+#endif
+
+#include <memory>
+#include <cstdint>
+#include <algorithm>
+
+#ifdef _MSC_VER
+    #include "freegetopt/getopt.h"
+#endif
+
+#include "lspci.h"
+
+using namespace std;
+using namespace pcm;
+
+class IPlatformMapping {
+private:
+    uint32_t m_sockets;
+    uint32_t m_model;
+    uint32_t m_stacks = 0;
+protected:
+    void probeDeviceRange(std::vector<struct pci> &child_pci_devs, int domain, int secondary, int subordinate);
+
+    uint32_t socketsCount() const { return m_sockets; }
+    uint32_t cpuId() const { return m_model; }
+    uint32_t stacksCount() const { return m_stacks; }
+
+    IPlatformMapping(uint32_t model, uint32_t sockets) : m_sockets(sockets), m_model(model) {}
+    IPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks) :
+        m_sockets(sockets), m_model(model), m_stacks(stacks) {}
+
+    virtual bool pciTreeDiscover(std::vector<struct iio_stacks_on_socket>& iios) = 0;
+    static std::unique_ptr<IPlatformMapping> getPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks);
+public:
+    virtual ~IPlatformMapping() {}
+
+    static bool initializeIOStacksStructure(std::vector<struct iio_stacks_on_socket>& iios, uint32_t model, uint32_t sockets, uint32_t stacks);
+};
diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp
index e4726bee..859d3f43 100644
--- a/src/pcm-iio.cpp
+++ b/src/pcm-iio.cpp
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: BSD-3-Clause
-// Copyright (c) 2017-2022, Intel Corporation
+// Copyright (c) 2017-2025, Intel Corporation
 
 // written by Patrick Lu,
-//            Aaron Cruz
+//            Aaron Cruz,
+//            Alexander Antonov
 //            and others
 
 #include "pcm-iio-pmu.h"
@@ -63,30 +64,9 @@ void print_usage(const string& progname)
     cout << "\n";
 }
 
-PCM_MAIN_NOTHROW;
-
-int mainThrows(int argc, char * argv[])
+void parse_arguments(int argc, char * argv[], struct pcm_iio_config& config, MainLoop& mainLoop)
 {
-    if (print_version(argc, argv))
-        exit(EXIT_SUCCESS);
-
-    null_stream nullStream;
-    check_and_set_silent(argc, argv, nullStream);
-
-    std::cout << "\n Intel(r) Performance Counter Monitor " << PCM_VERSION << "\n";
-    std::cout << "\n This utility measures IIO information\n\n";
-
-    string program = string(argv[0]);
-
-    bool csv = false;
-    bool human_readable = false;
-    bool show_root_port = false;
-    std::string csv_delimiter = ",";
-    std::string output_file;
-    double delay = PCM_DELAY_DEFAULT;
-    bool list = false;
-    MainLoop mainLoop;
-
+    const string program = string(argv[0]);
     while (argc > 1) {
         argv++;
         argc--;
@@ -100,73 +80,84 @@ int mainThrows(int argc, char * argv[])
             continue;
         }
         else if (extract_argument_value(*argv, {"-csv-delimiter", "/csv-delimiter"}, arg_value)) {
-            csv_delimiter = std::move(arg_value);
+            config.display.csv_delimiter = std::move(arg_value);
         }
         else if (check_argument_equals(*argv, {"-csv", "/csv"})) {
-            csv = true;
+            config.display.csv = true;
         }
         else if (extract_argument_value(*argv, {"-csv", "/csv"}, arg_value)) {
-            csv = true;
-            output_file = std::move(arg_value);
+            config.display.csv = true;
+            config.display.output_file = std::move(arg_value);
         }
         else if (check_argument_equals(*argv, {"-human-readable", "/human-readable"})) {
-            human_readable = true;
+            config.display.human_readable = true;
         }
         else if (check_argument_equals(*argv, {"-list", "--list"})) {
-            list = true;
+            config.display.list = true;
         }
         else if (check_argument_equals(*argv, {"-root-port", "/root-port"})) {
-            show_root_port = true;
+            config.display.show_root_port = true;
         }
         else if (mainLoop.parseArg(*argv)) {
             continue;
         }
         else {
-            delay = parse_delay(*argv, program, (print_usage_func)print_usage);
+            config.pmu_config.delay = parse_delay(*argv, program, (print_usage_func)print_usage);
             continue;
         }
     }
+}
+
+PCM_MAIN_NOTHROW;
+
+int mainThrows(int argc, char * argv[])
+{
+    if (print_version(argc, argv))
+        exit(EXIT_SUCCESS);
+
+    null_stream nullStream;
+    check_and_set_silent(argc, argv, nullStream);
+
+    std::cout << "\n Intel(r) Performance Counter Monitor " << PCM_VERSION << "\n";
+    std::cout << "\n This utility measures IIO information\n\n";
+
+    struct pcm_iio_config config;
+    MainLoop mainLoop;
+
+    parse_arguments(argc, argv, config, mainLoop);
 
     set_signal_handlers();
 
     print_cpu_details();
 
-    PCM * m = PCM::getInstance();
-
     std::ostream* output = &std::cout;
     std::fstream file_stream;
-    if (!output_file.empty()) {
-        file_stream.open(output_file.c_str(), std::ios_base::out);
+    if (!config.display.output_file.empty()) {
+        file_stream.open(config.display.output_file.c_str(), std::ios_base::out);
         output = &file_stream;
     }
 
-    std::vector<struct iio_stacks_on_socket> iios;
-    iio_evt_parse_context evt_ctx;
-    // Map with metrics names.
-    PCIeEventNameMap_t nameMap;
-
-    if ( !initializeIIOCounters( iios, evt_ctx, nameMap ) )
+    if (!initializePCIeBWCounters(config.pmu_config))
         exit(EXIT_FAILURE);
 
-    PCIDB pciDB;
-    load_PCIDB(pciDB);
+    load_PCIDB(config.pciDB);
 
-    if (list) {
-        print_PCIeMapping(iios, pciDB, *output);
+    if (config.display.list) {
+        print_PCIeMapping(config.pmu_config.iios, config.pciDB, *output);
         return 0;
     }
 
-
 #ifdef PCM_DEBUG
-    print_nameMap(nameMap);
+    print_nameMap(config.pmu_config.nameMap);
 #endif
 
+    auto displayBuilder = getDisplayBuilder(config);
+    auto collector = std::make_unique<PcmIioDataCollector>(config.pmu_config);
+
     mainLoop([&]()
     {
-        collect_data(m, delay, iios, evt_ctx.ctrs);
-        vector<string> display_buffer = csv ?
-            build_csv(iios, evt_ctx.ctrs, human_readable, show_root_port, csv_delimiter, nameMap) :
-            build_display(iios, evt_ctx.ctrs, pciDB, nameMap);
+        collector->collectData();
+        vector<string> display_buffer = displayBuilder->buildDisplayBuffer();
         display(display_buffer, *output);
         return true;
     });
diff --git a/src/pcm-sensor-server.cpp b/src/pcm-sensor-server.cpp
index 57181734..f3ba4aae 100644
--- a/src/pcm-sensor-server.cpp
+++ b/src/pcm-sensor-server.cpp
@@ -4061,12 +4061,12 @@ int mainThrows(int argc, char * argv[]) {
         std::vector<struct iio_stacks_on_socket> iios;
         iio_evt_parse_context evt_ctx;
         std::string ev_file_name;
-        // Map with metrics names.
-        PCIeEventNameMap_t nameMap;
 
         // TODO: add check for IIO support before trying to initialize the pmu
+        // Map with metrics names.
+        // PCIeEventNameMap nameMap;
 // Otto: re-add this check when there is support for IIO and do it properly, seems to fail for some reason, see #788
-//        if ( !initializeIIOCounters( iios, evt_ctx, nameMap ) )
+//        if ( !initializePCIeBWCounters( iios, evt_ctx, nameMap ) )
 //        {
 //            std::cerr << "Error: IIO is NOT supported with this platform! Program aborted\n";
 //            exit(EXIT_FAILURE);
diff --git a/src/utils.cpp b/src/utils.cpp
index dc5de539..2b5b537b 100644
--- a/src/utils.cpp
+++ b/src/utils.cpp
@@ -813,10 +813,75 @@ std::vector<std::string> split(const std::string & str, const char delim)
 
 uint64 read_number(const char* str)
 {
-    std::istringstream stream(str);
-    if (strstr(str, "x")) stream >> std::hex;
+    if (str == nullptr || *str == '\0')
+    {
+        throw std::invalid_argument("Input string is null or empty");
+    }
+
+    std::string input(str);
+    // Trim leading and trailing whitespace
+    size_t start = input.find_first_not_of(" \t\n\r");
+    size_t end = input.find_last_not_of(" \t\n\r");
+    
+    if (start == std::string::npos)
+    {
+        throw std::invalid_argument("Input string contains only whitespace");
+    }
+    
+    input = input.substr(start, end - start + 1);
+    
+    std::istringstream stream(input);
     uint64 result = 0;
-    stream >> result;
+    
+    // Check if the input is hexadecimal (starts with 0x or 0X)
+    if (input.length() >= 2 && input[0] == '0' && (input[1] == 'x' || input[1] == 'X'))
+    {
+        if (input.length() == 2)
+        {
+            throw std::invalid_argument("Invalid hexadecimal number: no digits after 0x");
+        }
+        
+        // Validate that all characters after 0x are valid hex digits
+        for (size_t i = 2; i < input.length(); ++i)
+        {
+            char c = input[i];
+            if (!((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F')))
+            {
+                throw std::invalid_argument("Invalid hexadecimal number: contains non-hex characters");
+            }
+        }
+        
+        stream >> std::hex >> result;
+    }
+    else
+    {
+        // Validate that all characters are valid decimal digits
+        for (size_t i = 0; i < input.length(); ++i)
+        {
+            char c = input[i];
+            if (!(c >= '0' && c <= '9'))
+            {
+                throw std::invalid_argument("Invalid decimal number: contains non-digit characters");
+            }
+        }
+        
+        stream >> result;
+    }
+    
+    // Check if the stream operation failed or if there are remaining characters
+    if (stream.fail())
+    {
+        throw std::invalid_argument("Failed to parse number from input string");
+    }
+    
+    // Check if there are any remaining characters in the stream
+    std::string remaining;
+    stream >> remaining;
+    if (!remaining.empty())
+    {
+        throw std::invalid_argument("Input string contains extra characters after the number");
+    }
+    
     return result;
 }
 
@@ -1152,19 +1217,19 @@ void display(const std::vector<std::string> &buff, std::ostream& stream)
     stream << std::flush;
 }
 
-void print_nameMap(std::map<std::string,std::pair<uint32_t,std::map<std::string,uint32_t>>>& nameMap)
+void print_nameMap(const PCIeEventNameMap& nameMap)
 {
-    for (std::map<std::string,std::pair<uint32_t,std::map<std::string,uint32_t>>>::const_iterator iunit = nameMap.begin(); iunit != nameMap.end(); ++iunit)
+    for (const auto& iunit : nameMap)
     {
-        std::string h_name = iunit->first;
-        std::pair<uint32_t,std::map<std::string,uint32_t>> value = iunit->second;
+        const std::string& h_name = iunit.first;
+        const auto& value = iunit.second;
         uint32_t hid = value.first;
-        std::map<std::string,uint32_t> vMap = value.second;
+        const auto& vMap = value.second;
         std::cout << "H name: " << h_name << " id =" << hid << " vMap size:" << vMap.size() << "\n";
-        for (std::map<std::string,uint32_t>::const_iterator junit = vMap.begin(); junit != vMap.end(); ++junit)
+        for (const auto& junit : vMap)
         {
-            std::string v_name = junit->first;
-            uint32_t vid = junit->second;
+            const std::string& v_name = junit.first;
+            uint32_t vid = junit.second;
             std::cout << "V name: " << v_name << " id =" << vid << "\n";
         }
     }
@@ -1187,7 +1252,7 @@ void print_nameMap(std::map<std::string,std::pair<uint32_t,std::map<std::string,
 //! \return -1 means fail with app exit, 0 means success or fail with continue.
 int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                 int (*pfn_evtcb)(evt_cb_type, void *, counter &, std::map<std::string, uint32_t> &, std::string, uint64),
-                void *evtcb_ctx, std::map<std::string,std::pair<uint32_t,std::map<std::string,uint32_t>>> &nameMap)
+                void *evtcb_ctx, PCIeEventNameMap& nameMap)
 {
     struct counter ctr;
 
@@ -1196,6 +1261,7 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
     if (!in.is_open())
     {
         const auto alt_fn = getInstallPathPrefix() + fn;
+        std::cout << "INFO: Couldn't load event config file " << fn << ", trying to load it from PCM install path: " << alt_fn << std::endl;
         in.open(alt_fn);
         if (!in.is_open())
         {
@@ -1226,11 +1292,9 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
         }
 
         /* Ignore anyline with # */
-        if (line.find("#") != std::string::npos)
-            continue;
+        if (line.find("#") != std::string::npos) continue;
         /* If line does not have any deliminator, we ignore it as well */
-        if (line.find("=") == std::string::npos)
-            continue;
+        if (line.find("=") == std::string::npos) continue;
 
         std::string h_name, v_name;
         std::istringstream iss(line);
@@ -1256,11 +1320,11 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                     if (nameMap.find(h_name) == nameMap.end())
                     {
                         /* It's a new horizontal event name */
-                        uint32_t next_h_id = (uint32_t)nameMap.size();
-                        std::pair<uint32_t,std::map<std::string,uint32_t>> nameMap_value(next_h_id, std::map<std::string,uint32_t>());
+                        auto next_h_id = static_cast<uint32_t>(nameMap.size());
+                        auto nameMap_value = std::make_pair(next_h_id, CounterValueMap());
                         nameMap[h_name] = nameMap_value;
                     }
-                    ctr.h_id = (uint32_t)nameMap.size() - 1;
+                    ctr.h_id = static_cast<uint32_t>(nameMap.size()) - 1;
                     DBG(2, "h_name:" , ctr.h_event_name , "h_id: ", ctr.h_id);
                     break;
                 case PCM::V_EVENT_NAME:
@@ -1269,10 +1333,10 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                         ctr.v_event_name = v_name;
                         //XXX: If h_name comes after v_name, we'll have a problem.
                         //XXX: It's very weird, I forgot to assign nameMap[h_name] = nameMap_value earlier (:298), but this part still works?
-                        std::map<std::string,uint32_t> &v_nameMap = nameMap[h_name].second;
+                        auto& v_nameMap = nameMap[h_name].second;
                         if (v_nameMap.find(v_name) == v_nameMap.end())
                         {
-                            v_nameMap[v_name] = (unsigned int)v_nameMap.size() - 1;
+                            v_nameMap[v_name] = static_cast<uint32_t>(v_nameMap.size()) - 1;
                             DBG(2, "v_name(" , v_name , ")=", v_nameMap[v_name]);
                         }
                         else
@@ -1281,21 +1345,35 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                             const auto err_msg = std::string("Detect duplicated v_name:") + v_name + "\n";
                             throw std::invalid_argument(err_msg);
                         }
-                        ctr.v_id = (uint32_t)v_nameMap.size() - 1;
+                        ctr.v_id = static_cast<uint32_t>(v_nameMap.size()) - 1;
                         DBG(2, "h_name:" , ctr.h_event_name , ",hid=" , ctr.h_id , ",v_name:" , ctr.v_event_name , ",v_id: ", ctr.v_id);
                         break;
                     }
                 //TODO: double type for multiplier. drop divider variable
                 case PCM::MULTIPLIER:
-                    ctr.multiplier = (int)numValue;
+                    ctr.multiplier = static_cast<int>(numValue);
                     break;
                 case PCM::DIVIDER:
-                    ctr.divider = (int)numValue;
+                    ctr.divider = static_cast<int>(numValue);
                     break;
                 case PCM::COUNTER_INDEX:
-                    ctr.idx = (int)numValue;
+                    ctr.idx = static_cast<int>(numValue);
+                    break;
+                case PCM::UNIT_TYPE:
+                    {
+                        auto typeString = dos2unix(value);
+                        if (typeString == std::string("iio"))
+                        {
+                            ctr.type = CounterType::iio;
+                        }
+                        else
+                        {
+                            in.close();
+                            const auto err_msg = std::string("event line processing(end) fault.\n");
+                            throw std::invalid_argument(err_msg);
+                        }
+                    }
                     break;
-
                 default:
                     if (pfn_evtcb(EVT_LINE_FIELD, evtcb_ctx, ctr, ofm, key, numValue))
                     {
@@ -1325,7 +1403,7 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                 int (*pfn_evtcb)(evt_cb_type, void *, counter &, std::map<std::string, uint32_t> &, std::string, uint64),
                 void *evtcb_ctx)
 {
-    std::map<std::string,std::pair<uint32_t,std::map<std::string,uint32_t>>> nm;
+    PCIeEventNameMap nm;
     return load_events(fn, ofm, pfn_evtcb, evtcb_ctx, nm);
 }
 
diff --git a/src/utils.h b/src/utils.h
index 5a0f4f16..7b8d112e 100644
--- a/src/utils.h
+++ b/src/utils.h
@@ -587,6 +587,12 @@ inline void parsePID(int argc, char* argv[], int& pid)
     parseParam(argc, argv, "pid", [&pid](const char* p) { if (p) pid = atoi(p); });
 }
 
+enum class CounterType {
+    COUNTER_TYPE_INVALID = -1,
+    iio = 0,
+    COUNTER_TYPES_COUNT
+};
+
 struct counter {
     std::string h_event_name = "";
     std::string v_event_name = "";
@@ -596,6 +602,7 @@ struct counter {
     int divider = 0;
     uint32_t h_id = 0;
     uint32_t v_id = 0;
+    CounterType type = CounterType::COUNTER_TYPE_INVALID;
 };
 
 struct data{
@@ -609,6 +616,13 @@ typedef enum{
     EVT_LINE_COMPLETE
 }evt_cb_type;
 
+using EventName = std::string;
+using CounterName = std::string;
+
+using CounterValueMap = std::unordered_map<CounterName, uint32_t>;
+using EventDefinition = std::pair<uint32_t, CounterValueMap>;
+using PCIeEventNameMap = std::unordered_map<EventName, EventDefinition>;
+
 void getMCFGRecords(std::vector<MCFGRecord>& mcfg);
 std::string dos2unix(std::string in);
 bool isRegisterEvent(const std::string & pmu);
@@ -620,10 +634,10 @@ std::string build_csv_row(const std::vector<std::string>& chunks, const std::str
 std::vector<struct data> prepare_data(const std::vector<uint64_t> &values, const std::vector<std::string> &headers);
 void display(const std::vector<std::string> &buff, std::ostream& stream);
 
-void print_nameMap(std::map<std::string,std::pair<uint32_t,std::map<std::string,uint32_t>>>& nameMap);
+void print_nameMap(const PCIeEventNameMap& nameMap);
 int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                 int (*p_fn_evtcb)(evt_cb_type, void *, counter &, std::map<std::string, uint32_t> &, std::string, uint64),
-                void *evtcb_ctx, std::map<std::string,std::pair<uint32_t,std::map<std::string,uint32_t>>> &nameMap);
+                void *evtcb_ctx, PCIeEventNameMap& nameMap);
 int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
                 int (*pfn_evtcb)(evt_cb_type, void *, counter &, std::map<std::string, uint32_t> &, std::string, uint64),
                 void *evtcb_ctx);
diff --git a/tests/utests/CMakeLists.txt b/tests/utests/CMakeLists.txt
index 6abc27a9..49fbc781 100644
--- a/tests/utests/CMakeLists.txt
+++ b/tests/utests/CMakeLists.txt
@@ -15,6 +15,8 @@ if(APPLE)
 endif()
 
 file(GLOB LSPCI_TEST_FILES lspci-utest.cpp ${CMAKE_SOURCE_DIR}/src/lspci.cpp)
+file(GLOB PCM_IIO_TEST_FILES pcm-iio-utest.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-pmu.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-topology.cpp)
+file(GLOB READ_NUMBER_TEST_FILES read-number-utest.cpp)
 
 if(APPLE)
     set(LIBS PcmMsr Threads::Threads PCM_STATIC)
@@ -23,6 +25,14 @@ else()
 endif()
 
 add_executable(lspci-utest ${LSPCI_TEST_FILES})
+add_executable(pcm-iio-utest ${PCM_IIO_TEST_FILES})
+add_executable(read-number-utest ${READ_NUMBER_TEST_FILES})
+
+configure_file(
+    ${CMAKE_SOURCE_DIR}/src/opCode-6-174.txt
+    ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/opCode-6-174.txt
+    COPYONLY
+)
 
 target_link_libraries(
     lspci-utest
@@ -31,5 +41,21 @@ target_link_libraries(
     ${LIBS}
 )
 
+target_link_libraries(
+    pcm-iio-utest
+    GTest::gtest_main
+    GTest::gmock_main
+    ${LIBS}
+)
+
+target_link_libraries(
+    read-number-utest
+    GTest::gtest_main
+    GTest::gmock_main
+    ${LIBS}
+)
+
 include(GoogleTest)
 gtest_discover_tests(lspci-utest)
+gtest_discover_tests(pcm-iio-utest)
+gtest_discover_tests(read-number-utest)
diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp
new file mode 100644
index 00000000..76b6fe53
--- /dev/null
+++ b/tests/utests/pcm-iio-utest.cpp
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2009-2025, Intel Corporation
+// written by Alexander Antonov
+
+#include <gtest/gtest.h>
+#include <string>
+#include <map>
+#include <vector>
+#include <iostream>
+#include "utils.h"
+#include "pcm-iio-pmu.h"
+#include "pcm-iio-topology.h"
+
+using namespace pcm;
+
+class LoadEventsTest : public ::testing::Test {
+protected:
+    void SetUp() override
+    {
+        fillOpcodeFieldMapForPCIeEvents(opcodeFieldMap);
+
+        evt_ctx.ctrs.clear();
+    }
+
+    std::map<std::string, uint32_t> opcodeFieldMap;
+    iio_evt_parse_context evt_ctx;
+    PCIeEventNameMap nameMap;
+};
+
+// Structure to hold expected event data from file
+struct ExpectedEvent {
+    int ctr;
+    uint32_t ev_sel;
+    uint32_t umask;
+    uint32_t ch_mask;
+    uint32_t fc_mask;
+    int multiplier;
+    std::string hname;
+    std::string vname;
+    CounterType type;
+
+    bool operator==(const struct iio_counter& actual) const
+    {
+        bool basic_match =
+            ctr == actual.idx &&
+            hname == actual.h_event_name &&
+            vname == actual.v_event_name &&
+            multiplier == actual.multiplier;
+
+        bool ev_sel_match = (actual.ccr & 0xFF) == ev_sel;
+        bool umask_match = ((actual.ccr >> 8) & 0xFF) == umask;
+
+        bool ch_mask_match = (((actual.ccr >> 36) & 0xFFF) == ch_mask);
+        bool fc_mask_match = (((actual.ccr >> 48) & 0x7) == fc_mask);
+
+        bool counter_type_match = (actual.type == type);
+
+        return basic_match && ev_sel_match && umask_match && ch_mask_match && fc_mask_match && counter_type_match;
+    }
+};
+
+TEST_F(LoadEventsTest, TestLoadEventsAlternateVersion)
+{
+    const std::string eventFile = "opCode-6-174.txt";
+
+    evt_ctx.cpu_family_model = PCM_CPU_FAMILY_MODEL(6, 174);
+
+    ASSERT_NO_THROW({
+        load_events(eventFile, opcodeFieldMap, iio_evt_parse_handler, &evt_ctx);
+    });
+
+    ASSERT_FALSE(evt_ctx.ctrs.empty()) << "No events were loaded from the file";
+
+    // Verify at least one counter was properly initialized
+    bool foundCounterWithProperConfig = false;
+    for (const auto& ctr : evt_ctx.ctrs) {
+        if (ctr.ccr != 0) {
+            foundCounterWithProperConfig = true;
+            break;
+        }
+    }
+    EXPECT_TRUE(foundCounterWithProperConfig) << "No properly configured counters found";
+}
+
+TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile)
+{
+    std::vector<ExpectedEvent> expectedEvents = {
+        // IB write events
+        {0, 0x83, 0x1, 1,  0x7,  4, "IB write", "Part0", CounterType::iio},
+        {1, 0x83, 0x1, 2,  0x7,  4, "IB write", "Part1", CounterType::iio},
+        {0, 0x83, 0x1, 4,  0x7,  4, "IB write", "Part2", CounterType::iio},
+        {1, 0x83, 0x1, 8,  0x7,  4, "IB write", "Part3", CounterType::iio},
+        {0, 0x83, 0x1, 16, 0x7,  4, "IB write", "Part4", CounterType::iio},
+        {1, 0x83, 0x1, 32, 0x7,  4, "IB write", "Part5", CounterType::iio},
+        {0, 0x83, 0x1, 64, 0x7,  4, "IB write", "Part6", CounterType::iio},
+        {1, 0x83, 0x1, 128, 0x7, 4, "IB write", "Part7", CounterType::iio},
+
+        // IB read events
+        {0, 0x83, 0x4, 1,   0x7, 4, "IB read", "Part0", CounterType::iio},
+        {1, 0x83, 0x4, 2,   0x7, 4, "IB read", "Part1", CounterType::iio},
+        {0, 0x83, 0x4, 4,   0x7, 4, "IB read", "Part2", CounterType::iio},
+        {1, 0x83, 0x4, 8,   0x7, 4, "IB read", "Part3", CounterType::iio},
+        {0, 0x83, 0x4, 16,  0x7, 4, "IB read", "Part4", CounterType::iio},
+        {1, 0x83, 0x4, 32,  0x7, 4, "IB read", "Part5", CounterType::iio},
+        {0, 0x83, 0x4, 64,  0x7, 4, "IB read", "Part6", CounterType::iio},
+        {1, 0x83, 0x4, 128, 0x7, 4, "IB read", "Part7", CounterType::iio},
+
+        // OB read events
+        {2, 0xc0, 0x4, 1,   0x7, 4, "OB read", "Part0", CounterType::iio},
+        {3, 0xc0, 0x4, 2,   0x7, 4, "OB read", "Part1", CounterType::iio},
+        {2, 0xc0, 0x4, 4,   0x7, 4, "OB read", "Part2", CounterType::iio},
+        {3, 0xc0, 0x4, 8,   0x7, 4, "OB read", "Part3", CounterType::iio},
+        {2, 0xc0, 0x4, 16,  0x7, 4, "OB read", "Part4", CounterType::iio},
+        {3, 0xc0, 0x4, 32,  0x7, 4, "OB read", "Part5", CounterType::iio},
+        {2, 0xc0, 0x4, 64,  0x7, 4, "OB read", "Part6", CounterType::iio},
+        {3, 0xc0, 0x4, 128, 0x7, 4, "OB read", "Part7", CounterType::iio},
+
+        // OB write events
+        {2, 0xc0, 0x1, 1,   0x7, 4, "OB write", "Part0", CounterType::iio},
+        {3, 0xc0, 0x1, 2,   0x7, 4, "OB write", "Part1", CounterType::iio},
+        {2, 0xc0, 0x1, 4,   0x7, 4, "OB write", "Part2", CounterType::iio},
+        {3, 0xc0, 0x1, 8,   0x7, 4, "OB write", "Part3", CounterType::iio},
+        {2, 0xc0, 0x1, 16,  0x7, 4, "OB write", "Part4", CounterType::iio},
+        {3, 0xc0, 0x1, 32,  0x7, 4, "OB write", "Part5", CounterType::iio},
+        {2, 0xc0, 0x1, 64,  0x7, 4, "OB write", "Part6", CounterType::iio},
+        {3, 0xc0, 0x1, 128, 0x7, 4, "OB write", "Part7", CounterType::iio},
+
+        // IOMMU events
+        {0, 0x40, 0x01, 0x0, 0x0, 1, "IOTLB Lookup",     "Total", CounterType::iio},
+        {1, 0x40, 0x20, 0x0, 0x0, 1, "IOTLB Miss",       "Total", CounterType::iio},
+        {2, 0x40, 0x80, 0x0, 0x0, 1, "Ctxt Cache Hit",   "Total", CounterType::iio},
+        {3, 0x41, 0x10, 0x0, 0x0, 1, "256T Cache Hit",   "Total", CounterType::iio},
+        {0, 0x41, 0x08, 0x0, 0x0, 1, "512G Cache Hit",   "Total", CounterType::iio},
+        {1, 0x41, 0x04, 0x0, 0x0, 1, "1G Cache Hit",     "Total", CounterType::iio},
+        {2, 0x41, 0x02, 0x0, 0x0, 1, "2M Cache Hit",     "Total", CounterType::iio},
+        {3, 0x41, 0xc0, 0x0, 0x0, 1, "IOMMU Mem Access", "Total", CounterType::iio},
+    };
+
+    evt_ctx.cpu_family_model = PCM_CPU_FAMILY_MODEL(6, 174);
+
+    evt_ctx.ctrs.clear();
+    ASSERT_NO_THROW({
+        load_events("opCode-6-174.txt", opcodeFieldMap, iio_evt_parse_handler, &evt_ctx);
+    });
+
+    ASSERT_EQ(expectedEvents.size(), evt_ctx.ctrs.size())
+        << "Number of loaded events doesn't match expected count";
+
+    std::vector<bool> foundEvents(expectedEvents.size(), false);
+
+    // For each loaded event, find and verify the matching expected event
+    for (const auto& actualEvt : evt_ctx.ctrs) {
+        bool found = false;
+        for (size_t i = 0; i < expectedEvents.size(); ++i) {
+            if (!foundEvents[i] && expectedEvents[i] == actualEvt) {
+                foundEvents[i] = true;
+                found = true;
+
+                EXPECT_EQ(expectedEvents[i].ctr, actualEvt.idx)
+                    << "Counter index mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                EXPECT_EQ(expectedEvents[i].ev_sel, (actualEvt.ccr & 0xFF))
+                    << "Event select mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                EXPECT_EQ(expectedEvents[i].umask, ((actualEvt.ccr >> 8) & 0xFF))
+                    << "UMASK mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                EXPECT_EQ(expectedEvents[i].ch_mask, ((actualEvt.ccr >> 36) & 0xFFF))
+                    << "CH_MASK mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                EXPECT_EQ(expectedEvents[i].fc_mask, ((actualEvt.ccr >> 48) & 0x7))
+                    << "FC_MASK mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                EXPECT_EQ(expectedEvents[i].multiplier, actualEvt.multiplier)
+                    << "Multiplier mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                EXPECT_EQ(expectedEvents[i].type, actualEvt.type)
+                    << "Counter type mismatch for " << actualEvt.h_event_name
+                    << "/" << actualEvt.v_event_name;
+
+                break;
+            }
+        }
+        EXPECT_TRUE(found) << "Could not find expected event for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name
+            << "\nActual event details:"
+            << "\n  Counter index: " << actualEvt.idx
+            << "\n  Event select: 0x" << std::hex << (actualEvt.ccr & 0xFF) << std::dec
+            << "\n  UMASK: 0x" << std::hex << ((actualEvt.ccr >> 8) & 0xFF) << std::dec
+            << "\n  CH_MASK: 0x" << std::hex << ((actualEvt.ccr >> 36) & 0xFFF) << std::dec
+            << "\n  FC_MASK: 0x" << std::hex << ((actualEvt.ccr >> 48) & 0x7) << std::dec
+            << "\n  CCR (full): 0x" << std::hex << actualEvt.ccr << std::dec
+            << "\n  Multiplier: " << actualEvt.multiplier
+            << "\n  Type: " << static_cast<int>(actualEvt.type);
+    }
+
+    // Verify all expected events were found
+    for (size_t i = 0; i < foundEvents.size(); ++i) {
+        EXPECT_TRUE(foundEvents[i]) << "Expected event " << expectedEvents[i].hname
+                                << "/" << expectedEvents[i].vname << " was not loaded";
+    }
+}
+
+class PcmIioTopologyTestBase: public ::testing::Test
+{
+};
+
+TEST_F(PcmIioTopologyTestBase, DefaultTopologyTest)
+{
+    // Use invalid value to trigger default platform mapping
+    const uint32_t model = PCM::END_OF_MODEL_LIST;
+    const uint32_t sockets = 2;
+    const uint32_t stacks = 12;
+
+    const std::vector<std::string> expectedStackNames =
+    {
+        "Stack  0", "Stack  1", "Stack  2",
+        "Stack  3", "Stack  4", "Stack  5",
+        "Stack  6", "Stack  7", "Stack  8",
+        "Stack  9", "Stack 10", "Stack 11"
+    };
+
+    std::vector<struct iio_stacks_on_socket> iios;
+    ASSERT_TRUE(IPlatformMapping::initializeIOStacksStructure(iios, model, sockets, stacks)) << "Failed to initialize IIO stacks structure";
+
+    ASSERT_EQ(iios.size(), sockets) << "Number of sockets mismatch";
+    for (const auto &iio_on_socket : iios)
+    {
+        ASSERT_EQ(iio_on_socket.stacks.size(), stacks) << "Number of stacks per socket mismatch";
+        for (uint32_t unit = 0; unit < stacks; unit++)
+        {
+            ASSERT_EQ(iio_on_socket.stacks[unit].iio_unit_id, unit) << "Stack ID mismatch";
+            EXPECT_EQ(iio_on_socket.stacks[unit].stack_name, expectedStackNames[unit]) << "Stack name mismatch";
+        }
+    }
+}
diff --git a/tests/utests/read-number-utest.cpp b/tests/utests/read-number-utest.cpp
new file mode 100644
index 00000000..3f559f9c
--- /dev/null
+++ b/tests/utests/read-number-utest.cpp
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2009-2025, Intel Corporation
+
+#include "utils.h"
+#include <gtest/gtest.h>
+#include <stdexcept>
+
+using namespace pcm;
+
+// Test valid decimal numbers
+TEST(ReadNumberTest, ValidDecimalNumbers)
+{
+    EXPECT_EQ(read_number("0"), 0ULL);
+    EXPECT_EQ(read_number("123"), 123ULL);
+    EXPECT_EQ(read_number("456789"), 456789ULL);
+    EXPECT_EQ(read_number("18446744073709551615"), 18446744073709551615ULL); // max uint64
+}
+
+// Test valid hexadecimal numbers
+TEST(ReadNumberTest, ValidHexadecimalNumbers)
+{
+    EXPECT_EQ(read_number("0x0"), 0ULL);
+    EXPECT_EQ(read_number("0x10"), 16ULL);
+    EXPECT_EQ(read_number("0xFF"), 255ULL);
+    EXPECT_EQ(read_number("0xABCD"), 43981ULL);
+    EXPECT_EQ(read_number("0xFFFFFFFFFFFFFFFF"), 18446744073709551615ULL); // max uint64
+    EXPECT_EQ(read_number("0Xabcd"), 43981ULL); // capital X
+}
+
+// Test invalid inputs - should throw exceptions
+TEST(ReadNumberTest, InvalidInputsThrowException)
+{
+    EXPECT_THROW(read_number(""), std::invalid_argument);
+    EXPECT_THROW(read_number("abc"), std::invalid_argument);
+    EXPECT_THROW(read_number("12abc"), std::invalid_argument);
+    EXPECT_THROW(read_number("0xGHI"), std::invalid_argument);
+    EXPECT_THROW(read_number("not a number"), std::invalid_argument);
+    EXPECT_THROW(read_number("123.456"), std::invalid_argument);
+    EXPECT_THROW(read_number("-123"), std::invalid_argument);
+    EXPECT_THROW(read_number("0x"), std::invalid_argument);
+    EXPECT_THROW(read_number("x123"), std::invalid_argument);
+    EXPECT_THROW(read_number("  "), std::invalid_argument);
+}
+
+// Test edge cases with whitespace
+TEST(ReadNumberTest, WhitespaceHandling)
+{
+    // Leading/trailing whitespace should be acceptable
+    EXPECT_EQ(read_number(" 123"), 123ULL);
+    EXPECT_EQ(read_number("123 "), 123ULL);
+    EXPECT_EQ(read_number(" 123 "), 123ULL);
+    EXPECT_EQ(read_number(" 0x10 "), 16ULL);
+}
+
+// Test numbers with extra characters should throw
+TEST(ReadNumberTest, ExtraCharactersThrowException)
+{
+    EXPECT_THROW(read_number("123abc"), std::invalid_argument);
+    EXPECT_THROW(read_number("0x10ZZ"), std::invalid_argument);
+    EXPECT_THROW(read_number("12 34"), std::invalid_argument);
+}