From b791df09bcb5fcf19d4f4cfe5ad4169d87503a74 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Mon, 22 Sep 2025 13:20:28 +0200 Subject: [PATCH 01/54] PMU discovery: don't fail on error, print warning and continue Change-Id: If5930428706b7e11b2a3edc522f212ef6c13e99f --- src/uncore_pmu_discovery.cpp | 70 +++++++++++++++++++++++------------- 1 file changed, 45 insertions(+), 25 deletions(-) diff --git a/src/uncore_pmu_discovery.cpp b/src/uncore_pmu_discovery.cpp index 62e47516..af3992f5 100644 --- a/src/uncore_pmu_discovery.cpp +++ b/src/uncore_pmu_discovery.cpp @@ -15,35 +15,55 @@ UncorePMUDiscovery::UncorePMUDiscovery() { return; } - auto processTables = [this](const uint64 bar, const VSEC &) + auto processTables = [this](const uint64 bar, const VSEC & vsec) { - constexpr size_t UncoreDiscoverySize = 3UL; - union UncoreGlobalDiscovery { - GlobalPMU pmu; - uint64 table[UncoreDiscoverySize]; - }; - UncoreGlobalDiscovery global; - mmio_memcpy(global.table, bar, UncoreDiscoverySize * sizeof(uint64), true); - globalPMUs.push_back(global.pmu); - union UncoreUnitDiscovery { - BoxPMU pmu; - uint64 table[UncoreDiscoverySize]; - }; - UncoreUnitDiscovery unit; - const auto step = global.pmu.stride * 8; - BoxPMUMap boxPMUMap; - for (size_t u = 0; u < global.pmu.maxUnits; ++u) - { - mmio_memcpy(unit.table, bar + (u+1) * step, UncoreDiscoverySize * sizeof(uint64), true); - if (unit.table[0] == 0 && unit.table[1] == 0) + try { + constexpr size_t UncoreDiscoverySize = 3UL; + union UncoreGlobalDiscovery { + GlobalPMU pmu; + uint64 table[UncoreDiscoverySize]; + }; + UncoreGlobalDiscovery global; + mmio_memcpy(global.table, bar, UncoreDiscoverySize * sizeof(uint64), true); + globalPMUs.push_back(global.pmu); + union UncoreUnitDiscovery { + BoxPMU pmu; + uint64 table[UncoreDiscoverySize]; + }; + UncoreUnitDiscovery unit; + const auto step = global.pmu.stride * 8; + BoxPMUMap boxPMUMap; + for (size_t u = 0; u < global.pmu.maxUnits; ++u) { - // invalid entry - continue; + mmio_memcpy(unit.table, bar + (u + 1) * step, UncoreDiscoverySize * sizeof(uint64), true); + if (unit.table[0] == 0 && unit.table[1] == 0) + { + // invalid entry + continue; + } + // unit.pmu.print(); + boxPMUMap[unit.pmu.boxType].push_back(unit.pmu); } - // unit.pmu.print(); - boxPMUMap[unit.pmu.boxType].push_back(unit.pmu); + boxPMUs.push_back(boxPMUMap); + } + catch (std::exception & e) + { + std::cerr << "WARNING: enumeration of devices in UncorePMUDiscovery failed on bar 0x" + << std::hex << bar << "\n" << e.what() << "\n" << + " CAP_ID: 0x" << vsec.fields.cap_id << "\n" << + " CAP_VERSION: 0x" << vsec.fields.cap_version << "\n" << + " CAP_NEXT: 0x" << vsec.fields.cap_next << "\n" << + " VSEC_ID: 0x" << vsec.fields.vsec_id << "\n" << + " VSEC_VERSION: 0x" << vsec.fields.vsec_version << "\n" << + " VSEC_LENGTH: 0x" << vsec.fields.vsec_length << "\n" << + " ENTRY_ID: 0x" << vsec.fields.entryID << "\n" << + " NUM_ENTRIES: 0x" << vsec.fields.NumEntries << "\n" << + " ENTRY_SIZE: 0x" << vsec.fields.EntrySize << "\n" << + " TBIR: 0x" << vsec.fields.tBIR << "\n" << + " ADDRESS: 0x" << vsec.fields.Address << + std::dec << "\n"; + std::cerr << "INFO: discovery has " << boxPMUs.size() << " entries\n"; } - boxPMUs.push_back(boxPMUMap); }; try { processDVSEC([](const VSEC & vsec) From fb437c98fff4b1564725d172de7d000b680cca4f Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Mon, 22 Sep 2025 13:45:58 +0200 Subject: [PATCH 02/54] Update src/uncore_pmu_discovery.cpp Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- src/uncore_pmu_discovery.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/uncore_pmu_discovery.cpp b/src/uncore_pmu_discovery.cpp index af3992f5..662f93fd 100644 --- a/src/uncore_pmu_discovery.cpp +++ b/src/uncore_pmu_discovery.cpp @@ -46,7 +46,7 @@ UncorePMUDiscovery::UncorePMUDiscovery() } boxPMUs.push_back(boxPMUMap); } - catch (std::exception & e) + catch (const std::exception & e) { std::cerr << "WARNING: enumeration of devices in UncorePMUDiscovery failed on bar 0x" << std::hex << bar << "\n" << e.what() << "\n" << From 7e6965ac85e9bdba0704225a8d033d7bb84a36b2 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Tue, 23 Sep 2025 16:29:56 +0200 Subject: [PATCH 03/54] pcm-raw: enable >1 UBOX counters Change-Id: I81517f0145c04cf511c20c15c08a6d6c028b3dcb --- src/pcm-raw.cpp | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index a92751e3..8bfdd02b 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -1877,10 +1877,11 @@ void printTransposed(const PCM::RawPMUConfigs& curPMUConfigs, } else if (type == "ubox") { + const auto numPMUs = (uint32)m->getMaxNumOfUncorePMUs(PCM::UBOX_PMU_ID); choose(outputType, - [&]() { printUncoreRows(nullptr, 1U, ""); }, - [&]() { printUncoreRows(nullptr, 1U, type); }, - [&]() { printUncoreRows([](const uint32, const uint32 i, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getUncoreCounter(PCM::UBOX_PMU_ID, 0, i, before, after); }, 1U, + [&]() { printUncoreRows(nullptr, numPMUs, ""); }, + [&]() { printUncoreRows(nullptr, numPMUs, type); }, + [&]() { printUncoreRows([](const uint32 u, const uint32 i, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getUncoreCounter(PCM::UBOX_PMU_ID, u, i, before, after); }, numPMUs, "UncoreClocks", [](const uint32, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getUncoreClocks(before, after); }); }); } @@ -2260,14 +2261,17 @@ void print(const PCM::RawPMUConfigs& curPMUConfigs, [&fixedEvents]() { cout << "UncoreClocks" << fixedEvents[0].second << separator; }, [&]() { cout << getUncoreClocks(BeforeUncoreState[s], AfterUncoreState[s]) << separator; }); } - int i = 0; - for (auto& event : events) + for (uint32 u = 0; u < m->getMaxNumOfUncorePMUs(PCM::UBOX_PMU_ID); ++u) { - choose(outputType, - [s]() { cout << "SKT" << s << separator; }, - [&event, &i]() { if (event.second.empty()) cout << "UBOXEvent" << i << separator; else cout << event.second << separator; }, - [&]() { cout << getUncoreCounter(PCM::UBOX_PMU_ID, 0, i, BeforeUncoreState[s], AfterUncoreState[s]) << separator; }); - ++i; + int i = 0; + for (auto& event : events) + { + choose(outputType, + [s, u]() { cout << "SKT" << s << "U" << u << separator; }, + [&event, &i]() { if (event.second.empty()) cout << "UBOXEvent" << i << separator; else cout << event.second << separator; }, + [&]() { cout << getUncoreCounter(PCM::UBOX_PMU_ID, u, i, BeforeUncoreState[s], AfterUncoreState[s]) << separator; }); + ++i; + } } } } From 0c39947adb55a77efaee809500ea08f35203b251 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 26 Sep 2025 08:51:07 +0200 Subject: [PATCH 04/54] add PCM_DEBUG_PMU_DISCOVERY capability Change-Id: Ifce75a0aa806f6ebc1f40cf7cf45485c31115951 --- src/uncore_pmu_discovery.cpp | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/uncore_pmu_discovery.cpp b/src/uncore_pmu_discovery.cpp index 662f93fd..fd968ef4 100644 --- a/src/uncore_pmu_discovery.cpp +++ b/src/uncore_pmu_discovery.cpp @@ -15,9 +15,12 @@ UncorePMUDiscovery::UncorePMUDiscovery() { return; } - auto processTables = [this](const uint64 bar, const VSEC & vsec) + const auto debug = (safe_getenv("PCM_DEBUG_PMU_DISCOVERY") == std::string("1")); + + auto processTables = [this, &debug](const uint64 bar, const VSEC & vsec) { try { + DBG(2, "Uncore discovery detection. Reading from bar 0x", std::hex, bar, std::dec); constexpr size_t UncoreDiscoverySize = 3UL; union UncoreGlobalDiscovery { GlobalPMU pmu; @@ -26,6 +29,12 @@ UncorePMUDiscovery::UncorePMUDiscovery() UncoreGlobalDiscovery global; mmio_memcpy(global.table, bar, UncoreDiscoverySize * sizeof(uint64), true); globalPMUs.push_back(global.pmu); + if (debug) + { + std::cerr << "Read global.pmu from 0x" << std::hex << bar << std::dec << "\n"; + global.pmu.print(); + std::cout.flush(); + } union UncoreUnitDiscovery { BoxPMU pmu; uint64 table[UncoreDiscoverySize]; @@ -36,8 +45,18 @@ UncorePMUDiscovery::UncorePMUDiscovery() for (size_t u = 0; u < global.pmu.maxUnits; ++u) { mmio_memcpy(unit.table, bar + (u + 1) * step, UncoreDiscoverySize * sizeof(uint64), true); + if (debug) + { + std::cerr << "Read unit.pmu " << u << " from 0x" << std::hex << (bar + (u + 1) * step) << std::dec << "\n"; + unit.pmu.print(); + std::cout.flush(); + } if (unit.table[0] == 0 && unit.table[1] == 0) { + if (debug) + { + std::cerr << "Invalid entry\n"; + } // invalid entry continue; } From 35ffd18e68c43fa01b87616b8b88351b9542f97d Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 26 Sep 2025 10:51:10 +0200 Subject: [PATCH 05/54] print more fields GlobalPMU Change-Id: If448cb04e501d5b5b072a4175ec32eea8ecec241 --- src/uncore_pmu_discovery.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/uncore_pmu_discovery.h b/src/uncore_pmu_discovery.h index 9d9f089d..7caddf7e 100644 --- a/src/uncore_pmu_discovery.h +++ b/src/uncore_pmu_discovery.h @@ -92,6 +92,9 @@ class UncorePMUDiscovery " globalCtrl: 0x" << std::hex << globalCtrlAddr; UncorePMUDiscovery::printHelper((accessTypeEnum)accessType, globalCtrlAddr); std::cout << " stride: " << std::dec << stride + << " maxUnits: " << maxUnits + << " statusOffset: " << statusOffset + << " numStatus: " << numStatus << "\n"; } }; From 4ebfe30d378891582610e43b1a4cc22f9bd6b1b1 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 02:21:33 -0700 Subject: [PATCH 06/54] Add UT for load_events function --- tests/utests/CMakeLists.txt | 16 +++ tests/utests/pcm-iio-utest.cpp | 206 +++++++++++++++++++++++++++++++++ 2 files changed, 222 insertions(+) create mode 100644 tests/utests/pcm-iio-utest.cpp diff --git a/tests/utests/CMakeLists.txt b/tests/utests/CMakeLists.txt index 6abc27a9..d789d0ba 100644 --- a/tests/utests/CMakeLists.txt +++ b/tests/utests/CMakeLists.txt @@ -15,6 +15,7 @@ if(APPLE) endif() file(GLOB LSPCI_TEST_FILES lspci-utest.cpp ${CMAKE_SOURCE_DIR}/src/lspci.cpp) +file(GLOB PCM_IIO_TEST_FILES pcm-iio-utest.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-pmu.cpp) if(APPLE) set(LIBS PcmMsr Threads::Threads PCM_STATIC) @@ -23,6 +24,13 @@ else() endif() add_executable(lspci-utest ${LSPCI_TEST_FILES}) +add_executable(pcm-iio-utest ${PCM_IIO_TEST_FILES}) + +configure_file( + ${CMAKE_SOURCE_DIR}/src/opCode-6-174.txt + ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/opCode-6-174.txt + COPYONLY +) target_link_libraries( lspci-utest @@ -31,5 +39,13 @@ target_link_libraries( ${LIBS} ) +target_link_libraries( + pcm-iio-utest + GTest::gtest_main + GTest::gmock_main + ${LIBS} +) + include(GoogleTest) gtest_discover_tests(lspci-utest) +gtest_discover_tests(pcm-iio-utest) diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp new file mode 100644 index 00000000..3d0a56d7 --- /dev/null +++ b/tests/utests/pcm-iio-utest.cpp @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2009-2025, Intel Corporation +// written by Alexander Antonov + +#include +#include +#include +#include +#include +#include "utils.h" +#include "pcm-iio-pmu.h" + +using namespace pcm; + +class LoadEventsTest : public ::testing::Test { +protected: + void SetUp() override + { + + fillOpcodeFieldMapForPCIeEvents(opcodeFieldMap); + + evt_ctx.m = PCM::getInstance(); + evt_ctx.ctrs.clear(); + } + + std::map opcodeFieldMap; + iio_evt_parse_context evt_ctx; + PCIeEventNameMap_t nameMap; +}; + +// Structure to hold expected event data from file +struct ExpectedEvent { + int ctr; + uint32_t ev_sel; + uint32_t umask; + uint32_t ch_mask; + uint32_t fc_mask; + int multiplier; + int divider; + std::string hname; + std::string vname; + + bool operator==(const struct iio_counter& actual) const + { + // Check if actual counter matches this expected event + bool basic_match = + ctr == actual.idx && + hname == actual.h_event_name && + vname == actual.v_event_name && + multiplier == actual.multiplier && + divider == actual.divider; + + // Check if ev_sel and umask were properly encoded in CCR + bool ev_sel_match = (actual.ccr & 0xFF) == ev_sel; + bool umask_match = ((actual.ccr >> 8) & 0xFF) == umask; + + // Check ch_mask and fc_mask fields + bool ch_mask_match = (((actual.ccr >> 36) & 0xFFF) == ch_mask); + bool fc_mask_match = (((actual.ccr >> 48) & 0x7) == fc_mask); + + return basic_match && ev_sel_match && umask_match && ch_mask_match && fc_mask_match; + } +}; + +TEST_F(LoadEventsTest, TestLoadEventsAlternateVersion) +{ + const std::string eventFile = "opCode-6-174.txt"; + + // Test the alternate version of load_events without nameMap + ASSERT_NO_THROW({ + load_events(eventFile, opcodeFieldMap, iio_evt_parse_handler, &evt_ctx); + }); + + // Verify events were loaded + ASSERT_FALSE(evt_ctx.ctrs.empty()) << "No events were loaded from the file"; + + // Verify at least one counter was properly initialized + bool foundCounterWithProperConfig = false; + for (const auto& ctr : evt_ctx.ctrs) { + if (ctr.ccr != 0) { + foundCounterWithProperConfig = true; + break; + } + } + EXPECT_TRUE(foundCounterWithProperConfig) << "No properly configured counters found"; +} + +TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) +{ + // 1. Define expected events directly (hardcoded values from opCode-6-174.txt) + std::vector expectedEvents = { + // IB write events + {0, 0x83, 0x1, 1, 0x7, 4, 1, "IB write", "Part0"}, + {1, 0x83, 0x1, 2, 0x7, 4, 1, "IB write", "Part1"}, + {0, 0x83, 0x1, 4, 0x7, 4, 1, "IB write", "Part2"}, + {1, 0x83, 0x1, 8, 0x7, 4, 1, "IB write", "Part3"}, + {0, 0x83, 0x1, 16, 0x7, 4, 1, "IB write", "Part4"}, + {1, 0x83, 0x1, 32, 0x7, 4, 1, "IB write", "Part5"}, + {0, 0x83, 0x1, 64, 0x7, 4, 1, "IB write", "Part6"}, + {1, 0x83, 0x1, 128, 0x7, 4, 1, "IB write", "Part7"}, + + // IB read events + {0, 0x83, 0x4, 1, 0x7, 4, 1, "IB read", "Part0"}, + {1, 0x83, 0x4, 2, 0x7, 4, 1, "IB read", "Part1"}, + {0, 0x83, 0x4, 4, 0x7, 4, 1, "IB read", "Part2"}, + {1, 0x83, 0x4, 8, 0x7, 4, 1, "IB read", "Part3"}, + {0, 0x83, 0x4, 16, 0x7, 4, 1, "IB read", "Part4"}, + {1, 0x83, 0x4, 32, 0x7, 4, 1, "IB read", "Part5"}, + {0, 0x83, 0x4, 64, 0x7, 4, 1, "IB read", "Part6"}, + {1, 0x83, 0x4, 128, 0x7, 4, 1, "IB read", "Part7"}, + + // OB read events + {2, 0xc0, 0x4, 1, 0x7, 4, 1, "OB read", "Part0"}, + {3, 0xc0, 0x4, 2, 0x7, 4, 1, "OB read", "Part1"}, + {2, 0xc0, 0x4, 4, 0x7, 4, 1, "OB read", "Part2"}, + {3, 0xc0, 0x4, 8, 0x7, 4, 1, "OB read", "Part3"}, + {2, 0xc0, 0x4, 16, 0x7, 4, 1, "OB read", "Part4"}, + {3, 0xc0, 0x4, 32, 0x7, 4, 1, "OB read", "Part5"}, + {2, 0xc0, 0x4, 64, 0x7, 4, 1, "OB read", "Part6"}, + {3, 0xc0, 0x4, 128, 0x7, 4, 1, "OB read", "Part7"}, + + // OB write events + {2, 0xc0, 0x1, 1, 0x7, 4, 1, "OB write", "Part0"}, + {3, 0xc0, 0x1, 2, 0x7, 4, 1, "OB write", "Part1"}, + {2, 0xc0, 0x1, 4, 0x7, 4, 1, "OB write", "Part2"}, + {3, 0xc0, 0x1, 8, 0x7, 4, 1, "OB write", "Part3"}, + {2, 0xc0, 0x1, 16, 0x7, 4, 1, "OB write", "Part4"}, + {3, 0xc0, 0x1, 32, 0x7, 4, 1, "OB write", "Part5"}, + {2, 0xc0, 0x1, 64, 0x7, 4, 1, "OB write", "Part6"}, + {3, 0xc0, 0x1, 128, 0x7, 4, 1, "OB write", "Part7"}, + + // IOMMU events + {0, 0x40, 0x01, 0x0, 0x0, 1, 1, "IOTLB Lookup", "Total"}, + {1, 0x40, 0x20, 0x0, 0x0, 1, 1, "IOTLB Miss", "Total"}, + {2, 0x40, 0x80, 0x0, 0x0, 1, 1, "Ctxt Cache Hit", "Total"}, + {3, 0x41, 0x10, 0x0, 0x0, 1, 1, "256T Cache Hit", "Total"}, + {0, 0x41, 0x08, 0x0, 0x0, 1, 1, "512G Cache Hit", "Total"}, + {1, 0x41, 0x04, 0x0, 0x0, 1, 1, "1G Cache Hit", "Total"}, + {2, 0x41, 0x02, 0x0, 0x0, 1, 1, "2M Cache Hit", "Total"}, + {3, 0x41, 0xc0, 0x0, 0x0, 1, 1, "IOMMU Mem Access", "Total"} + }; + + // 2. Load events using the existing function + evt_ctx.ctrs.clear(); + ASSERT_NO_THROW({ + load_events("opCode-6-174.txt", opcodeFieldMap, iio_evt_parse_handler, &evt_ctx); + }); + + // 3. Verify that all loaded events match the expected events + ASSERT_EQ(expectedEvents.size(), evt_ctx.ctrs.size()) + << "Number of loaded events doesn't match expected count"; + + // Create a copy of expected events that we'll mark as found + std::vector foundEvents(expectedEvents.size(), false); + + // For each loaded event, find and verify the matching expected event + for (const auto& actualEvt : evt_ctx.ctrs) { + bool found = false; + for (size_t i = 0; i < expectedEvents.size(); ++i) { + if (!foundEvents[i] && expectedEvents[i] == actualEvt) { + foundEvents[i] = true; + found = true; + + // Additional verification of specific fields + EXPECT_EQ(expectedEvents[i].ctr, actualEvt.idx) + << "Counter index mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + EXPECT_EQ(expectedEvents[i].ev_sel, (actualEvt.ccr & 0xFF)) + << "Event select mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + EXPECT_EQ(expectedEvents[i].umask, ((actualEvt.ccr >> 8) & 0xFF)) + << "UMASK mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + // Checks for ch_mask and fc_mask + EXPECT_EQ(expectedEvents[i].ch_mask, ((actualEvt.ccr >> 36) & 0xFFF)) + << "CH_MASK mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + EXPECT_EQ(expectedEvents[i].fc_mask, ((actualEvt.ccr >> 48) & 0x7)) + << "FC_MASK mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + EXPECT_EQ(expectedEvents[i].multiplier, actualEvt.multiplier) + << "Multiplier mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + EXPECT_EQ(expectedEvents[i].divider, actualEvt.divider) + << "Divider mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + + break; + } + } + EXPECT_TRUE(found) << "Could not find expected event for " + << actualEvt.h_event_name << "/" << actualEvt.v_event_name; + } + + // Verify all expected events were found + for (size_t i = 0; i < foundEvents.size(); ++i) { + EXPECT_TRUE(foundEvents[i]) << "Expected event " << expectedEvents[i].hname + << "/" << expectedEvents[i].vname << " was not loaded"; + } +} \ No newline at end of file From dfcb90639d95542169608318646b44d5cf8e4ee9 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 04:42:05 -0700 Subject: [PATCH 07/54] Rename initializeIIOCounters to initializePCIeBWCounters --- src/pcm-iio-pmu.cpp | 2 +- src/pcm-iio-pmu.h | 2 +- src/pcm-iio.cpp | 3 +-- src/pcm-sensor-server.cpp | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index e712fcc0..1b11e72d 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1526,7 +1526,7 @@ void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventN results.resize(m->getNumSockets(), stack_content(m->getMaxNumOfIIOStacks(), ctr_data())); } -bool initializeIIOCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap ) +bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap ) { PCM * m = PCM::getInstance(); if (!m->IIOEventsAvailable()) diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index df194c45..a1428d98 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -661,5 +661,5 @@ typedef map>> PCIeEventNameMap_t; void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap); -bool initializeIIOCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap ); +bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap ); diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index e4726bee..9129f3c2 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -145,7 +145,7 @@ int mainThrows(int argc, char * argv[]) // Map with metrics names. PCIeEventNameMap_t nameMap; - if ( !initializeIIOCounters( iios, evt_ctx, nameMap ) ) + if ( !initializePCIeBWCounters( iios, evt_ctx, nameMap ) ) exit(EXIT_FAILURE); PCIDB pciDB; @@ -156,7 +156,6 @@ int mainThrows(int argc, char * argv[]) return 0; } - #ifdef PCM_DEBUG print_nameMap(nameMap); #endif diff --git a/src/pcm-sensor-server.cpp b/src/pcm-sensor-server.cpp index 57181734..d115818c 100644 --- a/src/pcm-sensor-server.cpp +++ b/src/pcm-sensor-server.cpp @@ -4066,7 +4066,7 @@ int mainThrows(int argc, char * argv[]) { // TODO: add check for IIO support before trying to initialize the pmu // Otto: re-add this check when there is support for IIO and do it properly, seems to fail for some reason, see #788 -// if ( !initializeIIOCounters( iios, evt_ctx, nameMap ) ) +// if ( !initializePCIeBWCounters( iios, evt_ctx, nameMap ) ) // { // std::cerr << "Error: IIO is NOT supported with this platform! Program aborted\n"; // exit(EXIT_FAILURE); From bbe7d71869fe67fd8e0997d4c1bbcfbc2561416f Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 05:29:51 -0700 Subject: [PATCH 08/54] Refactor IIO monitoring with Builder pattern and modernize type system - Implement PcmIioOutputBuilder class hierarchy for flexible output formatting: * Add abstract base class PcmIioOutputBuilder * Create concrete implementations PcmIioCsvBuilder and PcmIioDisplayBuilder * Move display logic from main code into specialized builder classes - Replace legacy PCIeEventNameMap_t (std::map-based) with modern PCIeEventNameMap (std::unordered_map-based) throughout the codebase - Update all function signatures, implementations, and tests to use the new type system - Extract display formatting logic from main application flow, improving separation of concerns and making the code more maintainable - Apply consistent naming conventions across type aliases (EventName, CounterName, CounterValueMap, EventDefinition) - Improve performance through targeted use of unordered containers where appropriate - Simplify future output format additions via the new builder interface --- src/pcm-iio-pmu.cpp | 200 ++++++++++++++++----------------- src/pcm-iio-pmu.h | 56 +++++++-- src/pcm-iio.cpp | 13 ++- src/pcm-sensor-server.cpp | 4 +- src/utils.cpp | 36 +++--- src/utils.h | 11 +- tests/utests/pcm-iio-utest.cpp | 2 +- 7 files changed, 182 insertions(+), 140 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 1b11e72d..5ae00d21 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -9,12 +9,12 @@ result_content results; -vector combine_stack_name_and_counter_names(string stack_name, const map>> &nameMap) +vector combine_stack_name_and_counter_names(string stack_name, const PCIeEventNameMap& nameMap) { vector v; vector tmp(nameMap.size()); v.push_back(stack_name); - for (std::map>>::const_iterator iunit = nameMap.begin(); iunit != nameMap.end(); ++iunit) { + for (auto iunit = nameMap.begin(); iunit != nameMap.end(); ++iunit) { string h_name = iunit->first; int h_id = (iunit->second).first; tmp[h_id] = h_name; @@ -80,75 +80,6 @@ void build_pci_tree(vector &buffer, const PCIDB & pciDB, uint32_t column } } -vector build_display(vector& iios, vector& ctrs, const PCIDB& pciDB, - const map>> &nameMap) -{ - vector buffer; - vector headers; - vector data; - uint64_t header_width; - string row; - for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) { - buffer.push_back("Socket" + std::to_string(socket->socket_id)); - for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { - auto stack_id = stack->iio_unit_id; - headers = combine_stack_name_and_counter_names(stack->stack_name, nameMap); - //Print first row - row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer); - header_width = row.size(); - buffer.push_back(row); - //Print a_title - row = std::accumulate(headers.begin(), headers.end(), string("|"), a_title); - buffer.push_back(row); - //Print deliminator - row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer); - buffer.push_back(row); - //Print data - std::map> v_sort; - //re-organize data collection to be row wise - for (std::vector::iterator counter = ctrs.begin(); counter != ctrs.end(); ++counter) { - v_sort[counter->v_id][counter->h_id] = &(*counter); - } - for (std::map>::const_iterator vunit = v_sort.cbegin(); vunit != v_sort.cend(); ++vunit) { - map h_array = vunit->second; - uint32_t vv_id = vunit->first; - vector h_data; - string v_name = h_array[0]->v_event_name; - for (map::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) { - uint32_t hh_id = hunit->first; - uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair(hh_id,vv_id)]; - h_data.push_back(raw_data); - } - data = prepare_data(h_data, headers); - row = "| " + v_name; - row += string(abs(int(headers[0].size() - (row.size() - 1))), ' '); - row += std::accumulate(data.begin(), data.end(), string("|"), a_data); - buffer.push_back(row); - } - //Print deliminator - row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer); - buffer.push_back(row); - //Print pcie devices - for (const auto& part : stack->parts) { - uint8_t level = 1; - for (const auto& pci_device : part.child_pci_devs) { - row = build_pci_header(pciDB, (uint32_t)header_width, pci_device, -1, level); - buffer.push_back(row); - if (pci_device.hasChildDevices()) { - build_pci_tree(buffer, pciDB, (uint32_t)header_width, pci_device, -1, level + 1); - } else if (pci_device.header_type == 1) { - level++; - } - } - } - //Print footer - row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer); - buffer.push_back(row); - } - } - return buffer; -} - std::string get_root_port_dev(const bool show_root_port, int part_id, const pcm::iio_stack *stack) { char tmp[9] = " "; @@ -172,40 +103,40 @@ std::string get_root_port_dev(const bool show_root_port, int part_id, const pcm } -vector build_csv(vector& iios, vector& ctrs, - const bool human_readable, const bool show_root_port, const std::string& csv_delimiter, - const map>> &nameMap) +void PcmIioCsvBuilder::insertTimeStamp(vector & out, CsvOutputType type) +{ + std::string dateTime; + printDateForCSV(type, m_csv_delimiter, &dateTime); + // remove last delimiter + dateTime.pop_back(); + out.insert(out.begin(), dateTime); +} + +vector PcmIioCsvBuilder::buildDisplayBuffer() { vector result; vector current_row; - auto header = combine_stack_name_and_counter_names("Part", nameMap); + auto header = combine_stack_name_and_counter_names("Part", m_nameMap); header.insert(header.begin(), "Name"); - if (show_root_port) + if (m_show_root_port) header.insert(header.begin(), "Root Port"); header.insert(header.begin(), "Socket"); - auto insertDateTime = [&csv_delimiter](vector & out, CsvOutputType type) { - std::string dateTime; - printDateForCSV(type, csv_delimiter, &dateTime); - // remove last delimiter - dateTime.pop_back(); - out.insert(out.begin(), dateTime); - }; - insertDateTime(header, CsvOutputType::Header2); - result.push_back(build_csv_row(header, csv_delimiter)); + insertTimeStamp(header, CsvOutputType::Header2); + result.push_back(build_csv_row(header, m_csv_delimiter)); std::map> v_sort; //re-organize data collection to be row wise size_t max_name_width = 0; - for (std::vector::iterator counter = ctrs.begin(); counter != ctrs.end(); ++counter) { + for (auto counter = m_ctrs.begin(); counter != m_ctrs.end(); ++counter) { v_sort[counter->v_id][counter->h_id] = &(*counter); max_name_width = (std::max)(max_name_width, counter->v_event_name.size()); } - for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) { + for (auto socket = m_iios.cbegin(); socket != m_iios.cend(); ++socket) { for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { const std::string socket_name = "Socket" + std::to_string(socket->socket_id); std::string stack_name = stack->stack_name; - if (!human_readable) { + if (!m_human_readable) { stack_name.erase(stack_name.find_last_not_of(' ') + 1); } @@ -214,19 +145,19 @@ vector build_csv(vector& iios, vector>::const_iterator vunit; for (vunit = v_sort.cbegin(), part_id = 0; - vunit != v_sort.cend(); ++vunit, ++part_id) { + vunit != v_sort.cend(); ++vunit, ++part_id) { map h_array = vunit->second; uint32_t vv_id = vunit->first; vector h_data; string v_name = h_array[0]->v_event_name; - if (human_readable) { + if (m_human_readable) { v_name += string(max_name_width - (v_name.size()), ' '); } current_row.clear(); current_row.push_back(socket_name); - if (show_root_port) { - auto pci_dev = get_root_port_dev(show_root_port, part_id, &(*stack)); + if (m_show_root_port) { + auto pci_dev = get_root_port_dev(m_show_root_port, part_id, &(*stack)); current_row.push_back(pci_dev); } current_row.push_back(stack_name); @@ -234,16 +165,84 @@ vector build_csv(vector& iios, vector::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) { uint32_t hh_id = hunit->first; uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair(hh_id,vv_id)]; - current_row.push_back(human_readable ? unit_format(raw_data) : std::to_string(raw_data)); + current_row.push_back(m_human_readable ? unit_format(raw_data) : std::to_string(raw_data)); } - insertDateTime(current_row, CsvOutputType::Data); - result.push_back(build_csv_row(current_row, csv_delimiter)); + insertTimeStamp(current_row, CsvOutputType::Data); + result.push_back(build_csv_row(current_row, m_csv_delimiter)); } } } return result; } +vector PcmIioDisplayBuilder::buildDisplayBuffer() +{ + vector buffer; + vector headers; + vector data; + uint64_t header_width; + string row; + for (auto socket = m_iios.cbegin(); socket != m_iios.cend(); ++socket) { + buffer.push_back("Socket" + std::to_string(socket->socket_id)); + for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { + auto stack_id = stack->iio_unit_id; + headers = combine_stack_name_and_counter_names(stack->stack_name, m_nameMap); + //Print first row + row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer); + header_width = row.size(); + buffer.push_back(row); + //Print a_title + row = std::accumulate(headers.begin(), headers.end(), string("|"), a_title); + buffer.push_back(row); + //Print deliminator + row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer); + buffer.push_back(row); + //Print data + std::map> v_sort; + //re-organize data collection to be row wise + for (std::vector::iterator counter = m_ctrs.begin(); counter != m_ctrs.end(); ++counter) { + v_sort[counter->v_id][counter->h_id] = &(*counter); + } + for (std::map>::const_iterator vunit = v_sort.cbegin(); vunit != v_sort.cend(); ++vunit) { + map h_array = vunit->second; + uint32_t vv_id = vunit->first; + vector h_data; + string v_name = h_array[0]->v_event_name; + for (map::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) { + uint32_t hh_id = hunit->first; + uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair(hh_id,vv_id)]; + h_data.push_back(raw_data); + } + data = prepare_data(h_data, headers); + row = "| " + v_name; + row += string(abs(int(headers[0].size() - (row.size() - 1))), ' '); + row += std::accumulate(data.begin(), data.end(), string("|"), a_data); + buffer.push_back(row); + } + //Print deliminator + row = std::accumulate(headers.begin(), headers.end(), string("|"), a_header_footer); + buffer.push_back(row); + //Print pcie devices + for (const auto& part : stack->parts) { + uint8_t level = 1; + for (const auto& pci_device : part.child_pci_devs) { + row = build_pci_header(m_pciDB, (uint32_t)header_width, pci_device, -1, level); + buffer.push_back(row); + if (pci_device.hasChildDevices()) { + build_pci_tree(buffer, m_pciDB, (uint32_t)header_width, pci_device, -1, level + 1); + } else if (pci_device.header_type == 1) { + level++; + } + } + } + //Print footer + row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer); + buffer.push_back(row); + } + } + return buffer; +} + void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) { for (uint16_t bus = 0; bus < 256; bus++) { @@ -1492,19 +1491,18 @@ void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap) opcodeFieldMap["thresh"] = PCM::THRESH; opcodeFieldMap["ch_mask"] = PCM::CH_MASK; opcodeFieldMap["fc_mask"] = PCM::FC_MASK; - opcodeFieldMap["hname"] =PCM::H_EVENT_NAME; - opcodeFieldMap["vname"] =PCM::V_EVENT_NAME; + opcodeFieldMap["hname"] = PCM::H_EVENT_NAME; + opcodeFieldMap["vname"] = PCM::V_EVENT_NAME; opcodeFieldMap["multiplier"] = PCM::MULTIPLIER; opcodeFieldMap["divider"] = PCM::DIVIDER; opcodeFieldMap["ctr"] = PCM::COUNTER_INDEX; } -void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap) +void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap) { PCM * m = PCM::getInstance(); - string ev_file_name; - ev_file_name = "opCode-" + std::to_string(m->getCPUFamily()) + "-" + std::to_string(m->getInternalCPUModel()) + ".txt"; + string ev_file_name = "opCode-" + std::to_string(m->getCPUFamily()) + "-" + std::to_string(m->getInternalCPUModel()) + ".txt"; map opcodeFieldMap; fillOpcodeFieldMapForPCIeEvents( opcodeFieldMap ); @@ -1526,7 +1524,7 @@ void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventN results.resize(m->getNumSockets(), stack_content(m->getMaxNumOfIIOStacks(), ctr_data())); } -bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap ) +bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap ) { PCM * m = PCM::getInstance(); if (!m->IIOEventsAvailable()) diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index a1428d98..b07e10a6 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -495,20 +495,56 @@ typedef struct vector ctrs; } iio_evt_parse_context; -vector combine_stack_name_and_counter_names(string stack_name, const map>> &nameMap); +vector combine_stack_name_and_counter_names(string stack_name, const PCIeEventNameMap& nameMap); string build_pci_header(const PCIDB & pciDB, uint32_t column_width, const struct pci &p, int part = -1, uint32_t level = 0); void build_pci_tree(vector &buffer, const PCIDB & pciDB, uint32_t column_width, const struct pci &p, int part, uint32_t level = 0); -vector build_display(vector& iios, vector& ctrs, const PCIDB& pciDB, - const map>> &nameMap); - std::string get_root_port_dev(const bool show_root_port, int part_id, const pcm::iio_stack *stack); -vector build_csv(vector& iios, vector& ctrs, - const bool human_readable, const bool show_root_port, const std::string& csv_delimiter, - const map>> &nameMap); +class PcmIioOutputBuilder { +public: + PcmIioOutputBuilder(vector& iios, vector& ctrs, const PCIeEventNameMap& nameMap) + : m_iios(iios), m_ctrs(ctrs), m_nameMap(nameMap) {} + + virtual ~PcmIioOutputBuilder() = default; + + virtual vector buildDisplayBuffer() = 0; +protected: + vector& m_iios; + vector& m_ctrs; + const PCIeEventNameMap& m_nameMap; +}; + +class PcmIioCsvBuilder : public PcmIioOutputBuilder { +public: + PcmIioCsvBuilder(vector& iios, vector& ctrs, const PCIeEventNameMap& nameMap, + const bool human_readable, const bool show_root_port, const std::string& csv_delimiter) + : PcmIioOutputBuilder(iios, ctrs, nameMap), m_human_readable(human_readable), m_show_root_port(show_root_port), m_csv_delimiter(csv_delimiter) {} + + ~PcmIioCsvBuilder() = default; + + vector buildDisplayBuffer() override; +private: + void insertTimeStamp(vector & out, CsvOutputType type); + + bool m_human_readable; + bool m_show_root_port; + std::string m_csv_delimiter; +}; + +class PcmIioDisplayBuilder : public PcmIioOutputBuilder { +public: + PcmIioDisplayBuilder(vector& iios, vector& ctrs, PCIDB& pciDB, + const PCIeEventNameMap& nameMap) : PcmIioOutputBuilder(iios, ctrs, nameMap), m_pciDB(pciDB) {} + + ~PcmIioDisplayBuilder() = default; + + vector buildDisplayBuffer() override; +private: + PCIDB& m_pciDB; +}; class IPlatformMapping { private: @@ -657,9 +693,7 @@ void initializeIIOStructure( std::vector& iios ); void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap); -typedef map>> PCIeEventNameMap_t; - -void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap); +void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap); -bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap_t& nameMap ); +bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap ); diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index 9129f3c2..b4ee60b6 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -143,7 +143,7 @@ int mainThrows(int argc, char * argv[]) std::vector iios; iio_evt_parse_context evt_ctx; // Map with metrics names. - PCIeEventNameMap_t nameMap; + PCIeEventNameMap nameMap; if ( !initializePCIeBWCounters( iios, evt_ctx, nameMap ) ) exit(EXIT_FAILURE); @@ -160,12 +160,17 @@ int mainThrows(int argc, char * argv[]) print_nameMap(nameMap); #endif + std::unique_ptr displayBuilder; + if (csv) { + displayBuilder = std::make_unique(iios, evt_ctx.ctrs, nameMap, human_readable, show_root_port, csv_delimiter); + } else { + displayBuilder = std::make_unique(iios, evt_ctx.ctrs, pciDB, nameMap); + } + mainLoop([&]() { collect_data(m, delay, iios, evt_ctx.ctrs); - vector display_buffer = csv ? - build_csv(iios, evt_ctx.ctrs, human_readable, show_root_port, csv_delimiter, nameMap) : - build_display(iios, evt_ctx.ctrs, pciDB, nameMap); + vector display_buffer = displayBuilder->buildDisplayBuffer(); display(display_buffer, *output); return true; }); diff --git a/src/pcm-sensor-server.cpp b/src/pcm-sensor-server.cpp index d115818c..f3ba4aae 100644 --- a/src/pcm-sensor-server.cpp +++ b/src/pcm-sensor-server.cpp @@ -4061,10 +4061,10 @@ int mainThrows(int argc, char * argv[]) { std::vector iios; iio_evt_parse_context evt_ctx; std::string ev_file_name; - // Map with metrics names. - PCIeEventNameMap_t nameMap; // TODO: add check for IIO support before trying to initialize the pmu + // Map with metrics names. + // PCIeEventNameMap nameMap; // Otto: re-add this check when there is support for IIO and do it properly, seems to fail for some reason, see #788 // if ( !initializePCIeBWCounters( iios, evt_ctx, nameMap ) ) // { diff --git a/src/utils.cpp b/src/utils.cpp index dc5de539..499aa5b8 100644 --- a/src/utils.cpp +++ b/src/utils.cpp @@ -1152,19 +1152,19 @@ void display(const std::vector &buff, std::ostream& stream) stream << std::flush; } -void print_nameMap(std::map>>& nameMap) +void print_nameMap(const PCIeEventNameMap& nameMap) { - for (std::map>>::const_iterator iunit = nameMap.begin(); iunit != nameMap.end(); ++iunit) + for (const auto& iunit : nameMap) { - std::string h_name = iunit->first; - std::pair> value = iunit->second; + const std::string& h_name = iunit.first; + const auto& value = iunit.second; uint32_t hid = value.first; - std::map vMap = value.second; + const auto& vMap = value.second; std::cout << "H name: " << h_name << " id =" << hid << " vMap size:" << vMap.size() << "\n"; - for (std::map::const_iterator junit = vMap.begin(); junit != vMap.end(); ++junit) + for (const auto& junit : vMap) { - std::string v_name = junit->first; - uint32_t vid = junit->second; + const std::string& v_name = junit.first; + uint32_t vid = junit.second; std::cout << "V name: " << v_name << " id =" << vid << "\n"; } } @@ -1187,7 +1187,7 @@ void print_nameMap(std::map &ofm, int (*pfn_evtcb)(evt_cb_type, void *, counter &, std::map &, std::string, uint64), - void *evtcb_ctx, std::map>> &nameMap) + void *evtcb_ctx, PCIeEventNameMap& nameMap) { struct counter ctr; @@ -1226,11 +1226,9 @@ int load_events(const std::string &fn, std::map &ofm, } /* Ignore anyline with # */ - if (line.find("#") != std::string::npos) - continue; + if (line.find("#") != std::string::npos) continue; /* If line does not have any deliminator, we ignore it as well */ - if (line.find("=") == std::string::npos) - continue; + if (line.find("=") == std::string::npos) continue; std::string h_name, v_name; std::istringstream iss(line); @@ -1256,11 +1254,11 @@ int load_events(const std::string &fn, std::map &ofm, if (nameMap.find(h_name) == nameMap.end()) { /* It's a new horizontal event name */ - uint32_t next_h_id = (uint32_t)nameMap.size(); - std::pair> nameMap_value(next_h_id, std::map()); + auto next_h_id = static_cast(nameMap.size()); + auto nameMap_value = std::make_pair(next_h_id, CounterValueMap()); nameMap[h_name] = nameMap_value; } - ctr.h_id = (uint32_t)nameMap.size() - 1; + ctr.h_id = static_cast(nameMap.size()) - 1; DBG(2, "h_name:" , ctr.h_event_name , "h_id: ", ctr.h_id); break; case PCM::V_EVENT_NAME: @@ -1269,10 +1267,10 @@ int load_events(const std::string &fn, std::map &ofm, ctr.v_event_name = v_name; //XXX: If h_name comes after v_name, we'll have a problem. //XXX: It's very weird, I forgot to assign nameMap[h_name] = nameMap_value earlier (:298), but this part still works? - std::map &v_nameMap = nameMap[h_name].second; + auto& v_nameMap = nameMap[h_name].second; if (v_nameMap.find(v_name) == v_nameMap.end()) { - v_nameMap[v_name] = (unsigned int)v_nameMap.size() - 1; + v_nameMap[v_name] = static_cast(v_nameMap.size()) - 1; DBG(2, "v_name(" , v_name , ")=", v_nameMap[v_name]); } else @@ -1325,7 +1323,7 @@ int load_events(const std::string &fn, std::map &ofm, int (*pfn_evtcb)(evt_cb_type, void *, counter &, std::map &, std::string, uint64), void *evtcb_ctx) { - std::map>> nm; + PCIeEventNameMap nm; return load_events(fn, ofm, pfn_evtcb, evtcb_ctx, nm); } diff --git a/src/utils.h b/src/utils.h index 5a0f4f16..2bf1d5ea 100644 --- a/src/utils.h +++ b/src/utils.h @@ -609,6 +609,13 @@ typedef enum{ EVT_LINE_COMPLETE }evt_cb_type; +using EventName = std::string; +using CounterName = std::string; + +using CounterValueMap = std::unordered_map; +using EventDefinition = std::pair; +using PCIeEventNameMap = std::unordered_map; + void getMCFGRecords(std::vector& mcfg); std::string dos2unix(std::string in); bool isRegisterEvent(const std::string & pmu); @@ -620,10 +627,10 @@ std::string build_csv_row(const std::vector& chunks, const std::str std::vector prepare_data(const std::vector &values, const std::vector &headers); void display(const std::vector &buff, std::ostream& stream); -void print_nameMap(std::map>>& nameMap); +void print_nameMap(const PCIeEventNameMap& nameMap); int load_events(const std::string &fn, std::map &ofm, int (*p_fn_evtcb)(evt_cb_type, void *, counter &, std::map &, std::string, uint64), - void *evtcb_ctx, std::map>> &nameMap); + void *evtcb_ctx, PCIeEventNameMap& nameMap); int load_events(const std::string &fn, std::map &ofm, int (*pfn_evtcb)(evt_cb_type, void *, counter &, std::map &, std::string, uint64), void *evtcb_ctx); diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp index 3d0a56d7..e1c5d745 100644 --- a/tests/utests/pcm-iio-utest.cpp +++ b/tests/utests/pcm-iio-utest.cpp @@ -25,7 +25,7 @@ class LoadEventsTest : public ::testing::Test { std::map opcodeFieldMap; iio_evt_parse_context evt_ctx; - PCIeEventNameMap_t nameMap; + PCIeEventNameMap nameMap; }; // Structure to hold expected event data from file From 04384c1649d9d87ad2c013cf144e3fc4d4902b1c Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 06:40:22 -0700 Subject: [PATCH 09/54] Create wrapper for PCM IIO configs --- src/pcm-iio-pmu.cpp | 34 ++++++++++++++--------------- src/pcm-iio-pmu.h | 43 +++++++++++++++++++++++-------------- src/pcm-iio.cpp | 52 +++++++++++++++++---------------------------- 3 files changed, 64 insertions(+), 65 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 5ae00d21..83f58836 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -106,7 +106,7 @@ std::string get_root_port_dev(const bool show_root_port, int part_id, const pcm void PcmIioCsvBuilder::insertTimeStamp(vector & out, CsvOutputType type) { std::string dateTime; - printDateForCSV(type, m_csv_delimiter, &dateTime); + printDateForCSV(type, m_config.display.csv_delimiter, &dateTime); // remove last delimiter dateTime.pop_back(); out.insert(out.begin(), dateTime); @@ -116,27 +116,27 @@ vector PcmIioCsvBuilder::buildDisplayBuffer() { vector result; vector current_row; - auto header = combine_stack_name_and_counter_names("Part", m_nameMap); + auto header = combine_stack_name_and_counter_names("Part", m_config.pmu_config.pcieEventNameMap); header.insert(header.begin(), "Name"); - if (m_show_root_port) + if (m_config.display.show_root_port) header.insert(header.begin(), "Root Port"); header.insert(header.begin(), "Socket"); insertTimeStamp(header, CsvOutputType::Header2); - result.push_back(build_csv_row(header, m_csv_delimiter)); + result.push_back(build_csv_row(header, m_config.display.csv_delimiter)); std::map> v_sort; //re-organize data collection to be row wise size_t max_name_width = 0; - for (auto counter = m_ctrs.begin(); counter != m_ctrs.end(); ++counter) { + for (auto counter = m_config.pmu_config.evt_ctx.ctrs.begin(); counter != m_config.pmu_config.evt_ctx.ctrs.end(); ++counter) { v_sort[counter->v_id][counter->h_id] = &(*counter); max_name_width = (std::max)(max_name_width, counter->v_event_name.size()); } - for (auto socket = m_iios.cbegin(); socket != m_iios.cend(); ++socket) { + for (auto socket = m_config.pmu_config.iios.cbegin(); socket != m_config.pmu_config.iios.cend(); ++socket) { for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { const std::string socket_name = "Socket" + std::to_string(socket->socket_id); std::string stack_name = stack->stack_name; - if (!m_human_readable) { + if (!m_config.display.human_readable) { stack_name.erase(stack_name.find_last_not_of(' ') + 1); } @@ -150,14 +150,14 @@ vector PcmIioCsvBuilder::buildDisplayBuffer() uint32_t vv_id = vunit->first; vector h_data; string v_name = h_array[0]->v_event_name; - if (m_human_readable) { + if (m_config.display.human_readable) { v_name += string(max_name_width - (v_name.size()), ' '); } current_row.clear(); current_row.push_back(socket_name); - if (m_show_root_port) { - auto pci_dev = get_root_port_dev(m_show_root_port, part_id, &(*stack)); + if (m_config.display.show_root_port) { + auto pci_dev = get_root_port_dev(m_config.display.show_root_port, part_id, &(*stack)); current_row.push_back(pci_dev); } current_row.push_back(stack_name); @@ -165,10 +165,10 @@ vector PcmIioCsvBuilder::buildDisplayBuffer() for (map::const_iterator hunit = h_array.cbegin(); hunit != h_array.cend(); ++hunit) { uint32_t hh_id = hunit->first; uint64_t raw_data = hunit->second->data[0][socket->socket_id][stack_id][std::pair(hh_id,vv_id)]; - current_row.push_back(m_human_readable ? unit_format(raw_data) : std::to_string(raw_data)); + current_row.push_back(m_config.display.human_readable ? unit_format(raw_data) : std::to_string(raw_data)); } insertTimeStamp(current_row, CsvOutputType::Data); - result.push_back(build_csv_row(current_row, m_csv_delimiter)); + result.push_back(build_csv_row(current_row, m_config.display.csv_delimiter)); } } } @@ -182,11 +182,11 @@ vector PcmIioDisplayBuilder::buildDisplayBuffer() vector data; uint64_t header_width; string row; - for (auto socket = m_iios.cbegin(); socket != m_iios.cend(); ++socket) { + for (auto socket = m_config.pmu_config.iios.cbegin(); socket != m_config.pmu_config.iios.cend(); ++socket) { buffer.push_back("Socket" + std::to_string(socket->socket_id)); for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { auto stack_id = stack->iio_unit_id; - headers = combine_stack_name_and_counter_names(stack->stack_name, m_nameMap); + headers = combine_stack_name_and_counter_names(stack->stack_name, m_config.pmu_config.pcieEventNameMap); //Print first row row = std::accumulate(headers.begin(), headers.end(), string(" "), a_header_footer); header_width = row.size(); @@ -200,7 +200,7 @@ vector PcmIioDisplayBuilder::buildDisplayBuffer() //Print data std::map> v_sort; //re-organize data collection to be row wise - for (std::vector::iterator counter = m_ctrs.begin(); counter != m_ctrs.end(); ++counter) { + for (std::vector::iterator counter = m_config.pmu_config.evt_ctx.ctrs.begin(); counter != m_config.pmu_config.evt_ctx.ctrs.end(); ++counter) { v_sort[counter->v_id][counter->h_id] = &(*counter); } for (std::map>::const_iterator vunit = v_sort.cbegin(); vunit != v_sort.cend(); ++vunit) { @@ -226,10 +226,10 @@ vector PcmIioDisplayBuilder::buildDisplayBuffer() for (const auto& part : stack->parts) { uint8_t level = 1; for (const auto& pci_device : part.child_pci_devs) { - row = build_pci_header(m_pciDB, (uint32_t)header_width, pci_device, -1, level); + row = build_pci_header(m_config.pciDB, (uint32_t)header_width, pci_device, -1, level); buffer.push_back(row); if (pci_device.hasChildDevices()) { - build_pci_tree(buffer, m_pciDB, (uint32_t)header_width, pci_device, -1, level + 1); + build_pci_tree(buffer, m_config.pciDB, (uint32_t)header_width, pci_device, -1, level + 1); } else if (pci_device.header_type == 1) { level++; } diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index b07e10a6..46d1f265 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -503,47 +503,58 @@ void build_pci_tree(vector &buffer, const PCIDB & pciDB, uint32_t column std::string get_root_port_dev(const bool show_root_port, int part_id, const pcm::iio_stack *stack); +struct pcm_iio_display_config { + bool csv = false; + bool human_readable = false; + bool show_root_port = false; + bool list = false; + std::string csv_delimiter = ","; + std::string output_file = ""; +}; + +struct pcm_iio_pmu_config { + double delay = PCM_DELAY_DEFAULT; + // Map with metrics names. + PCIeEventNameMap pcieEventNameMap; + vector iios; + iio_evt_parse_context evt_ctx; +}; + +struct pcm_iio_config { + struct pcm_iio_display_config display; + struct pcm_iio_pmu_config pmu_config; + PCIDB pciDB; +}; + class PcmIioOutputBuilder { public: - PcmIioOutputBuilder(vector& iios, vector& ctrs, const PCIeEventNameMap& nameMap) - : m_iios(iios), m_ctrs(ctrs), m_nameMap(nameMap) {} + PcmIioOutputBuilder(struct pcm_iio_config& config) : m_config(config) {} virtual ~PcmIioOutputBuilder() = default; virtual vector buildDisplayBuffer() = 0; protected: - vector& m_iios; - vector& m_ctrs; - const PCIeEventNameMap& m_nameMap; + struct pcm_iio_config& m_config; }; class PcmIioCsvBuilder : public PcmIioOutputBuilder { public: - PcmIioCsvBuilder(vector& iios, vector& ctrs, const PCIeEventNameMap& nameMap, - const bool human_readable, const bool show_root_port, const std::string& csv_delimiter) - : PcmIioOutputBuilder(iios, ctrs, nameMap), m_human_readable(human_readable), m_show_root_port(show_root_port), m_csv_delimiter(csv_delimiter) {} + PcmIioCsvBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {} ~PcmIioCsvBuilder() = default; vector buildDisplayBuffer() override; private: void insertTimeStamp(vector & out, CsvOutputType type); - - bool m_human_readable; - bool m_show_root_port; - std::string m_csv_delimiter; }; class PcmIioDisplayBuilder : public PcmIioOutputBuilder { public: - PcmIioDisplayBuilder(vector& iios, vector& ctrs, PCIDB& pciDB, - const PCIeEventNameMap& nameMap) : PcmIioOutputBuilder(iios, ctrs, nameMap), m_pciDB(pciDB) {} + PcmIioDisplayBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {} ~PcmIioDisplayBuilder() = default; vector buildDisplayBuffer() override; -private: - PCIDB& m_pciDB; }; class IPlatformMapping { diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index b4ee60b6..b4c040a9 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -78,13 +78,7 @@ int mainThrows(int argc, char * argv[]) string program = string(argv[0]); - bool csv = false; - bool human_readable = false; - bool show_root_port = false; - std::string csv_delimiter = ","; - std::string output_file; - double delay = PCM_DELAY_DEFAULT; - bool list = false; + struct pcm_iio_config config; MainLoop mainLoop; while (argc > 1) { @@ -100,29 +94,29 @@ int mainThrows(int argc, char * argv[]) continue; } else if (extract_argument_value(*argv, {"-csv-delimiter", "/csv-delimiter"}, arg_value)) { - csv_delimiter = std::move(arg_value); + config.display.csv_delimiter = std::move(arg_value); } else if (check_argument_equals(*argv, {"-csv", "/csv"})) { - csv = true; + config.display.csv = true; } else if (extract_argument_value(*argv, {"-csv", "/csv"}, arg_value)) { - csv = true; - output_file = std::move(arg_value); + config.display.csv = true; + config.display.output_file = std::move(arg_value); } else if (check_argument_equals(*argv, {"-human-readable", "/human-readable"})) { - human_readable = true; + config.display.human_readable = true; } else if (check_argument_equals(*argv, {"-list", "--list"})) { - list = true; + config.display.list = true; } else if (check_argument_equals(*argv, {"-root-port", "/root-port"})) { - show_root_port = true; + config.display.show_root_port = true; } else if (mainLoop.parseArg(*argv)) { continue; } else { - delay = parse_delay(*argv, program, (print_usage_func)print_usage); + config.pmu_config.delay = parse_delay(*argv, program, (print_usage_func)print_usage); continue; } } @@ -135,41 +129,35 @@ int mainThrows(int argc, char * argv[]) std::ostream* output = &std::cout; std::fstream file_stream; - if (!output_file.empty()) { - file_stream.open(output_file.c_str(), std::ios_base::out); + if (!config.display.output_file.empty()) { + file_stream.open(config.display.output_file.c_str(), std::ios_base::out); output = &file_stream; } - std::vector iios; - iio_evt_parse_context evt_ctx; - // Map with metrics names. - PCIeEventNameMap nameMap; - - if ( !initializePCIeBWCounters( iios, evt_ctx, nameMap ) ) + if ( !initializePCIeBWCounters( config.pmu_config.iios, config.pmu_config.evt_ctx, config.pmu_config.pcieEventNameMap ) ) exit(EXIT_FAILURE); - PCIDB pciDB; - load_PCIDB(pciDB); + load_PCIDB(config.pciDB); - if (list) { - print_PCIeMapping(iios, pciDB, *output); + if (config.display.list) { + print_PCIeMapping(config.pmu_config.iios, config.pciDB, *output); return 0; } #ifdef PCM_DEBUG - print_nameMap(nameMap); + print_nameMap(config.pmu_config.nameMap); #endif std::unique_ptr displayBuilder; - if (csv) { - displayBuilder = std::make_unique(iios, evt_ctx.ctrs, nameMap, human_readable, show_root_port, csv_delimiter); + if (config.display.csv) { + displayBuilder = std::make_unique(config); } else { - displayBuilder = std::make_unique(iios, evt_ctx.ctrs, pciDB, nameMap); + displayBuilder = std::make_unique(config); } mainLoop([&]() { - collect_data(m, delay, iios, evt_ctx.ctrs); + collect_data(m, config.pmu_config.delay, config.pmu_config.iios, config.pmu_config.evt_ctx.ctrs); vector display_buffer = displayBuilder->buildDisplayBuffer(); display(display_buffer, *output); return true; From ca5a6cd9f4e7f176bc870d82156daf6fca09099d Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 06:45:40 -0700 Subject: [PATCH 10/54] Move parse arguments procedure to separate function --- src/pcm-iio.cpp | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index b4c040a9..a0a6f540 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -63,24 +63,9 @@ void print_usage(const string& progname) cout << "\n"; } -PCM_MAIN_NOTHROW; - -int mainThrows(int argc, char * argv[]) +void parse_arguments(int argc, char * argv[], struct pcm_iio_config& config, MainLoop& mainLoop) { - if (print_version(argc, argv)) - exit(EXIT_SUCCESS); - - null_stream nullStream; - check_and_set_silent(argc, argv, nullStream); - - std::cout << "\n Intel(r) Performance Counter Monitor " << PCM_VERSION << "\n"; - std::cout << "\n This utility measures IIO information\n\n"; - - string program = string(argv[0]); - - struct pcm_iio_config config; - MainLoop mainLoop; - + const string program = string(argv[0]); while (argc > 1) { argv++; argc--; @@ -120,6 +105,25 @@ int mainThrows(int argc, char * argv[]) continue; } } +} + +PCM_MAIN_NOTHROW; + +int mainThrows(int argc, char * argv[]) +{ + if (print_version(argc, argv)) + exit(EXIT_SUCCESS); + + null_stream nullStream; + check_and_set_silent(argc, argv, nullStream); + + std::cout << "\n Intel(r) Performance Counter Monitor " << PCM_VERSION << "\n"; + std::cout << "\n This utility measures IIO information\n\n"; + + struct pcm_iio_config config; + MainLoop mainLoop; + + parse_arguments(argc, argv, config, mainLoop); set_signal_handlers(); From b95caabd9b1a2c278a31559a3ecbe762d771c873 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 06:54:33 -0700 Subject: [PATCH 11/54] Use iio_pmu_config in initializePCIeBWCounters --- src/pcm-iio-pmu.cpp | 6 +++--- src/pcm-iio-pmu.h | 2 +- src/pcm-iio.cpp | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 83f58836..9a79ae88 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1524,7 +1524,7 @@ void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventN results.resize(m->getNumSockets(), stack_content(m->getMaxNumOfIIOStacks(), ctr_data())); } -bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap ) +bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) { PCM * m = PCM::getInstance(); if (!m->IIOEventsAvailable()) @@ -1533,9 +1533,9 @@ bool initializePCIeBWCounters( std::vector& iios, i return false; } - initializeIIOStructure( iios ); + initializeIIOStructure(pmu_config.iios); - setupPCIeEventContextAndNameMap( evt_ctx, nameMap ); + setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap); return true; } diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 46d1f265..757be12c 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -706,5 +706,5 @@ void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap); void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap); -bool initializePCIeBWCounters( std::vector& iios, iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap ); +bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config); diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index a0a6f540..253b1873 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -138,7 +138,7 @@ int mainThrows(int argc, char * argv[]) output = &file_stream; } - if ( !initializePCIeBWCounters( config.pmu_config.iios, config.pmu_config.evt_ctx, config.pmu_config.pcieEventNameMap ) ) + if (!initializePCIeBWCounters(config.pmu_config)) exit(EXIT_FAILURE); load_PCIDB(config.pciDB); From c5bb03705ab4fb3d3e18093e2d416cd4b3c05adc Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 07:10:18 -0700 Subject: [PATCH 12/54] Use iio_pmu_config in collect_data() --- src/pcm-iio-pmu.cpp | 8 ++++---- src/pcm-iio-pmu.h | 2 +- src/pcm-iio.cpp | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 9a79ae88..f4ceb8e1 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1453,12 +1453,12 @@ result_content get_IIO_Samples(PCM *m, const std::vector& iios, vector& ctrs) +void collect_data(PCM *m, struct pcm_iio_pmu_config& config) { - const uint32_t delay_ms = uint32_t(delay * 1000 / ctrs.size()); - for (auto counter = ctrs.begin(); counter != ctrs.end(); ++counter) { + const uint32_t delay_ms = uint32_t(config.delay * 1000 / config.evt_ctx.ctrs.size()); + for (auto counter = config.evt_ctx.ctrs.begin(); counter != config.evt_ctx.ctrs.end(); ++counter) { counter->data.clear(); - result_content sample = get_IIO_Samples(m, iios, *counter, delay_ms); + result_content sample = get_IIO_Samples(m, config.iios, *counter, delay_ms); counter->data.push_back(sample); } } diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 757be12c..e5e6a985 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -698,7 +698,7 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, result_content get_IIO_Samples(PCM *m, const std::vector& iios, const struct iio_counter & ctr, uint32_t delay_ms); -void collect_data(PCM *m, const double delay, vector& iios, vector& ctrs); +void collect_data(PCM *m, struct pcm_iio_pmu_config& config); void initializeIIOStructure( std::vector& iios ); diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index 253b1873..78b9b87c 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -161,7 +161,7 @@ int mainThrows(int argc, char * argv[]) mainLoop([&]() { - collect_data(m, config.pmu_config.delay, config.pmu_config.iios, config.pmu_config.evt_ctx.ctrs); + collect_data(m, config.pmu_config); vector display_buffer = displayBuilder->buildDisplayBuffer(); display(display_buffer, *output); return true; From 398f13e0f657ea6364a7b3d4b4c7586294db9e4e Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 07:28:17 -0700 Subject: [PATCH 13/54] Create factory method to get display builder --- src/pcm-iio-pmu.cpp | 31 +++++++++++++++++++++++++++++++ src/pcm-iio-pmu.h | 20 +------------------- src/pcm-iio.cpp | 7 +------ 3 files changed, 33 insertions(+), 25 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index f4ceb8e1..b31d588c 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -103,6 +103,17 @@ std::string get_root_port_dev(const bool show_root_port, int part_id, const pcm } +class PcmIioCsvBuilder : public PcmIioOutputBuilder { +public: + PcmIioCsvBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {} + + ~PcmIioCsvBuilder() = default; + + vector buildDisplayBuffer() override; +private: + void insertTimeStamp(vector & out, CsvOutputType type); +}; + void PcmIioCsvBuilder::insertTimeStamp(vector & out, CsvOutputType type) { std::string dateTime; @@ -175,6 +186,15 @@ vector PcmIioCsvBuilder::buildDisplayBuffer() return result; } +class PcmIioDisplayBuilder : public PcmIioOutputBuilder { +public: + PcmIioDisplayBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {} + + ~PcmIioDisplayBuilder() = default; + + vector buildDisplayBuffer() override; +}; + vector PcmIioDisplayBuilder::buildDisplayBuffer() { vector buffer; @@ -243,6 +263,17 @@ vector PcmIioDisplayBuilder::buildDisplayBuffer() return buffer; } +std::unique_ptr getDisplayBuilder(struct pcm_iio_config& config) +{ + std::unique_ptr displayBuilder; + if (config.display.csv) { + displayBuilder = std::make_unique(config); + } else { + displayBuilder = std::make_unique(config); + } + return displayBuilder; +} + void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) { for (uint16_t bus = 0; bus < 256; bus++) { diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index e5e6a985..2983e6ac 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -537,25 +537,7 @@ class PcmIioOutputBuilder { struct pcm_iio_config& m_config; }; -class PcmIioCsvBuilder : public PcmIioOutputBuilder { -public: - PcmIioCsvBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {} - - ~PcmIioCsvBuilder() = default; - - vector buildDisplayBuffer() override; -private: - void insertTimeStamp(vector & out, CsvOutputType type); -}; - -class PcmIioDisplayBuilder : public PcmIioOutputBuilder { -public: - PcmIioDisplayBuilder(struct pcm_iio_config& config) : PcmIioOutputBuilder(config) {} - - ~PcmIioDisplayBuilder() = default; - - vector buildDisplayBuffer() override; -}; +std::unique_ptr getDisplayBuilder(struct pcm_iio_config& config); class IPlatformMapping { private: diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index 78b9b87c..191cb16d 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -152,12 +152,7 @@ int mainThrows(int argc, char * argv[]) print_nameMap(config.pmu_config.nameMap); #endif - std::unique_ptr displayBuilder; - if (config.display.csv) { - displayBuilder = std::make_unique(config); - } else { - displayBuilder = std::make_unique(config); - } + auto displayBuilder = getDisplayBuilder(config); mainLoop([&]() { From bab493172437da83c6bd6e27cb7bf450db93d884 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 08:55:02 -0700 Subject: [PATCH 14/54] Create wrapper class for collect_data function --- src/pcm-iio-pmu.cpp | 40 ++++++++++++++++++++-------------------- src/pcm-iio-pmu.h | 13 +++++++++++-- src/pcm-iio.cpp | 3 ++- 3 files changed, 33 insertions(+), 23 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index b31d588c..6394f7d4 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1450,30 +1450,40 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, return 0; } -result_content get_IIO_Samples(PCM *m, const std::vector& iios, const struct iio_counter & ctr, uint32_t delay_ms) +void PcmIioDataCollector::collect_data() +{ + const uint32_t delay_ms = uint32_t(m_config.delay * 1000 / m_config.evt_ctx.ctrs.size()); + for (auto counter = m_config.evt_ctx.ctrs.begin(); counter != m_config.evt_ctx.ctrs.end(); ++counter) { + counter->data.clear(); + result_content sample = get_IIO_Samples(*counter, delay_ms); + counter->data.push_back(sample); + } +} + +result_content PcmIioDataCollector::get_IIO_Samples(const struct iio_counter & ctr, uint32_t delay_ms) { IIOCounterState *before, *after; uint64 rawEvents[4] = {0}; - std::unique_ptr pccr(get_ccr(m, const_cast(ctr).ccr)); + std::unique_ptr pccr(get_ccr(m_pcm, const_cast(ctr).ccr)); rawEvents[ctr.idx] = pccr->get_ccr_value(); - const int stacks_count = (int)m->getMaxNumOfIIOStacks(); - before = new IIOCounterState[iios.size() * stacks_count]; - after = new IIOCounterState[iios.size() * stacks_count]; + const int stacks_count = (int)m_pcm->getMaxNumOfIIOStacks(); + before = new IIOCounterState[m_config.iios.size() * stacks_count]; + after = new IIOCounterState[m_config.iios.size() * stacks_count]; - m->programIIOCounters(rawEvents); - for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) { + m_pcm->programIIOCounters(rawEvents); + for (auto socket = m_config.iios.cbegin(); socket != m_config.iios.cend(); ++socket) { for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { auto iio_unit_id = stack->iio_unit_id; uint32_t idx = (uint32_t)stacks_count * socket->socket_id + iio_unit_id; - before[idx] = m->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx); + before[idx] = m_pcm->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx); } } MySleepMs(delay_ms); - for (auto socket = iios.cbegin(); socket != iios.cend(); ++socket) { + for (auto socket = m_config.iios.cbegin(); socket != m_config.iios.cend(); ++socket) { for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { auto iio_unit_id = stack->iio_unit_id; uint32_t idx = (uint32_t)stacks_count * socket->socket_id + iio_unit_id; - after[idx] = m->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx); + after[idx] = m_pcm->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx); uint64_t raw_result = getNumberOfEvents(before[idx], after[idx]); uint64_t trans_result = uint64_t (raw_result * ctr.multiplier / (double) ctr.divider * (1000 / (double) delay_ms)); results[socket->socket_id][iio_unit_id][std::pair(ctr.h_id,ctr.v_id)] = trans_result; @@ -1484,16 +1494,6 @@ result_content get_IIO_Samples(PCM *m, const std::vectordata.clear(); - result_content sample = get_IIO_Samples(m, config.iios, *counter, delay_ms); - counter->data.push_back(sample); - } -} - void initializeIIOStructure( std::vector& iios ) { PCM * m = PCM::getInstance(); diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 2983e6ac..15286c87 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -678,9 +678,18 @@ class KasseyvillePlatform: public Xeon6thNextGenPlatform { int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map &ofm, std::string key, uint64 numValue); -result_content get_IIO_Samples(PCM *m, const std::vector& iios, const struct iio_counter & ctr, uint32_t delay_ms); +class PcmIioDataCollector { +public: + PcmIioDataCollector(struct pcm_iio_pmu_config& config) : m_config(config) {} + ~PcmIioDataCollector() = default; + + void collect_data(); +private: + struct pcm_iio_pmu_config& m_config; + PCM *m_pcm; -void collect_data(PCM *m, struct pcm_iio_pmu_config& config); + result_content get_IIO_Samples(const struct iio_counter & ctr, uint32_t delay_ms); +}; void initializeIIOStructure( std::vector& iios ); diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index 191cb16d..aeac9fe3 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -153,10 +153,11 @@ int mainThrows(int argc, char * argv[]) #endif auto displayBuilder = getDisplayBuilder(config); + auto collector = std::make_unique(config.pmu_config); mainLoop([&]() { - collect_data(m, config.pmu_config); + collector->collect_data(); vector display_buffer = displayBuilder->buildDisplayBuffer(); display(display_buffer, *output); return true; From 7f06764b2c39367de6d6f09273ebf35476285007 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 08:31:35 -0700 Subject: [PATCH 15/54] Rename initializeIIOStructure to initializeIOStacksStructure --- src/pcm-iio-pmu.cpp | 4 ++-- src/pcm-iio-pmu.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 6394f7d4..8f5a0ddc 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1494,7 +1494,7 @@ result_content PcmIioDataCollector::get_IIO_Samples(const struct iio_counter & c return results; } -void initializeIIOStructure( std::vector& iios ) +void initializeIOStacksStructure( std::vector& iios ) { PCM * m = PCM::getInstance(); auto mapping = IPlatformMapping::getPlatformMapping(m->getCPUFamilyModel(), m->getNumSockets()); @@ -1564,7 +1564,7 @@ bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) return false; } - initializeIIOStructure(pmu_config.iios); + initializeIOStacksStructure(pmu_config.iios); setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap); diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 15286c87..a79a032e 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -691,7 +691,7 @@ class PcmIioDataCollector { result_content get_IIO_Samples(const struct iio_counter & ctr, uint32_t delay_ms); }; -void initializeIIOStructure( std::vector& iios ); +void initializeIOStacksStructure( std::vector& iios ); void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap); From 4615414f2a936cd808ea030ba334ccf04e7299e7 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 09:01:59 -0700 Subject: [PATCH 16/54] Simplify PcmIioDataCollector --- src/pcm-iio-pmu.cpp | 62 ++++++++++++++++++++++++--------------------- src/pcm-iio-pmu.h | 13 +++++++--- src/pcm-iio.cpp | 4 +-- 3 files changed, 44 insertions(+), 35 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 8f5a0ddc..efd13fc3 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1450,47 +1450,51 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, return 0; } -void PcmIioDataCollector::collect_data() +PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) : m_config(config) { - const uint32_t delay_ms = uint32_t(m_config.delay * 1000 / m_config.evt_ctx.ctrs.size()); - for (auto counter = m_config.evt_ctx.ctrs.begin(); counter != m_config.evt_ctx.ctrs.end(); ++counter) { - counter->data.clear(); - result_content sample = get_IIO_Samples(*counter, delay_ms); - counter->data.push_back(sample); + m_pcm = PCM::getInstance(); + m_delay_ms = static_cast(m_config.delay * 1000 / m_config.evt_ctx.ctrs.size()); + m_stacks_count = m_pcm->getMaxNumOfIIOStacks(); + m_time_scaling_factor = 1000.0 / m_delay_ms; + + m_before = std::make_unique(m_config.iios.size() * m_stacks_count); + m_after = std::make_unique(m_config.iios.size() * m_stacks_count); +} + +void PcmIioDataCollector::collectData() +{ + for (auto& counter : m_config.evt_ctx.ctrs) { + counter.data.clear(); + result_content sample = getSample(counter); + counter.data.push_back(sample); } } -result_content PcmIioDataCollector::get_IIO_Samples(const struct iio_counter & ctr, uint32_t delay_ms) +result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) { - IIOCounterState *before, *after; - uint64 rawEvents[4] = {0}; - std::unique_ptr pccr(get_ccr(m_pcm, const_cast(ctr).ccr)); + uint64 rawEvents[COUNTERS_NUMBER] = {0}; + std::unique_ptr pccr(get_ccr(m_pcm, ctr.ccr)); rawEvents[ctr.idx] = pccr->get_ccr_value(); - const int stacks_count = (int)m_pcm->getMaxNumOfIIOStacks(); - before = new IIOCounterState[m_config.iios.size() * stacks_count]; - after = new IIOCounterState[m_config.iios.size() * stacks_count]; m_pcm->programIIOCounters(rawEvents); - for (auto socket = m_config.iios.cbegin(); socket != m_config.iios.cend(); ++socket) { - for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { - auto iio_unit_id = stack->iio_unit_id; - uint32_t idx = (uint32_t)stacks_count * socket->socket_id + iio_unit_id; - before[idx] = m_pcm->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx); + for (const auto& socket : m_config.iios) { + for (const auto& stack : socket.stacks) { + auto iio_unit_id = stack.iio_unit_id; + uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; + m_before[idx] = m_pcm->getIIOCounterState(socket.socket_id, iio_unit_id, ctr.idx); } } - MySleepMs(delay_ms); - for (auto socket = m_config.iios.cbegin(); socket != m_config.iios.cend(); ++socket) { - for (auto stack = socket->stacks.cbegin(); stack != socket->stacks.cend(); ++stack) { - auto iio_unit_id = stack->iio_unit_id; - uint32_t idx = (uint32_t)stacks_count * socket->socket_id + iio_unit_id; - after[idx] = m_pcm->getIIOCounterState(socket->socket_id, iio_unit_id, ctr.idx); - uint64_t raw_result = getNumberOfEvents(before[idx], after[idx]); - uint64_t trans_result = uint64_t (raw_result * ctr.multiplier / (double) ctr.divider * (1000 / (double) delay_ms)); - results[socket->socket_id][iio_unit_id][std::pair(ctr.h_id,ctr.v_id)] = trans_result; + MySleepMs(m_delay_ms); + for (const auto& socket : m_config.iios) { + for (const auto& stack : socket.stacks) { + auto iio_unit_id = stack.iio_unit_id; + uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; + m_after[idx] = m_pcm->getIIOCounterState(socket.socket_id, iio_unit_id, ctr.idx); + uint64_t raw_result = getNumberOfEvents(m_before[idx], m_after[idx]); + uint64_t trans_result = static_cast(raw_result * ctr.multiplier / (double) ctr.divider * m_time_scaling_factor); + results[socket.socket_id][iio_unit_id][std::pair(ctr.h_id, ctr.v_id)] = trans_result; } } - deleteAndNullifyArray(before); - deleteAndNullifyArray(after); return results; } diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index a79a032e..2f97755a 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -680,15 +680,22 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, class PcmIioDataCollector { public: - PcmIioDataCollector(struct pcm_iio_pmu_config& config) : m_config(config) {} + PcmIioDataCollector(struct pcm_iio_pmu_config& config); ~PcmIioDataCollector() = default; - void collect_data(); + void collectData(); private: struct pcm_iio_pmu_config& m_config; PCM *m_pcm; + uint32_t m_delay_ms; + uint32_t m_stacks_count; + double m_time_scaling_factor; + std::unique_ptr m_before; + std::unique_ptr m_after; - result_content get_IIO_Samples(const struct iio_counter & ctr, uint32_t delay_ms); + result_content getSample(struct iio_counter & ctr); + + static constexpr int COUNTERS_NUMBER = 4; }; void initializeIOStacksStructure( std::vector& iios ); diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index aeac9fe3..7a044d7c 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -129,8 +129,6 @@ int mainThrows(int argc, char * argv[]) print_cpu_details(); - PCM * m = PCM::getInstance(); - std::ostream* output = &std::cout; std::fstream file_stream; if (!config.display.output_file.empty()) { @@ -157,7 +155,7 @@ int mainThrows(int argc, char * argv[]) mainLoop([&]() { - collector->collect_data(); + collector->collectData(); vector display_buffer = displayBuilder->buildDisplayBuffer(); display(display_buffer, *output); return true; From a5b0b76b73b41182530eaf5873997b6e646fb4ae Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 11:35:45 -0700 Subject: [PATCH 17/54] Remove extern declaration for result_content results --- src/pcm-iio-pmu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 2f97755a..1275d13c 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -486,8 +486,6 @@ struct iio_counter : public counter { std::vector data; }; -extern result_content results; - typedef struct { PCM *m; From 7a8e307905157c844112be9eb7b67131a6180d9d Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Mon, 29 Sep 2025 11:49:03 -0700 Subject: [PATCH 18/54] Move result_content to PcmIioDataCollector class --- src/pcm-iio-pmu.cpp | 10 ++++------ src/pcm-iio-pmu.h | 1 + 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index efd13fc3..dcd7ada1 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -7,8 +7,6 @@ #include "pcm-iio-pmu.h" -result_content results; - vector combine_stack_name_and_counter_names(string stack_name, const PCIeEventNameMap& nameMap) { vector v; @@ -1459,6 +1457,8 @@ PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) : m_ m_before = std::make_unique(m_config.iios.size() * m_stacks_count); m_after = std::make_unique(m_config.iios.size() * m_stacks_count); + + m_results.resize(m_pcm->getNumSockets(), stack_content(m_stacks_count, ctr_data())); } void PcmIioDataCollector::collectData() @@ -1492,10 +1492,10 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) m_after[idx] = m_pcm->getIIOCounterState(socket.socket_id, iio_unit_id, ctr.idx); uint64_t raw_result = getNumberOfEvents(m_before[idx], m_after[idx]); uint64_t trans_result = static_cast(raw_result * ctr.multiplier / (double) ctr.divider * m_time_scaling_factor); - results[socket.socket_id][iio_unit_id][std::pair(ctr.h_id, ctr.v_id)] = trans_result; + m_results[socket.socket_id][iio_unit_id][std::pair(ctr.h_id, ctr.v_id)] = trans_result; } } - return results; + return m_results; } void initializeIOStacksStructure( std::vector& iios ) @@ -1555,8 +1555,6 @@ void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventN std::cerr << "The event configuration file (" << ev_file_name << ") cannot be loaded. Please verify the file. Exiting.\n"; exit(EXIT_FAILURE); } - - results.resize(m->getNumSockets(), stack_content(m->getMaxNumOfIIOStacks(), ctr_data())); } bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 1275d13c..301ca8f1 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -690,6 +690,7 @@ class PcmIioDataCollector { double m_time_scaling_factor; std::unique_ptr m_before; std::unique_ptr m_after; + result_content m_results; result_content getSample(struct iio_counter & ctr); From 14007217dc07b7b3a7020eee7d76a7dc0090bb9c Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 00:43:58 -0700 Subject: [PATCH 19/54] Introduce PMU unit type --- src/cpucounters.h | 1 + src/opCode-6-106.txt | 82 +++++++++++++------------- src/opCode-6-108.txt | 82 +++++++++++++------------- src/opCode-6-134.txt | 82 +++++++++++++------------- src/opCode-6-143.txt | 82 +++++++++++++------------- src/opCode-6-173.txt | 82 +++++++++++++------------- src/opCode-6-174.txt | 82 +++++++++++++------------- src/opCode-6-175.txt | 82 +++++++++++++------------- src/opCode-6-182.txt | 82 +++++++++++++------------- src/opCode-6-207.txt | 82 +++++++++++++------------- src/opCode-6-85.txt | 46 +++++++-------- src/pcm-iio-pmu.cpp | 4 +- src/utils.cpp | 24 ++++++-- src/utils.h | 7 +++ tests/utests/pcm-iio-utest.cpp | 101 +++++++++++++++++++-------------- 15 files changed, 480 insertions(+), 441 deletions(-) diff --git a/src/cpucounters.h b/src/cpucounters.h index 2aafa00c..6ecefe50 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -957,6 +957,7 @@ class PCM_API PCM THRESH, CH_MASK, FC_MASK, + UNIT_TYPE, /* Below are not part of perfmon definition */ H_EVENT_NAME, V_EVENT_NAME, diff --git a/src/opCode-6-106.txt b/src/opCode-6-106.txt index 8de50f50..78016232 100644 --- a/src/opCode-6-106.txt +++ b/src/opCode-6-106.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-108.txt b/src/opCode-6-108.txt index 8de50f50..78016232 100644 --- a/src/opCode-6-108.txt +++ b/src/opCode-6-108.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-134.txt b/src/opCode-6-134.txt index b5256ce7..7ae1885e 100644 --- a/src/opCode-6-134.txt +++ b/src/opCode-6-134.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) -ctr=2,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total \ No newline at end of file +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total \ No newline at end of file diff --git a/src/opCode-6-143.txt b/src/opCode-6-143.txt index f2360e2a..426c4fa9 100644 --- a/src/opCode-6-143.txt +++ b/src/opCode-6-143.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-173.txt b/src/opCode-6-173.txt index c3ccfbc9..9e4636f1 100644 --- a/src/opCode-6-173.txt +++ b/src/opCode-6-173.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-174.txt b/src/opCode-6-174.txt index c3ccfbc9..9e4636f1 100644 --- a/src/opCode-6-174.txt +++ b/src/opCode-6-174.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-175.txt b/src/opCode-6-175.txt index c3ccfbc9..9e4636f1 100644 --- a/src/opCode-6-175.txt +++ b/src/opCode-6-175.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-182.txt b/src/opCode-6-182.txt index c3ccfbc9..9e4636f1 100644 --- a/src/opCode-6-182.txt +++ b/src/opCode-6-182.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-207.txt b/src/opCode-6-207.txt index f2360e2a..426c4fa9 100644 --- a/src/opCode-6-207.txt +++ b/src/opCode-6-207.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 # IOMMU events -ctr=0,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-85.txt b/src/opCode-6-85.txt index 34179b85..7289b384 100644 --- a/src/opCode-6-85.txt +++ b/src/opCode-6-85.txt @@ -1,26 +1,26 @@ # Inbound (PCIe device DMA into system) payload events -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part3 (4th x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part1 (2nd x4) -ctr=0,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=1,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part3 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part1 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part3 (4th x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part1 (2nd x4) -ctr=2,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=3,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part3 (4th x4) # VTd events -ctr=0,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Hit,vname=Total -ctr=1,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d CTXT Miss,vname=Total -ctr=3,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L1 Miss,vname=Total -ctr=0,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L2 Miss,vname=Total -ctr=1,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L3 Miss,vname=Total -ctr=2,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d Mem Read,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d CTXT Miss,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L1 Miss,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L2 Miss,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L3 Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d Mem Read,vname=Total diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index dcd7ada1..1e7a5b63 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1439,9 +1439,10 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, context->ctr.divider = base_ctr.divider; context->ctr.h_id = base_ctr.h_id; context->ctr.v_id = base_ctr.v_id; + context->ctr.type = base_ctr.type; DBG(4, "line parse OK, ctrcfg=0x", std::hex, context->ctr.ccr, ", h_event_name=", base_ctr.h_event_name, ", v_event_name=", base_ctr.v_event_name); DBG(4, ", h_id=0x", std::hex, base_ctr.h_id, ", v_id=0x", std::hex, base_ctr.v_id); - DBG(4, ", idx=0x", std::hex, base_ctr.idx, ", multiplier=0x", std::hex, base_ctr.multiplier, ", divider=0x", std::hex, base_ctr.divider, std::dec, "\n"); + DBG(4, ", idx=0x", std::hex, base_ctr.idx, ", multiplier=0x", std::hex, base_ctr.multiplier, ", divider=0x", std::hex, base_ctr.divider, std::dec, ", counter type = ", static_cast(base_ctr.type), "\n"); context->ctrs.push_back(context->ctr); } @@ -1531,6 +1532,7 @@ void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap) opcodeFieldMap["multiplier"] = PCM::MULTIPLIER; opcodeFieldMap["divider"] = PCM::DIVIDER; opcodeFieldMap["ctr"] = PCM::COUNTER_INDEX; + opcodeFieldMap["unit"] = PCM::UNIT_TYPE; } void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap) diff --git a/src/utils.cpp b/src/utils.cpp index 499aa5b8..29caec0a 100644 --- a/src/utils.cpp +++ b/src/utils.cpp @@ -1279,21 +1279,35 @@ int load_events(const std::string &fn, std::map &ofm, const auto err_msg = std::string("Detect duplicated v_name:") + v_name + "\n"; throw std::invalid_argument(err_msg); } - ctr.v_id = (uint32_t)v_nameMap.size() - 1; + ctr.v_id = static_cast(v_nameMap.size()) - 1; DBG(2, "h_name:" , ctr.h_event_name , ",hid=" , ctr.h_id , ",v_name:" , ctr.v_event_name , ",v_id: ", ctr.v_id); break; } //TODO: double type for multiplier. drop divider variable case PCM::MULTIPLIER: - ctr.multiplier = (int)numValue; + ctr.multiplier = static_cast(numValue); break; case PCM::DIVIDER: - ctr.divider = (int)numValue; + ctr.divider = static_cast(numValue); break; case PCM::COUNTER_INDEX: - ctr.idx = (int)numValue; + ctr.idx = static_cast(numValue); + break; + case PCM::UNIT_TYPE: + { + auto typeString = dos2unix(value); + if (typeString == std::string("iio")) + { + ctr.type = CounterType::iio; + } + else + { + in.close(); + const auto err_msg = std::string("event line processing(end) fault.\n"); + throw std::invalid_argument(err_msg); + } + } break; - default: if (pfn_evtcb(EVT_LINE_FIELD, evtcb_ctx, ctr, ofm, key, numValue)) { diff --git a/src/utils.h b/src/utils.h index 2bf1d5ea..7b8d112e 100644 --- a/src/utils.h +++ b/src/utils.h @@ -587,6 +587,12 @@ inline void parsePID(int argc, char* argv[], int& pid) parseParam(argc, argv, "pid", [&pid](const char* p) { if (p) pid = atoi(p); }); } +enum class CounterType { + COUNTER_TYPE_INVALID = -1, + iio = 0, + COUNTER_TYPES_COUNT +}; + struct counter { std::string h_event_name = ""; std::string v_event_name = ""; @@ -596,6 +602,7 @@ struct counter { int divider = 0; uint32_t h_id = 0; uint32_t v_id = 0; + CounterType type = CounterType::COUNTER_TYPE_INVALID; }; struct data{ diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp index e1c5d745..61bac53b 100644 --- a/tests/utests/pcm-iio-utest.cpp +++ b/tests/utests/pcm-iio-utest.cpp @@ -39,6 +39,7 @@ struct ExpectedEvent { int divider; std::string hname; std::string vname; + CounterType type; bool operator==(const struct iio_counter& actual) const { @@ -58,7 +59,9 @@ struct ExpectedEvent { bool ch_mask_match = (((actual.ccr >> 36) & 0xFFF) == ch_mask); bool fc_mask_match = (((actual.ccr >> 48) & 0x7) == fc_mask); - return basic_match && ev_sel_match && umask_match && ch_mask_match && fc_mask_match; + bool counter_type_match = (actual.type == type); + + return basic_match && ev_sel_match && umask_match && ch_mask_match && fc_mask_match && counter_type_match; } }; @@ -90,54 +93,54 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) // 1. Define expected events directly (hardcoded values from opCode-6-174.txt) std::vector expectedEvents = { // IB write events - {0, 0x83, 0x1, 1, 0x7, 4, 1, "IB write", "Part0"}, - {1, 0x83, 0x1, 2, 0x7, 4, 1, "IB write", "Part1"}, - {0, 0x83, 0x1, 4, 0x7, 4, 1, "IB write", "Part2"}, - {1, 0x83, 0x1, 8, 0x7, 4, 1, "IB write", "Part3"}, - {0, 0x83, 0x1, 16, 0x7, 4, 1, "IB write", "Part4"}, - {1, 0x83, 0x1, 32, 0x7, 4, 1, "IB write", "Part5"}, - {0, 0x83, 0x1, 64, 0x7, 4, 1, "IB write", "Part6"}, - {1, 0x83, 0x1, 128, 0x7, 4, 1, "IB write", "Part7"}, + {0, 0x83, 0x1, 1, 0x7, 4, 1, "IB write", "Part0", CounterType::iio}, + {1, 0x83, 0x1, 2, 0x7, 4, 1, "IB write", "Part1", CounterType::iio}, + {0, 0x83, 0x1, 4, 0x7, 4, 1, "IB write", "Part2", CounterType::iio}, + {1, 0x83, 0x1, 8, 0x7, 4, 1, "IB write", "Part3", CounterType::iio}, + {0, 0x83, 0x1, 16, 0x7, 4, 1, "IB write", "Part4", CounterType::iio}, + {1, 0x83, 0x1, 32, 0x7, 4, 1, "IB write", "Part5", CounterType::iio}, + {0, 0x83, 0x1, 64, 0x7, 4, 1, "IB write", "Part6", CounterType::iio}, + {1, 0x83, 0x1, 128, 0x7, 4, 1, "IB write", "Part7", CounterType::iio}, // IB read events - {0, 0x83, 0x4, 1, 0x7, 4, 1, "IB read", "Part0"}, - {1, 0x83, 0x4, 2, 0x7, 4, 1, "IB read", "Part1"}, - {0, 0x83, 0x4, 4, 0x7, 4, 1, "IB read", "Part2"}, - {1, 0x83, 0x4, 8, 0x7, 4, 1, "IB read", "Part3"}, - {0, 0x83, 0x4, 16, 0x7, 4, 1, "IB read", "Part4"}, - {1, 0x83, 0x4, 32, 0x7, 4, 1, "IB read", "Part5"}, - {0, 0x83, 0x4, 64, 0x7, 4, 1, "IB read", "Part6"}, - {1, 0x83, 0x4, 128, 0x7, 4, 1, "IB read", "Part7"}, + {0, 0x83, 0x4, 1, 0x7, 4, 1, "IB read", "Part0", CounterType::iio}, + {1, 0x83, 0x4, 2, 0x7, 4, 1, "IB read", "Part1", CounterType::iio}, + {0, 0x83, 0x4, 4, 0x7, 4, 1, "IB read", "Part2", CounterType::iio}, + {1, 0x83, 0x4, 8, 0x7, 4, 1, "IB read", "Part3", CounterType::iio}, + {0, 0x83, 0x4, 16, 0x7, 4, 1, "IB read", "Part4", CounterType::iio}, + {1, 0x83, 0x4, 32, 0x7, 4, 1, "IB read", "Part5", CounterType::iio}, + {0, 0x83, 0x4, 64, 0x7, 4, 1, "IB read", "Part6", CounterType::iio}, + {1, 0x83, 0x4, 128, 0x7, 4, 1, "IB read", "Part7", CounterType::iio}, // OB read events - {2, 0xc0, 0x4, 1, 0x7, 4, 1, "OB read", "Part0"}, - {3, 0xc0, 0x4, 2, 0x7, 4, 1, "OB read", "Part1"}, - {2, 0xc0, 0x4, 4, 0x7, 4, 1, "OB read", "Part2"}, - {3, 0xc0, 0x4, 8, 0x7, 4, 1, "OB read", "Part3"}, - {2, 0xc0, 0x4, 16, 0x7, 4, 1, "OB read", "Part4"}, - {3, 0xc0, 0x4, 32, 0x7, 4, 1, "OB read", "Part5"}, - {2, 0xc0, 0x4, 64, 0x7, 4, 1, "OB read", "Part6"}, - {3, 0xc0, 0x4, 128, 0x7, 4, 1, "OB read", "Part7"}, + {2, 0xc0, 0x4, 1, 0x7, 4, 1, "OB read", "Part0", CounterType::iio}, + {3, 0xc0, 0x4, 2, 0x7, 4, 1, "OB read", "Part1", CounterType::iio}, + {2, 0xc0, 0x4, 4, 0x7, 4, 1, "OB read", "Part2", CounterType::iio}, + {3, 0xc0, 0x4, 8, 0x7, 4, 1, "OB read", "Part3", CounterType::iio}, + {2, 0xc0, 0x4, 16, 0x7, 4, 1, "OB read", "Part4", CounterType::iio}, + {3, 0xc0, 0x4, 32, 0x7, 4, 1, "OB read", "Part5", CounterType::iio}, + {2, 0xc0, 0x4, 64, 0x7, 4, 1, "OB read", "Part6", CounterType::iio}, + {3, 0xc0, 0x4, 128, 0x7, 4, 1, "OB read", "Part7", CounterType::iio}, // OB write events - {2, 0xc0, 0x1, 1, 0x7, 4, 1, "OB write", "Part0"}, - {3, 0xc0, 0x1, 2, 0x7, 4, 1, "OB write", "Part1"}, - {2, 0xc0, 0x1, 4, 0x7, 4, 1, "OB write", "Part2"}, - {3, 0xc0, 0x1, 8, 0x7, 4, 1, "OB write", "Part3"}, - {2, 0xc0, 0x1, 16, 0x7, 4, 1, "OB write", "Part4"}, - {3, 0xc0, 0x1, 32, 0x7, 4, 1, "OB write", "Part5"}, - {2, 0xc0, 0x1, 64, 0x7, 4, 1, "OB write", "Part6"}, - {3, 0xc0, 0x1, 128, 0x7, 4, 1, "OB write", "Part7"}, + {2, 0xc0, 0x1, 1, 0x7, 4, 1, "OB write", "Part0", CounterType::iio}, + {3, 0xc0, 0x1, 2, 0x7, 4, 1, "OB write", "Part1", CounterType::iio}, + {2, 0xc0, 0x1, 4, 0x7, 4, 1, "OB write", "Part2", CounterType::iio}, + {3, 0xc0, 0x1, 8, 0x7, 4, 1, "OB write", "Part3", CounterType::iio}, + {2, 0xc0, 0x1, 16, 0x7, 4, 1, "OB write", "Part4", CounterType::iio}, + {3, 0xc0, 0x1, 32, 0x7, 4, 1, "OB write", "Part5", CounterType::iio}, + {2, 0xc0, 0x1, 64, 0x7, 4, 1, "OB write", "Part6", CounterType::iio}, + {3, 0xc0, 0x1, 128, 0x7, 4, 1, "OB write", "Part7", CounterType::iio}, // IOMMU events - {0, 0x40, 0x01, 0x0, 0x0, 1, 1, "IOTLB Lookup", "Total"}, - {1, 0x40, 0x20, 0x0, 0x0, 1, 1, "IOTLB Miss", "Total"}, - {2, 0x40, 0x80, 0x0, 0x0, 1, 1, "Ctxt Cache Hit", "Total"}, - {3, 0x41, 0x10, 0x0, 0x0, 1, 1, "256T Cache Hit", "Total"}, - {0, 0x41, 0x08, 0x0, 0x0, 1, 1, "512G Cache Hit", "Total"}, - {1, 0x41, 0x04, 0x0, 0x0, 1, 1, "1G Cache Hit", "Total"}, - {2, 0x41, 0x02, 0x0, 0x0, 1, 1, "2M Cache Hit", "Total"}, - {3, 0x41, 0xc0, 0x0, 0x0, 1, 1, "IOMMU Mem Access", "Total"} + {0, 0x40, 0x01, 0x0, 0x0, 1, 1, "IOTLB Lookup", "Total", CounterType::iio}, + {1, 0x40, 0x20, 0x0, 0x0, 1, 1, "IOTLB Miss", "Total", CounterType::iio}, + {2, 0x40, 0x80, 0x0, 0x0, 1, 1, "Ctxt Cache Hit", "Total", CounterType::iio}, + {3, 0x41, 0x10, 0x0, 0x0, 1, 1, "256T Cache Hit", "Total", CounterType::iio}, + {0, 0x41, 0x08, 0x0, 0x0, 1, 1, "512G Cache Hit", "Total", CounterType::iio}, + {1, 0x41, 0x04, 0x0, 0x0, 1, 1, "1G Cache Hit", "Total", CounterType::iio}, + {2, 0x41, 0x02, 0x0, 0x0, 1, 1, "2M Cache Hit", "Total", CounterType::iio}, + {3, 0x41, 0xc0, 0x0, 0x0, 1, 1, "IOMMU Mem Access", "Total", CounterType::iio}, }; // 2. Load events using the existing function @@ -191,11 +194,23 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) << "Divider mismatch for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name; + EXPECT_EQ(expectedEvents[i].type, actualEvt.type) + << "Counter type mismatch for " << actualEvt.h_event_name + << "/" << actualEvt.v_event_name; + break; } } - EXPECT_TRUE(found) << "Could not find expected event for " - << actualEvt.h_event_name << "/" << actualEvt.v_event_name; + EXPECT_TRUE(found) << "Could not find expected event for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name + << "\nActual event details:" + << "\n Counter index: " << actualEvt.idx + << "\n Event select: 0x" << std::hex << (actualEvt.ccr & 0xFF) << std::dec + << "\n UMASK: 0x" << std::hex << ((actualEvt.ccr >> 8) & 0xFF) << std::dec + << "\n CH_MASK: 0x" << std::hex << ((actualEvt.ccr >> 36) & 0xFFF) << std::dec + << "\n FC_MASK: 0x" << std::hex << ((actualEvt.ccr >> 48) & 0x7) << std::dec + << "\n CCR (full): 0x" << std::hex << actualEvt.ccr << std::dec + << "\n Multiplier: " << actualEvt.multiplier + << "\n Type: " << static_cast(actualEvt.type); } // Verify all expected events were found From acc35e61439ce54b5aa771b203378907a21a3370 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 02:00:15 -0700 Subject: [PATCH 20/54] Introduce strategy pattern to handle different counter types --- src/pcm-iio-pmu.cpp | 62 ++++++++++++++++++++++++++++++++++++++++++--- src/pcm-iio-pmu.h | 4 +++ 2 files changed, 62 insertions(+), 4 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 1e7a5b63..c104a513 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1449,7 +1449,57 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, return 0; } -PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) : m_config(config) +class CounterHandlerStrategy { +public: + CounterHandlerStrategy(PCM* pcm) : m_pcm(pcm) {} + virtual ~CounterHandlerStrategy() = default; + + virtual void programCounters(uint64 rawEvents[4]) = 0; + + virtual SimpleCounterState getCounterState(uint32_t socket_id, uint32_t unit_id, uint32_t counter_idx) = 0; + +protected: + PCM* m_pcm; +}; + +class IIOCounterStrategy : public CounterHandlerStrategy { +public: + IIOCounterStrategy(PCM* pcm) : CounterHandlerStrategy(pcm) {} + + void programCounters(uint64 rawEvents[4]) override + { + m_pcm->programIIOCounters(rawEvents); + } + + SimpleCounterState getCounterState(uint32_t socket_id, uint32_t unit_id, uint32_t counter_idx) override + { + return m_pcm->getIIOCounterState(socket_id, unit_id, counter_idx); + } +}; + +std::shared_ptr createCounterStrategy(PCM* pcm, CounterType type) +{ + switch (type) + { + case CounterType::iio: + return std::make_shared(pcm); + default: + std::cerr << "Unsupported counter type: " << static_cast(type) << std::endl; + exit(EXIT_FAILURE); + } +} + +void PcmIioDataCollector::initializeCounterHandlers() +{ + for (const auto& counter : m_config.evt_ctx.ctrs) { + if (!m_strategies[static_cast(counter.type)]) { + m_strategies[static_cast(counter.type)] = createCounterStrategy(m_pcm, counter.type); + } + } +} + +PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) : + m_config(config), m_strategies(static_cast(CounterType::COUNTER_TYPES_COUNT), nullptr) { m_pcm = PCM::getInstance(); m_delay_ms = static_cast(m_config.delay * 1000 / m_config.evt_ctx.ctrs.size()); @@ -1460,6 +1510,8 @@ PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) : m_ m_after = std::make_unique(m_config.iios.size() * m_stacks_count); m_results.resize(m_pcm->getNumSockets(), stack_content(m_stacks_count, ctr_data())); + + initializeCounterHandlers(); } void PcmIioDataCollector::collectData() @@ -1477,12 +1529,14 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) std::unique_ptr pccr(get_ccr(m_pcm, ctr.ccr)); rawEvents[ctr.idx] = pccr->get_ccr_value(); - m_pcm->programIIOCounters(rawEvents); + auto strategy = m_strategies[static_cast(ctr.type)]; + + strategy->programCounters(rawEvents); for (const auto& socket : m_config.iios) { for (const auto& stack : socket.stacks) { auto iio_unit_id = stack.iio_unit_id; uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; - m_before[idx] = m_pcm->getIIOCounterState(socket.socket_id, iio_unit_id, ctr.idx); + m_before[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx); } } MySleepMs(m_delay_ms); @@ -1490,7 +1544,7 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) for (const auto& stack : socket.stacks) { auto iio_unit_id = stack.iio_unit_id; uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; - m_after[idx] = m_pcm->getIIOCounterState(socket.socket_id, iio_unit_id, ctr.idx); + m_after[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx); uint64_t raw_result = getNumberOfEvents(m_before[idx], m_after[idx]); uint64_t trans_result = static_cast(raw_result * ctr.multiplier / (double) ctr.divider * m_time_scaling_factor); m_results[socket.socket_id][iio_unit_id][std::pair(ctr.h_id, ctr.v_id)] = trans_result; diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 301ca8f1..632fee1a 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -676,6 +676,8 @@ class KasseyvillePlatform: public Xeon6thNextGenPlatform { int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map &ofm, std::string key, uint64 numValue); +class CounterHandlerStrategy; + class PcmIioDataCollector { public: PcmIioDataCollector(struct pcm_iio_pmu_config& config); @@ -691,8 +693,10 @@ class PcmIioDataCollector { std::unique_ptr m_before; std::unique_ptr m_after; result_content m_results; + std::vector> m_strategies; result_content getSample(struct iio_counter & ctr); + void initializeCounterHandlers(); static constexpr int COUNTERS_NUMBER = 4; }; From fb0b0c36f87135ab276d5ae9c3a366c812b7f756 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 02:23:54 -0700 Subject: [PATCH 21/54] Drop divider from pcm-iio opCode files as far it's always 1 --- src/opCode-6-106.txt | 82 +++++++++++++++---------------- src/opCode-6-108.txt | 82 +++++++++++++++---------------- src/opCode-6-134.txt | 82 +++++++++++++++---------------- src/opCode-6-143.txt | 82 +++++++++++++++---------------- src/opCode-6-173.txt | 82 +++++++++++++++---------------- src/opCode-6-174.txt | 82 +++++++++++++++---------------- src/opCode-6-175.txt | 82 +++++++++++++++---------------- src/opCode-6-182.txt | 82 +++++++++++++++---------------- src/opCode-6-207.txt | 82 +++++++++++++++---------------- src/opCode-6-85.txt | 46 +++++++++--------- src/pcm-iio-pmu.cpp | 6 +-- tests/utests/pcm-iio-utest.cpp | 88 ++++++++++++++++------------------ 12 files changed, 435 insertions(+), 443 deletions(-) diff --git a/src/opCode-6-106.txt b/src/opCode-6-106.txt index 78016232..2bd1077e 100644 --- a/src/opCode-6-106.txt +++ b/src/opCode-6-106.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-108.txt b/src/opCode-6-108.txt index 78016232..2bd1077e 100644 --- a/src/opCode-6-108.txt +++ b/src/opCode-6-108.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-134.txt b/src/opCode-6-134.txt index 7ae1885e..4c8e744f 100644 --- a/src/opCode-6-134.txt +++ b/src/opCode-6-134.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=4K Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total \ No newline at end of file +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total \ No newline at end of file diff --git a/src/opCode-6-143.txt b/src/opCode-6-143.txt index 426c4fa9..7a4dfc3d 100644 --- a/src/opCode-6-143.txt +++ b/src/opCode-6-143.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-173.txt b/src/opCode-6-173.txt index 9e4636f1..821de1c2 100644 --- a/src/opCode-6-173.txt +++ b/src/opCode-6-173.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-174.txt b/src/opCode-6-174.txt index 9e4636f1..821de1c2 100644 --- a/src/opCode-6-174.txt +++ b/src/opCode-6-174.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-175.txt b/src/opCode-6-175.txt index 9e4636f1..821de1c2 100644 --- a/src/opCode-6-175.txt +++ b/src/opCode-6-175.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-182.txt b/src/opCode-6-182.txt index 9e4636f1..821de1c2 100644 --- a/src/opCode-6-182.txt +++ b/src/opCode-6-182.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-207.txt b/src/opCode-6-207.txt index 426c4fa9..7a4dfc3d 100644 --- a/src/opCode-6-207.txt +++ b/src/opCode-6-207.txt @@ -1,45 +1,45 @@ #Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,divider=1,hname=Clockticks,vname=Total +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=IB read,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,divider=1,hname=OB write,vname=Part7 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 # IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,divider=1,hname=IOMMU Mem Access,vname=Total +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/src/opCode-6-85.txt b/src/opCode-6-85.txt index 7289b384..73d93176 100644 --- a/src/opCode-6-85.txt +++ b/src/opCode-6-85.txt @@ -1,26 +1,26 @@ # Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB write (bytes),vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=IB read (bytes),vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part3 (4th x4) # Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB read (bytes),vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,divider=1,hname=OB write (bytes),vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part3 (4th x4) # VTd events -ctr=0,unit=iio,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d CTXT Miss,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L1 Miss,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L2 Miss,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d L3 Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,divider=1,hname=VT-d Mem Read,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d CTXT Miss,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d L1 Miss,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d L2 Miss,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=VT-d L3 Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,hname=VT-d Mem Read,vname=Total diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index c104a513..a038ccec 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1436,13 +1436,12 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, context->ctr.v_event_name = base_ctr.v_event_name; context->ctr.idx = base_ctr.idx; context->ctr.multiplier = base_ctr.multiplier; - context->ctr.divider = base_ctr.divider; context->ctr.h_id = base_ctr.h_id; context->ctr.v_id = base_ctr.v_id; context->ctr.type = base_ctr.type; DBG(4, "line parse OK, ctrcfg=0x", std::hex, context->ctr.ccr, ", h_event_name=", base_ctr.h_event_name, ", v_event_name=", base_ctr.v_event_name); DBG(4, ", h_id=0x", std::hex, base_ctr.h_id, ", v_id=0x", std::hex, base_ctr.v_id); - DBG(4, ", idx=0x", std::hex, base_ctr.idx, ", multiplier=0x", std::hex, base_ctr.multiplier, ", divider=0x", std::hex, base_ctr.divider, std::dec, ", counter type = ", static_cast(base_ctr.type), "\n"); + DBG(4, ", idx=0x", std::hex, base_ctr.idx, ", multiplier=0x", std::hex, base_ctr.multiplier, std::dec, ", counter type = ", static_cast(base_ctr.type), "\n"); context->ctrs.push_back(context->ctr); } @@ -1546,7 +1545,7 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; m_after[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx); uint64_t raw_result = getNumberOfEvents(m_before[idx], m_after[idx]); - uint64_t trans_result = static_cast(raw_result * ctr.multiplier / (double) ctr.divider * m_time_scaling_factor); + uint64_t trans_result = static_cast(raw_result * ctr.multiplier * m_time_scaling_factor); m_results[socket.socket_id][iio_unit_id][std::pair(ctr.h_id, ctr.v_id)] = trans_result; } } @@ -1584,7 +1583,6 @@ void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap) opcodeFieldMap["hname"] = PCM::H_EVENT_NAME; opcodeFieldMap["vname"] = PCM::V_EVENT_NAME; opcodeFieldMap["multiplier"] = PCM::MULTIPLIER; - opcodeFieldMap["divider"] = PCM::DIVIDER; opcodeFieldMap["ctr"] = PCM::COUNTER_INDEX; opcodeFieldMap["unit"] = PCM::UNIT_TYPE; } diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp index 61bac53b..2072156c 100644 --- a/tests/utests/pcm-iio-utest.cpp +++ b/tests/utests/pcm-iio-utest.cpp @@ -36,7 +36,6 @@ struct ExpectedEvent { uint32_t ch_mask; uint32_t fc_mask; int multiplier; - int divider; std::string hname; std::string vname; CounterType type; @@ -48,8 +47,7 @@ struct ExpectedEvent { ctr == actual.idx && hname == actual.h_event_name && vname == actual.v_event_name && - multiplier == actual.multiplier && - divider == actual.divider; + multiplier == actual.multiplier; // Check if ev_sel and umask were properly encoded in CCR bool ev_sel_match = (actual.ccr & 0xFF) == ev_sel; @@ -93,54 +91,54 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) // 1. Define expected events directly (hardcoded values from opCode-6-174.txt) std::vector expectedEvents = { // IB write events - {0, 0x83, 0x1, 1, 0x7, 4, 1, "IB write", "Part0", CounterType::iio}, - {1, 0x83, 0x1, 2, 0x7, 4, 1, "IB write", "Part1", CounterType::iio}, - {0, 0x83, 0x1, 4, 0x7, 4, 1, "IB write", "Part2", CounterType::iio}, - {1, 0x83, 0x1, 8, 0x7, 4, 1, "IB write", "Part3", CounterType::iio}, - {0, 0x83, 0x1, 16, 0x7, 4, 1, "IB write", "Part4", CounterType::iio}, - {1, 0x83, 0x1, 32, 0x7, 4, 1, "IB write", "Part5", CounterType::iio}, - {0, 0x83, 0x1, 64, 0x7, 4, 1, "IB write", "Part6", CounterType::iio}, - {1, 0x83, 0x1, 128, 0x7, 4, 1, "IB write", "Part7", CounterType::iio}, + {0, 0x83, 0x1, 1, 0x7, 4, "IB write", "Part0", CounterType::iio}, + {1, 0x83, 0x1, 2, 0x7, 4, "IB write", "Part1", CounterType::iio}, + {0, 0x83, 0x1, 4, 0x7, 4, "IB write", "Part2", CounterType::iio}, + {1, 0x83, 0x1, 8, 0x7, 4, "IB write", "Part3", CounterType::iio}, + {0, 0x83, 0x1, 16, 0x7, 4, "IB write", "Part4", CounterType::iio}, + {1, 0x83, 0x1, 32, 0x7, 4, "IB write", "Part5", CounterType::iio}, + {0, 0x83, 0x1, 64, 0x7, 4, "IB write", "Part6", CounterType::iio}, + {1, 0x83, 0x1, 128, 0x7, 4, "IB write", "Part7", CounterType::iio}, // IB read events - {0, 0x83, 0x4, 1, 0x7, 4, 1, "IB read", "Part0", CounterType::iio}, - {1, 0x83, 0x4, 2, 0x7, 4, 1, "IB read", "Part1", CounterType::iio}, - {0, 0x83, 0x4, 4, 0x7, 4, 1, "IB read", "Part2", CounterType::iio}, - {1, 0x83, 0x4, 8, 0x7, 4, 1, "IB read", "Part3", CounterType::iio}, - {0, 0x83, 0x4, 16, 0x7, 4, 1, "IB read", "Part4", CounterType::iio}, - {1, 0x83, 0x4, 32, 0x7, 4, 1, "IB read", "Part5", CounterType::iio}, - {0, 0x83, 0x4, 64, 0x7, 4, 1, "IB read", "Part6", CounterType::iio}, - {1, 0x83, 0x4, 128, 0x7, 4, 1, "IB read", "Part7", CounterType::iio}, + {0, 0x83, 0x4, 1, 0x7, 4, "IB read", "Part0", CounterType::iio}, + {1, 0x83, 0x4, 2, 0x7, 4, "IB read", "Part1", CounterType::iio}, + {0, 0x83, 0x4, 4, 0x7, 4, "IB read", "Part2", CounterType::iio}, + {1, 0x83, 0x4, 8, 0x7, 4, "IB read", "Part3", CounterType::iio}, + {0, 0x83, 0x4, 16, 0x7, 4, "IB read", "Part4", CounterType::iio}, + {1, 0x83, 0x4, 32, 0x7, 4, "IB read", "Part5", CounterType::iio}, + {0, 0x83, 0x4, 64, 0x7, 4, "IB read", "Part6", CounterType::iio}, + {1, 0x83, 0x4, 128, 0x7, 4, "IB read", "Part7", CounterType::iio}, // OB read events - {2, 0xc0, 0x4, 1, 0x7, 4, 1, "OB read", "Part0", CounterType::iio}, - {3, 0xc0, 0x4, 2, 0x7, 4, 1, "OB read", "Part1", CounterType::iio}, - {2, 0xc0, 0x4, 4, 0x7, 4, 1, "OB read", "Part2", CounterType::iio}, - {3, 0xc0, 0x4, 8, 0x7, 4, 1, "OB read", "Part3", CounterType::iio}, - {2, 0xc0, 0x4, 16, 0x7, 4, 1, "OB read", "Part4", CounterType::iio}, - {3, 0xc0, 0x4, 32, 0x7, 4, 1, "OB read", "Part5", CounterType::iio}, - {2, 0xc0, 0x4, 64, 0x7, 4, 1, "OB read", "Part6", CounterType::iio}, - {3, 0xc0, 0x4, 128, 0x7, 4, 1, "OB read", "Part7", CounterType::iio}, + {2, 0xc0, 0x4, 1, 0x7, 4, "OB read", "Part0", CounterType::iio}, + {3, 0xc0, 0x4, 2, 0x7, 4, "OB read", "Part1", CounterType::iio}, + {2, 0xc0, 0x4, 4, 0x7, 4, "OB read", "Part2", CounterType::iio}, + {3, 0xc0, 0x4, 8, 0x7, 4, "OB read", "Part3", CounterType::iio}, + {2, 0xc0, 0x4, 16, 0x7, 4, "OB read", "Part4", CounterType::iio}, + {3, 0xc0, 0x4, 32, 0x7, 4, "OB read", "Part5", CounterType::iio}, + {2, 0xc0, 0x4, 64, 0x7, 4, "OB read", "Part6", CounterType::iio}, + {3, 0xc0, 0x4, 128, 0x7, 4, "OB read", "Part7", CounterType::iio}, // OB write events - {2, 0xc0, 0x1, 1, 0x7, 4, 1, "OB write", "Part0", CounterType::iio}, - {3, 0xc0, 0x1, 2, 0x7, 4, 1, "OB write", "Part1", CounterType::iio}, - {2, 0xc0, 0x1, 4, 0x7, 4, 1, "OB write", "Part2", CounterType::iio}, - {3, 0xc0, 0x1, 8, 0x7, 4, 1, "OB write", "Part3", CounterType::iio}, - {2, 0xc0, 0x1, 16, 0x7, 4, 1, "OB write", "Part4", CounterType::iio}, - {3, 0xc0, 0x1, 32, 0x7, 4, 1, "OB write", "Part5", CounterType::iio}, - {2, 0xc0, 0x1, 64, 0x7, 4, 1, "OB write", "Part6", CounterType::iio}, - {3, 0xc0, 0x1, 128, 0x7, 4, 1, "OB write", "Part7", CounterType::iio}, + {2, 0xc0, 0x1, 1, 0x7, 4, "OB write", "Part0", CounterType::iio}, + {3, 0xc0, 0x1, 2, 0x7, 4, "OB write", "Part1", CounterType::iio}, + {2, 0xc0, 0x1, 4, 0x7, 4, "OB write", "Part2", CounterType::iio}, + {3, 0xc0, 0x1, 8, 0x7, 4, "OB write", "Part3", CounterType::iio}, + {2, 0xc0, 0x1, 16, 0x7, 4, "OB write", "Part4", CounterType::iio}, + {3, 0xc0, 0x1, 32, 0x7, 4, "OB write", "Part5", CounterType::iio}, + {2, 0xc0, 0x1, 64, 0x7, 4, "OB write", "Part6", CounterType::iio}, + {3, 0xc0, 0x1, 128, 0x7, 4, "OB write", "Part7", CounterType::iio}, // IOMMU events - {0, 0x40, 0x01, 0x0, 0x0, 1, 1, "IOTLB Lookup", "Total", CounterType::iio}, - {1, 0x40, 0x20, 0x0, 0x0, 1, 1, "IOTLB Miss", "Total", CounterType::iio}, - {2, 0x40, 0x80, 0x0, 0x0, 1, 1, "Ctxt Cache Hit", "Total", CounterType::iio}, - {3, 0x41, 0x10, 0x0, 0x0, 1, 1, "256T Cache Hit", "Total", CounterType::iio}, - {0, 0x41, 0x08, 0x0, 0x0, 1, 1, "512G Cache Hit", "Total", CounterType::iio}, - {1, 0x41, 0x04, 0x0, 0x0, 1, 1, "1G Cache Hit", "Total", CounterType::iio}, - {2, 0x41, 0x02, 0x0, 0x0, 1, 1, "2M Cache Hit", "Total", CounterType::iio}, - {3, 0x41, 0xc0, 0x0, 0x0, 1, 1, "IOMMU Mem Access", "Total", CounterType::iio}, + {0, 0x40, 0x01, 0x0, 0x0, 1, "IOTLB Lookup", "Total", CounterType::iio}, + {1, 0x40, 0x20, 0x0, 0x0, 1, "IOTLB Miss", "Total", CounterType::iio}, + {2, 0x40, 0x80, 0x0, 0x0, 1, "Ctxt Cache Hit", "Total", CounterType::iio}, + {3, 0x41, 0x10, 0x0, 0x0, 1, "256T Cache Hit", "Total", CounterType::iio}, + {0, 0x41, 0x08, 0x0, 0x0, 1, "512G Cache Hit", "Total", CounterType::iio}, + {1, 0x41, 0x04, 0x0, 0x0, 1, "1G Cache Hit", "Total", CounterType::iio}, + {2, 0x41, 0x02, 0x0, 0x0, 1, "2M Cache Hit", "Total", CounterType::iio}, + {3, 0x41, 0xc0, 0x0, 0x0, 1, "IOMMU Mem Access", "Total", CounterType::iio}, }; // 2. Load events using the existing function @@ -190,10 +188,6 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) << "Multiplier mismatch for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name; - EXPECT_EQ(expectedEvents[i].divider, actualEvt.divider) - << "Divider mismatch for " << actualEvt.h_event_name - << "/" << actualEvt.v_event_name; - EXPECT_EQ(expectedEvents[i].type, actualEvt.type) << "Counter type mismatch for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name; From 2f742d822f695902f0a313fa7e494cee9c57ca31 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 02:29:55 -0700 Subject: [PATCH 22/54] Introduce getMaxNumOfIOStacks() --- src/cpucounters.cpp | 5 +++++ src/cpucounters.h | 3 +++ src/pcm-iio-pmu.cpp | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 14d903f0..b662fa3c 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -10348,6 +10348,11 @@ uint32 PCM::getMaxNumOfIIOStacks() const return 0; } +uint32 PCM::getMaxNumOfIOStacks() const +{ + return getMaxNumOfIIOStacks(); +} + void PCM::programCboOpcodeFilter(const uint32 opc0, UncorePMU & pmu, const uint32 nc_, const uint32 opc1, const uint32 loc, const uint32 rem) { if (JAKETOWN == cpu_family_model) diff --git a/src/cpucounters.h b/src/cpucounters.h index 6ecefe50..2f7d649a 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1398,6 +1398,9 @@ class PCM_API PCM //! \brief Returns the number of IIO stacks per socket uint32 getMaxNumOfIIOStacks() const; + //! \brief Returns the number of IO stacks per socket + uint32 getMaxNumOfIOStacks() const; + /*! \brief Returns the number of IDX accel devs \param accel index of IDX accel */ diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index a038ccec..0e2c68c1 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1502,7 +1502,7 @@ PcmIioDataCollector::PcmIioDataCollector(struct pcm_iio_pmu_config& config) : { m_pcm = PCM::getInstance(); m_delay_ms = static_cast(m_config.delay * 1000 / m_config.evt_ctx.ctrs.size()); - m_stacks_count = m_pcm->getMaxNumOfIIOStacks(); + m_stacks_count = m_pcm->getMaxNumOfIOStacks(); m_time_scaling_factor = 1000.0 / m_delay_ms; m_before = std::make_unique(m_config.iios.size() * m_stacks_count); From 11606f8106db63c9b60cb6c7d20c15523d106fa7 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 03:33:41 -0700 Subject: [PATCH 23/54] Move pcm-iio-topology to separate file --- src/CMakeLists.txt | 2 +- src/pcm-iio-pmu.cpp | 1101 +--------------------------------- src/pcm-iio-pmu.h | 597 +------------------ src/pcm-iio-topology.cpp | 1106 +++++++++++++++++++++++++++++++++++ src/pcm-iio-topology.h | 623 ++++++++++++++++++++ src/pcm-iio.cpp | 5 +- tests/utests/CMakeLists.txt | 2 +- 7 files changed, 1741 insertions(+), 1695 deletions(-) create mode 100644 src/pcm-iio-topology.cpp create mode 100644 src/pcm-iio-topology.h diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 1c87ba30..aec24e1a 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -8,7 +8,7 @@ set(PROJECT_NAMES pcm pcm-numa pcm-latency pcm-power pcm-msr pcm-memory pcm-tsx set(MINIMUM_OPENSSL_VERSION 1.1.1) -file(GLOB COMMON_SOURCES pcm-accel-common.cpp msr.cpp cpucounters.cpp pci.cpp mmio.cpp tpmi.cpp pmt.cpp bw.cpp utils.cpp topology.cpp debug.cpp threadpool.cpp uncore_pmu_discovery.cpp pcm-iio-pmu.cpp lspci.cpp ${PCM_PUGIXML_CPP}) +file(GLOB COMMON_SOURCES pcm-accel-common.cpp msr.cpp cpucounters.cpp pci.cpp mmio.cpp tpmi.cpp pmt.cpp bw.cpp utils.cpp topology.cpp debug.cpp threadpool.cpp uncore_pmu_discovery.cpp pcm-iio-pmu.cpp pcm-iio-topology.cpp lspci.cpp ${PCM_PUGIXML_CPP}) if (APPLE) file(GLOB UNIX_SOURCES dashboard.cpp) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 0e2c68c1..ddfcf745 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -1,11 +1,13 @@ // SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2017-2022, Intel Corporation +// Copyright (c) 2017-2025, Intel Corporation // written by Patrick Lu, // Aaron Cruz +// Alexander Antonov // and others #include "pcm-iio-pmu.h" +#include "pcm-iio-topology.h" vector combine_stack_name_and_counter_names(string stack_name, const PCIeEventNameMap& nameMap) { @@ -272,1089 +274,6 @@ std::unique_ptr getDisplayBuilder(struct pcm_iio_config& co return displayBuilder; } -void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) -{ - for (uint16_t bus = 0; bus < 256; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci pci_dev; - pci_dev.bdf.busno = (uint8_t)bus; - pci_dev.bdf.devno = device; - pci_dev.bdf.funcno = function; - if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SKX_SOCKETID_UBOX_DID)) { - ubox.push_back(bus); - } - } - } - } -} - -bool PurleyPlatformMapping::pciTreeDiscover(std::vector& iios) -{ - std::vector ubox; - getUboxBusNumbers(ubox); - if (ubox.empty()) { - cerr << "UBOXs were not found! Program aborted" << endl; - return false; - } - - for (uint32_t socket_id = 0; socket_id < socketsCount(); socket_id++) { - if (!PciHandleType::exists(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM)) { - cerr << "No access to PCICFG\n" << endl; - return false; - } - uint64 cpubusno = 0; - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = socket_id; - PciHandleType h(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM); - h.read64(ROOT_BUSES_OFFSET, &cpubusno); - - iio_on_socket.stacks.reserve(6); - for (int stack_id = 0; stack_id < 6; stack_id++) { - struct iio_stack stack; - stack.iio_unit_id = stack_id; - stack.busno = (uint8_t)(cpubusno >> (stack_id * SKX_BUS_NUM_STRIDE)); - stack.stack_name = skx_iio_stack_names[stack_id]; - for (uint8_t part_id = 0; part_id < 4; part_id++) { - struct iio_bifurcated_part part; - part.part_id = part_id; - struct pci *pci = &part.root_pci_dev; - struct bdf *bdf = &pci->bdf; - bdf->busno = stack.busno; - bdf->devno = part_id; - bdf->funcno = 0; - /* This is a workaround to catch some IIO stack does not exist */ - if (stack_id != 0 && stack.busno == 0) { - pci->exist = false; - } - else if (probe_pci(pci)) { - /* FIXME: for 0:0.0, we may need to scan from secondary switch down; lgtm [cpp/fixme-comment] */ - for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev; - child_pci_dev.bdf.busno = bus; - child_pci_dev.bdf.devno = device; - child_pci_dev.bdf.funcno = function; - if (probe_pci(&child_pci_dev)) { - part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - } - stack.parts.push_back(part); - } - - iio_on_socket.stacks.push_back(stack); - } - iios.push_back(iio_on_socket); - } - - return true; -} - -bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map& sad_id_bus_map) -{ - for (uint16_t bus = 0; bus < 256; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci pci_dev; - pci_dev.bdf.busno = (uint8_t)bus; - pci_dev.bdf.devno = device; - pci_dev.bdf.funcno = function; - if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SNR_ICX_MESH2IIO_MMAP_DID)) { - - PciHandleType h(0, bus, device, function); - std::uint32_t sad_ctrl_cfg; - h.read32(SNR_ICX_SAD_CONTROL_CFG_OFFSET, &sad_ctrl_cfg); - if (sad_ctrl_cfg == (std::numeric_limits::max)()) { - cerr << "Could not read SAD_CONTROL_CFG" << endl; - return false; - } - - if ((sad_ctrl_cfg & 0xf) == socket_id) { - uint8_t sid = (sad_ctrl_cfg >> 4) & 0x7; - sad_id_bus_map.insert(std::pair(sid, (uint8_t)bus)); - } - } - } - } - } - - if (sad_id_bus_map.empty()) { - cerr << "Could not find Root Port bus numbers" << endl; - return false; - } - - return true; -} - -bool WhitleyPlatformMapping::pciTreeDiscover(std::vector& iios) -{ - for (uint32_t socket = 0; socket < socketsCount(); socket++) { - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = socket; - std::map sad_id_bus_map; - if (!getSadIdRootBusMap(socket, sad_id_bus_map)) { - return false; - } - - { - struct iio_stack stack; - stack.iio_unit_id = sad_to_pmu_id_mapping.at(ICX_MCP_SAD_ID); - stack.stack_name = iio_stack_names[stack.iio_unit_id]; - iio_on_socket.stacks.push_back(stack); - } - - for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { - int sad_id = sad_id_bus_pair->first; - if (sad_to_pmu_id_mapping.find(sad_id) == - sad_to_pmu_id_mapping.end()) { - cerr << "Unknown SAD ID: " << sad_id << endl; - return false; - } - - if (sad_id == ICX_MCP_SAD_ID) { - continue; - } - - struct iio_stack stack; - int root_bus = sad_id_bus_pair->second; - if (sad_id == ICX_CBDMA_DMI_SAD_ID) { - // There is one DMA Controller on each socket - stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id); - stack.busno = root_bus; - stack.stack_name = iio_stack_names[stack.iio_unit_id]; - - // PCH is on socket 0 only - if (socket == 0) { - struct iio_bifurcated_part pch_part; - struct pci *pci = &pch_part.root_pci_dev; - struct bdf *bdf = &pci->bdf; - pch_part.part_id = ICX_PCH_PART_ID; - bdf->busno = root_bus; - bdf->devno = 0x00; - bdf->funcno = 0x00; - if (probe_pci(pci)) { - // Probe child devices only under PCH part. - for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev; - child_pci_dev.bdf.busno = bus; - child_pci_dev.bdf.devno = device; - child_pci_dev.bdf.funcno = function; - if (probe_pci(&child_pci_dev)) { - pch_part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(pch_part); - } - } - - struct iio_bifurcated_part part; - part.part_id = ICX_CBDMA_PART_ID; - struct pci *pci = &part.root_pci_dev; - struct bdf *bdf = &pci->bdf; - bdf->busno = root_bus; - bdf->devno = 0x01; - bdf->funcno = 0x00; - if (probe_pci(pci)) - stack.parts.push_back(part); - - iio_on_socket.stacks.push_back(stack); - continue; - } - stack.busno = root_bus; - stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id); - stack.stack_name = iio_stack_names[stack.iio_unit_id]; - for (int slot = 2; slot < 6; slot++) { - struct pci pci; - pci.bdf.busno = root_bus; - pci.bdf.devno = slot; - pci.bdf.funcno = 0x00; - if (!probe_pci(&pci)) { - continue; - } - struct iio_bifurcated_part part; - part.part_id = slot - 2; - part.root_pci_dev = pci; - - for (uint8_t bus = pci.secondary_bus_number; bus <= pci.subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev; - child_pci_dev.bdf.busno = bus; - child_pci_dev.bdf.devno = device; - child_pci_dev.bdf.funcno = function; - if (probe_pci(&child_pci_dev)) { - part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(part); - } - iio_on_socket.stacks.push_back(stack); - } - std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); - iios.push_back(iio_on_socket); - } - return true; -} - -bool JacobsvillePlatformMapping::JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack) -{ - uint16_t expected_dev_id; - auto sad_id = sad_id_bus_pair.first; - switch (sad_id) { - case SNR_HQM_SAD_ID: - expected_dev_id = HQM_DID; - break; - case SNR_NIS_SAD_ID: - expected_dev_id = NIS_DID; - break; - case SNR_QAT_SAD_ID: - expected_dev_id = QAT_DID; - break; - default: - return false; - } - stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id); - stack.stack_name = snr_iio_stack_names[stack.iio_unit_id]; - for (uint16_t bus = sad_id_bus_pair.second; bus < 256; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci pci_dev; - pci_dev.bdf.busno = (uint8_t)bus; - pci_dev.bdf.devno = device; - pci_dev.bdf.funcno = function; - if (probe_pci(&pci_dev)) { - if (expected_dev_id == pci_dev.device_id) { - struct iio_bifurcated_part part; - part.part_id = SNR_ACCELERATOR_PART_ID; - part.root_pci_dev = pci_dev; - stack.busno = (uint8_t)bus; - stack.parts.push_back(part); - return true; - } - } - } - } - } - return false; -} - -bool JacobsvillePlatformMapping::pciTreeDiscover(std::vector& iios) -{ - std::map sad_id_bus_map; - if (!getSadIdRootBusMap(0, sad_id_bus_map)) { - return false; - } - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = 0; - if (sad_id_bus_map.size() != snr_sad_to_pmu_id_mapping.size()) { - cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << snr_sad_to_pmu_id_mapping.size() << endl; - return false; - } - - for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { - int sad_id = sad_id_bus_pair->first; - struct iio_stack stack; - switch (sad_id) { - case SNR_CBDMA_DMI_SAD_ID: - { - int root_bus = sad_id_bus_pair->second; - stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id); - stack.stack_name = snr_iio_stack_names[stack.iio_unit_id]; - stack.busno = root_bus; - // DMA Controller - struct iio_bifurcated_part part; - part.part_id = 0; - struct pci pci_dev; - pci_dev.bdf.busno = root_bus; - pci_dev.bdf.devno = 0x01; - pci_dev.bdf.funcno = 0x00; - if (probe_pci(&pci_dev)) { - part.root_pci_dev = pci_dev; - stack.parts.push_back(part); - } - - part.part_id = 4; - pci_dev.bdf.busno = root_bus; - pci_dev.bdf.devno = 0x00; - pci_dev.bdf.funcno = 0x00; - if (probe_pci(&pci_dev)) { - for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev; - child_pci_dev.bdf.busno = bus; - child_pci_dev.bdf.devno = device; - child_pci_dev.bdf.funcno = function; - if (probe_pci(&child_pci_dev)) { - part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - part.root_pci_dev = pci_dev; - stack.parts.push_back(part); - } - } - break; - case SNR_PCIE_GEN3_SAD_ID: - { - int root_bus = sad_id_bus_pair->second; - stack.busno = root_bus; - stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id); - stack.stack_name = snr_iio_stack_names[stack.iio_unit_id]; - for (int slot = 4; slot < 8; slot++) { - struct pci pci_dev; - pci_dev.bdf.busno = root_bus; - pci_dev.bdf.devno = slot; - pci_dev.bdf.funcno = 0x00; - if (!probe_pci(&pci_dev)) { - continue; - } - int part_id = 4 + pci_dev.device_id - SNR_ROOT_PORT_A_DID; - if ((part_id < 0) || (part_id > 4)) { - cerr << "Invalid part ID " << part_id << endl; - return false; - } - struct iio_bifurcated_part part; - part.part_id = part_id; - part.root_pci_dev = pci_dev; - for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev; - child_pci_dev.bdf.busno = bus; - child_pci_dev.bdf.devno = device; - child_pci_dev.bdf.funcno = function; - if (probe_pci(&child_pci_dev)) { - part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(part); - } - } - break; - case SNR_HQM_SAD_ID: - case SNR_NIS_SAD_ID: - case SNR_QAT_SAD_ID: - JacobsvilleAccelerators(*sad_id_bus_pair, stack); - break; - default: - cerr << "Unknown SAD ID: " << sad_id << endl; - return false; - } - iio_on_socket.stacks.push_back(stack); - } - - std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); - - iios.push_back(iio_on_socket); - - return true; -} - -bool EagleStreamPlatformMapping::setChopValue() -{ - for (uint16_t b = 0; b < 256; b++) { - struct pci pci_dev(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION); - if (!(probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SPR_PCU_CR3_DID))) { - continue; - } - - std::uint32_t capid4; - PciHandleType h(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION); - h.read32(SPR_CAPID4_OFFSET, &capid4); - if (capid4 == (std::numeric_limits::max)()) { - std::cerr << "Cannot read PCU RC3 register" << std::endl; - return false; - } - capid4 = SPR_CAPID4_GET_PHYSICAL_CHOP(capid4); - if (capid4 == kXccChop || capid4 == kMccChop) { - m_chop = capid4; - m_es_type = cpuId() == PCM::SPR ? (m_chop == kXccChop ? estype::esSprXcc : estype::esSprMcc) : estype::esEmrXcc; - } - else { - std::cerr << "Unknown chop value " << capid4 << std::endl; - return false; - } - return true; - } - std::cerr << "Cannot find PCU RC3 registers on the system. Device ID is " << std::hex << SPR_PCU_CR3_DID << std::dec << std::endl; - return false; -} - -bool EagleStreamPlatformMapping::getRootBuses(std::map> &root_buses) -{ - bool mapped = true; - for (uint32_t domain = 0; mapped; domain++) { - mapped = false; - for (uint16_t b = 0; b < 256; b++) { - for (uint8_t d = 0; d < 32; d++) { - for (uint8_t f = 0; f < 8; f++) { - struct pci pci_dev(domain, b, d, f); - if (!probe_pci(&pci_dev)) { - break; - } - if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) { - continue; - } - - std::uint32_t cpuBusValid; - std::vector cpuBusNo; - int package_id; - - if (get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id) == false) - { - return false; - } - - const auto& sad_to_pmu_id_mapping = es_sad_to_pmu_id_mapping.at(m_es_type); - for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) { - if (!((cpuBusValid >> cpuBusId) & 0x1)) - { - cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl; - continue; - } - if (sad_to_pmu_id_mapping.find(cpuBusId) == sad_to_pmu_id_mapping.end()) - { - cerr << "Cannot map CPU bus " << cpuBusId << " to IO PMU ID" << endl; - continue; - } - int pmuId = sad_to_pmu_id_mapping.at(cpuBusId); - int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff; - root_buses[package_id][pmuId] = bdf(domain, rootBus, 0, 0); - cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ") to IO PMU #" - << pmuId << " package " << package_id << endl; - mapped = true; - } - } - } - } - } - return !root_buses.empty(); -} - -bool EagleStreamPlatformMapping::eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - struct iio_stack stack; - stack.iio_unit_id = unit; - stack.stack_name = es_stack_names.at(m_es_type)[unit]; - stack.busno = address.busno; - stack.domain = address.domainno; - struct iio_bifurcated_part pch_part; - struct pci *pci = &pch_part.root_pci_dev; - auto dmi_part_id = SPR_DMI_PART_ID; - pch_part.part_id = dmi_part_id; - pci->bdf = address; - if (!probe_pci(pci)) { - cerr << "Failed to probe DMI Stack: address: " << std::setw(4) << std::setfill('0') << std::hex << address.domainno << - std::setw(2) << std::setfill('0') << ":" << address.busno << ":" << address.devno << - "." << address.funcno << std::dec << endl; - return false; - } - - /* Scan devices behind PCH port only */ - if (!iio_on_socket.socket_id) - probeDeviceRange(pch_part.child_pci_devs, pci->bdf.domainno, pci->secondary_bus_number, pci->subordinate_bus_number); - - pci->parts_no.push_back(dmi_part_id); - - stack.parts.push_back(pch_part); - iio_on_socket.stacks.push_back(stack); - return true; -} - -bool EagleStreamPlatformMapping::eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - /* - * Stacks that manage PCIe 4.0 (device 2,4,6,8) and 5.0 (device 1,3,5,7) Root Ports. - */ - struct iio_stack stack; - stack.domain = address.domainno; - stack.busno = address.busno; - stack.iio_unit_id = unit; - stack.stack_name = es_stack_names.at(m_es_type)[unit]; - for (int slot = 1; slot < 9; ++slot) - { - // Check if port is enabled - struct pci root_pci_dev; - root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0); - if (probe_pci(&root_pci_dev)) - { - struct iio_bifurcated_part part; - // Bifurcated Root Ports to channel mapping on SPR - part.part_id = slot - 1; - part.root_pci_dev = root_pci_dev; - for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) { - for (uint8_t d = 0; d < 32; ++d) { - for (uint8_t f = 0; f < 8; ++f) { - struct pci child_pci_dev(address.domainno, b, d, f); - if (probe_pci(&child_pci_dev)) { - child_pci_dev.parts_no.push_back(part.part_id); - part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(part); - } - } - iio_on_socket.stacks.push_back(stack); - return true; -} - -bool EagleStreamPlatformMapping::eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - struct iio_stack stack; - stack.iio_unit_id = unit; - stack.domain = address.domainno; - stack.busno = address.busno; - - // Channel mappings are checked on B0 stepping - auto rb = address.busno; - const std::vector acceleratorBuses{ rb, rb + 1, rb + 2, rb + 3 }; - stack.stack_name = es_stack_names.at(m_es_type)[unit]; - for (auto& b : acceleratorBuses) { - for (auto d = 0; d < 32; ++d) { - for (auto f = 0; f < 8; ++f) { - struct iio_bifurcated_part part; - struct pci pci_dev(address.domainno, b, d, f); - - if (probe_pci(&pci_dev)) { - if (pci_dev.isIntelDevice()) { - switch (pci_dev.device_id) { - case DSA_DID: - pci_dev.parts_no.push_back(0); - pci_dev.parts_no.push_back(1); - pci_dev.parts_no.push_back(2); - break; - case IAX_DID: - pci_dev.parts_no.push_back(0); - pci_dev.parts_no.push_back(1); - pci_dev.parts_no.push_back(2); - break; - case HQMV2_DID: - pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_HQM_PART_ID : SPR_MCC_HQM_PART_ID); - break; - case QATV2_DID: - pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_QAT_PART_ID : SPR_MCC_QAT_PART_ID); - break; - default: - continue; - } - part.child_pci_devs.push_back(pci_dev); - } - stack.parts.push_back(part); - } - } - } - } - - iio_on_socket.stacks.push_back(stack); - return true; -} - -bool EagleStreamPlatformMapping::isDmiStack(int unit) -{ - const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type); - - return stacks_enumeration[esDMI] == unit; -} - -bool EagleStreamPlatformMapping::isPcieStack(int unit) -{ - const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type); - - return stacks_enumeration[esPCIe0] == unit || stacks_enumeration[esPCIe1] == unit || - stacks_enumeration[esPCIe2] == unit || stacks_enumeration[esPCIe3] == unit || - stacks_enumeration[esPCIe4] == unit; -} - -bool EagleStreamPlatformMapping::isDinoStack(int unit) -{ - const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type); - - return stacks_enumeration[esDINO0] == unit || stacks_enumeration[esDINO1] == unit || - stacks_enumeration[esDINO2] == unit || stacks_enumeration[esDINO3] == unit; -} - -bool EagleStreamPlatformMapping::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - if (isDmiStack(unit)) { - return eagleStreamDmiStackProbe(unit, address, iio_on_socket); - } - else if (isPcieStack(unit)) { - return eagleStreamPciStackProbe(unit, address, iio_on_socket); - } - else if (isDinoStack(unit)) { - return eagleStreamAcceleratorStackProbe(unit, address, iio_on_socket); - } - - return false; -} - -bool EagleStreamPlatformMapping::pciTreeDiscover(std::vector& iios) -{ - if (!setChopValue()) return false; - - std::map> root_buses; - if (!getRootBuses(root_buses)) - { - return false; - } - - for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) { - auto rbs_on_socket = iter->second; - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = iter->first; - for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) { - if (!stackProbe(rb->first, rb->second, iio_on_socket)) { - return false; - } - } - std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); - iios.push_back(iio_on_socket); - } - - return true; -} - -bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) -{ - struct iio_stack stack; - stack.busno = root_bus; - stack.iio_unit_id = stack_pmon_id; - stack.stack_name = grr_iio_stack_names[stack_pmon_id]; - - struct iio_bifurcated_part pch_part; - pch_part.part_id = 7; - struct pci* pci_dev = &pch_part.root_pci_dev; - pci_dev->bdf.busno = root_bus; - - if (probe_pci(pci_dev)) { - probeDeviceRange(pch_part.child_pci_devs, pci_dev->bdf.domainno, pci_dev->secondary_bus_number, pci_dev->subordinate_bus_number); - stack.parts.push_back(pch_part); - iio_on_socket.stacks.push_back(stack); - return true; - } - - return false; -} - -bool LoganvillePlatform::loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) -{ - struct iio_stack stack; - stack.busno = root_bus; - stack.iio_unit_id = stack_pmon_id; - stack.stack_name = grr_iio_stack_names[stack_pmon_id]; - - struct iio_bifurcated_part dlb_part; - dlb_part.part_id = GRR_DLB_PART_ID; - - for (uint8_t bus = root_bus; bus < 255; bus++) { - struct pci pci_dev(bus, 0x00, 0x00); - if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(HQMV25_DID)) { - dlb_part.root_pci_dev = pci_dev; - // Check Virtual RPs for DLB - for (uint8_t device = 0; device < 2; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev(bus, device, function); - if (probe_pci(&child_pci_dev)) { - dlb_part.child_pci_devs.push_back(child_pci_dev); - } - } - } - stack.parts.push_back(dlb_part); - iio_on_socket.stacks.push_back(stack); - return true; - } - } - - return false; -} - -bool LoganvillePlatform::loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) -{ - struct iio_stack stack; - stack.busno = root_bus; - stack.iio_unit_id = stack_pmon_id; - stack.stack_name = grr_iio_stack_names[stack_pmon_id]; - - // Probe NIS - { - struct iio_bifurcated_part nis_part; - nis_part.part_id = GRR_NIS_PART_ID; - struct pci pci_dev(root_bus, 0x04, 0x00); - if (probe_pci(&pci_dev)) { - nis_part.root_pci_dev = pci_dev; - for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 2; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev(bus, device, function); - if (probe_pci(&child_pci_dev)) { - nis_part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(nis_part); - } - } - - // Probe QAT - { - struct iio_bifurcated_part qat_part; - qat_part.part_id = GRR_QAT_PART_ID; - struct pci pci_dev(root_bus, 0x05, 0x00); - if (probe_pci(&pci_dev)) { - qat_part.root_pci_dev = pci_dev; - for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { - for (uint8_t device = 0; device < 17; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_pci_dev(bus, device, function); - if (probe_pci(&child_pci_dev)) { - qat_part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(qat_part); - } - } - - iio_on_socket.stacks.push_back(stack); - return true; -} - -bool LoganvillePlatform::pciTreeDiscover(std::vector& iios) -{ - std::map sad_id_bus_map; - if (!getSadIdRootBusMap(0, sad_id_bus_map)) { - return false; - } - - if (sad_id_bus_map.size() != grr_sad_to_pmu_id_mapping.size()) { - cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << grr_sad_to_pmu_id_mapping.size() << endl; - return false; - } - - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = 0; - - for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { - if (grr_sad_to_pmu_id_mapping.find(sad_id_bus_pair->first) == grr_sad_to_pmu_id_mapping.end()) { - cerr << "Cannot map SAD ID to PMON ID. Unknown ID: " << sad_id_bus_pair->first << endl; - return false; - } - int stack_pmon_id = grr_sad_to_pmu_id_mapping.at(sad_id_bus_pair->first); - int root_bus = sad_id_bus_pair->second; - switch (stack_pmon_id) { - case GRR_PCH_DSA_GEN4_PMON_ID: - if (!loganvillePchDsaPciStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { - return false; - } - break; - case GRR_DLB_PMON_ID: - if (!loganvilleDlbStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { - return false; - } - break; - case GRR_NIS_QAT_PMON_ID: - if (!loganvilleNacStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { - return false; - } - break; - default: - return false; - } - } - - std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); - - iios.push_back(iio_on_socket); - - return true; -} - -bool Xeon6thNextGenPlatform::getRootBuses(std::map> &root_buses) -{ - bool mapped = true; - for (uint32_t domain = 0; mapped; domain++) { - mapped = false; - for (uint16_t b = 0; b < 256; b++) { - for (uint8_t d = 0; d < 32; d++) { - for (uint8_t f = 0; f < 8; f++) { - struct pci pci_dev(domain, b, d, f); - if (!probe_pci(&pci_dev)) { - break; - } - if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) { - continue; - } - - std::uint32_t cpuBusValid; - std::vector cpuBusNo; - int package_id; - - if (!get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id)) { - return false; - } - - for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) { - if (!((cpuBusValid >> cpuBusId) & 0x1)) { - cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl; - continue; - } - int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff; - root_buses[package_id][cpuBusId] = bdf(domain, rootBus, 0, 0); - cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ")" - << " package " << package_id << endl; - mapped = true; - } - } - } - } - } - return !root_buses.empty(); -} - -bool Xeon6thNextGenPlatform::pciTreeDiscover(std::vector& iios) -{ - std::map> root_buses; - if (!getRootBuses(root_buses)) - { - return false; - } - - for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) { - auto rbs_on_socket = iter->second; - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = iter->first; - for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) { - if (!stackProbe(rb->first, rb->second, iio_on_socket)) { - return false; - } - } - std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); - iios.push_back(iio_on_socket); - } - - return true; -} - -bool BirchStreamPlatform::birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - /* - * All stacks manage PCIe 5.0 Root Ports. Bifurcated Root Ports A-H appear as devices 2-9. - */ - struct iio_stack stack; - stack.domain = address.domainno; - stack.busno = address.busno; - stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit); - stack.stack_name = srf_iio_stack_names[stack.iio_unit_id]; - for (int slot = 2; slot < 9; ++slot) - { - struct pci root_pci_dev; - root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0); - if (probe_pci(&root_pci_dev)) - { - struct iio_bifurcated_part part; - part.part_id = slot - 2; - part.root_pci_dev = root_pci_dev; - for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) { - for (uint8_t d = 0; d < 32; ++d) { - for (uint8_t f = 0; f < 8; ++f) { - struct pci child_pci_dev(address.domainno, b, d, f); - if (probe_pci(&child_pci_dev)) { - child_pci_dev.parts_no.push_back(part.part_id); - part.child_pci_devs.push_back(child_pci_dev); - } - } - } - } - stack.parts.push_back(part); - } - } - iio_on_socket.stacks.push_back(stack); - return true; -} - -bool BirchStreamPlatform::birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - struct iio_stack stack; - stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit); - stack.domain = address.domainno; - stack.busno = address.busno; - stack.stack_name = srf_iio_stack_names[stack.iio_unit_id]; - - /* - * Instance of DSA(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 1, function 0 - * Instance of IAX(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 2, function 0 - * Instance of QAT(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (9, 13, 21, 17), device 0, function 0 - * Instance of HQM(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (10, 14, 22, 18), device 0, function 0 - */ - auto process_pci_dev = [](int domainno, int busno, int devno, int part_number, iio_bifurcated_part& part) - { - struct pci pci_dev(domainno, busno, devno, 0); - if (probe_pci(&pci_dev) && pci_dev.isIntelDevice()) { - part.part_id = part_number; - pci_dev.parts_no.push_back(part_number); - part.child_pci_devs.push_back(pci_dev); - return true; - } - return false; - }; - - auto add_pci_part = [&](int domainno, int busno, int devno, int part_number) { - struct iio_bifurcated_part part; - if (process_pci_dev(domainno, busno, devno, part_number, part)) { - stack.parts.push_back(part); - } - }; - - add_pci_part(address.domainno, address.busno, 1, SRF_DSA_IAX_PART_NUMBER); - add_pci_part(address.domainno, address.busno, 2, SRF_DSA_IAX_PART_NUMBER); - - add_pci_part(address.domainno, address.busno + 1, 0, SRF_QAT_PART_NUMBER); - - /* Bus number for HQM is higher on 3 than DSA bus number */ - add_pci_part(address.domainno, address.busno + 3, 0, SRF_HQM_PART_NUMBER); - - if (!stack.parts.empty()) { - iio_on_socket.stacks.push_back(stack); - } - - return true; -} - -bool BirchStreamPlatform::isPcieStack(int unit) -{ - return srf_pcie_stacks.find(unit) != srf_pcie_stacks.end(); -} - -/* - * HC is the name of DINO stacks as we had on SPR - */ -bool BirchStreamPlatform::isRootHcStack(int unit) -{ - return SRF_HC0_SAD_BUS_ID == unit || SRF_HC1_SAD_BUS_ID == unit || - SRF_HC2_SAD_BUS_ID == unit || SRF_HC3_SAD_BUS_ID == unit; -} - -bool BirchStreamPlatform::isPartHcStack(int unit) -{ - return isRootHcStack(unit - 1) || isRootHcStack(unit - 2); -} - -bool BirchStreamPlatform::isUboxStack(int unit) -{ - return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; -} - -bool BirchStreamPlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - if (isPcieStack(unit)) { - return birchStreamPciStackProbe(unit, address, iio_on_socket); - } - else if (isRootHcStack(unit)) { - return birchStreamAcceleratorStackProbe(unit, address, iio_on_socket); - } - else if (isPartHcStack(unit)) { - cout << "Found a part of HC stack. Stack ID - " << unit << " domain " << address.domainno - << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << ". Don't probe it again." << endl; - return true; - } - else if (isUboxStack(unit)) { - cout << "Found UBOX stack. Stack ID - " << unit << " domain " << address.domainno - << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl; - return true; - } - - cout << "Unknown stack ID " << unit << " domain " << address.domainno << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl; - - return false; -} - -const std::string generate_stack_str(const int unit) -{ - static const std::string stack_str = "Stack "; - std::stringstream ss; - ss << stack_str << std::setw(2) << unit; - return ss.str(); -} - -bool KasseyvillePlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - // Skip UBOX buses - if (isUboxStack(unit)) return true; - - // To suppress compilation warning - (void)address; - - struct iio_stack stack; - stack.iio_unit_id = unit; - stack.stack_name = generate_stack_str(unit); - iio_on_socket.stacks.push_back(stack); - return true; -} - -void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int domain, int secondary, int subordinate) -{ - for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) { - for (uint8_t device = 0; device < 32; device++) { - for (uint8_t function = 0; function < 8; function++) { - struct pci child_dev; - child_dev.bdf.domainno = domain; - child_dev.bdf.busno = bus; - child_dev.bdf.devno = device; - child_dev.bdf.funcno = function; - if (probe_pci(&child_dev)) { - if (secondary < child_dev.secondary_bus_number && subordinate < child_dev.subordinate_bus_number) { - probeDeviceRange(child_dev.child_pci_devs, domain, child_dev.secondary_bus_number, child_dev.subordinate_bus_number); - } - pci_devs.push_back(child_dev); - } - } - } - } -} - -std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count) -{ - switch (cpu_family_model) { - case PCM::SKX: - return std::unique_ptr{new PurleyPlatformMapping(cpu_family_model, sockets_count)}; - case PCM::ICX: - return std::unique_ptr{new WhitleyPlatformMapping(cpu_family_model, sockets_count)}; - case PCM::SNOWRIDGE: - return std::unique_ptr{new JacobsvillePlatformMapping(cpu_family_model, sockets_count)}; - case PCM::SPR: - case PCM::EMR: - return std::unique_ptr{new EagleStreamPlatformMapping(cpu_family_model, sockets_count)}; - case PCM::GRR: - return std::unique_ptr{new LoganvillePlatform(cpu_family_model, sockets_count)}; - case PCM::SRF: - case PCM::GNR: - return std::unique_ptr{new BirchStreamPlatform(cpu_family_model, sockets_count)}; - case PCM::GNR_D: - std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for Graniterapids-D is provided" << std::endl; - return std::unique_ptr{new KasseyvillePlatform(cpu_family_model, sockets_count)}; - default: - return nullptr; - } -} - ccr* get_ccr(PCM* m, uint64_t& ccr) { switch (m->getCPUFamilyModel()) @@ -1552,20 +471,6 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) return m_results; } -void initializeIOStacksStructure( std::vector& iios ) -{ - PCM * m = PCM::getInstance(); - auto mapping = IPlatformMapping::getPlatformMapping(m->getCPUFamilyModel(), m->getNumSockets()); - if (!mapping) { - cerr << "Failed to discover pci tree: unknown platform" << endl; - exit(EXIT_FAILURE); - } - - if (!mapping->pciTreeDiscover(iios)) { - exit(EXIT_FAILURE); - } -} - void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap) { opcodeFieldMap["opcode"] = PCM::OPCODE; diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 632fee1a..ab88a17b 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -1,9 +1,12 @@ // SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2017-2022, Intel Corporation +// Copyright (c) 2017-2025, Intel Corporation // written by Patrick Lu, // Aaron Cruz +// Alexander Antonov // and others +#pragma once + #include "cpucounters.h" #ifdef _MSC_VER @@ -14,14 +17,8 @@ #endif #include -#include -#include -#include -#include // std::length_error #include -#include #include -#include #ifdef _MSC_VER #include "freegetopt/getopt.h" @@ -35,453 +32,6 @@ using namespace pcm; #define PCM_DELAY_DEFAULT 3.0 // in seconds -#define QAT_DID 0x18DA -#define NIS_DID 0x18D1 -#define HQM_DID 0x270B - -#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT) -#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS) - -#define ROOT_BUSES_OFFSET 0xCC -#define ROOT_BUSES_OFFSET_2 0xD0 - -#define SKX_SOCKETID_UBOX_DID 0x2014 -#define SKX_UBOX_DEVICE_NUM 0x08 -#define SKX_UBOX_FUNCTION_NUM 0x02 -#define SKX_BUS_NUM_STRIDE 8 -//the below LNID and GID applies to Skylake Server -#define SKX_UNC_SOCKETID_UBOX_LNID_OFFSET 0xC0 -#define SKX_UNC_SOCKETID_UBOX_GID_OFFSET 0xD4 - -static const std::string iio_stack_names[6] = { - "IIO Stack 0 - CBDMA/DMI ", - "IIO Stack 1 - PCIe0 ", - "IIO Stack 2 - PCIe1 ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - MCP0 ", - "IIO Stack 5 - MCP1 " -}; - -static const std::string skx_iio_stack_names[6] = { - "IIO Stack 0 - CBDMA/DMI ", - "IIO Stack 1 - PCIe0 ", - "IIO Stack 2 - PCIe1 ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - MCP0 ", - "IIO Stack 5 - MCP1 " -}; - -static const std::string icx_iio_stack_names[6] = { - "IIO Stack 0 - PCIe0 ", - "IIO Stack 1 - PCIe1 ", - "IIO Stack 2 - MCP ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - PCIe3 ", - "IIO Stack 5 - CBDMA/DMI " -}; - -static const std::string icx_d_iio_stack_names[6] = { - "IIO Stack 0 - MCP ", - "IIO Stack 1 - PCIe0 ", - "IIO Stack 2 - CBDMA/DMI ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - PCIe3 ", - "IIO Stack 5 - PCIe1 " -}; - -static const std::string snr_iio_stack_names[5] = { - "IIO Stack 0 - QAT ", - "IIO Stack 1 - CBDMA/DMI ", - "IIO Stack 2 - NIS ", - "IIO Stack 3 - HQM ", - "IIO Stack 4 - PCIe " -}; - -#define ICX_CBDMA_DMI_SAD_ID 0 -#define ICX_MCP_SAD_ID 3 - -#define ICX_PCH_PART_ID 0 -#define ICX_CBDMA_PART_ID 3 - -#define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4 -#define SNR_ICX_MESH2IIO_MMAP_DID 0x09A2 - -#define ICX_VMD_PCI_DEVNO 0x00 -#define ICX_VMD_PCI_FUNCNO 0x05 - -static const std::map icx_sad_to_pmu_id_mapping = { - { ICX_CBDMA_DMI_SAD_ID, 5 }, - { 1, 0 }, - { 2, 1 }, - { ICX_MCP_SAD_ID, 2 }, - { 4, 3 }, - { 5, 4 } -}; - -static const std::map icx_d_sad_to_pmu_id_mapping = { - { ICX_CBDMA_DMI_SAD_ID, 2 }, - { 1, 5 }, - { 2, 1 }, - { ICX_MCP_SAD_ID, 0 }, - { 4, 3 }, - { 5, 4 } -}; - -#define SNR_ACCELERATOR_PART_ID 4 - -#define SNR_ROOT_PORT_A_DID 0x334A - -#define SNR_CBDMA_DMI_SAD_ID 0 -#define SNR_PCIE_GEN3_SAD_ID 1 -#define SNR_HQM_SAD_ID 2 -#define SNR_NIS_SAD_ID 3 -#define SNR_QAT_SAD_ID 4 - -static const std::map snr_sad_to_pmu_id_mapping = { - { SNR_CBDMA_DMI_SAD_ID, 1 }, - { SNR_PCIE_GEN3_SAD_ID, 4 }, - { SNR_HQM_SAD_ID , 3 }, - { SNR_NIS_SAD_ID , 2 }, - { SNR_QAT_SAD_ID , 0 } -}; - -#define HQMV2_DID 0x2710 // Hardware Queue Manager v2 -#define HQMV25_DID 0x2714 // Hardware Queue Manager v2.5 -#define DSA_DID 0x0b25 // Data Streaming Accelerator (DSA) -#define IAX_DID 0x0cfe // In-Memory Database Analytics Accelerator (IAX) -#define QATV2_DID 0x4940 // QuickAssist (CPM) v2 - -#define SPR_DMI_PART_ID 7 -#define SPR_XCC_HQM_PART_ID 5 -#define SPR_MCC_HQM_PART_ID 4 -#define SPR_XCC_QAT_PART_ID 4 -#define SPR_MCC_QAT_PART_ID 5 -#define SPR_SAD_CONTROL_CFG_OFFSET SNR_ICX_SAD_CONTROL_CFG_OFFSET - -#define SPR_PCU_CR3_DID 0x325b -#define SPR_PCU_CR3_REG_DEVICE 0x1e -#define SPR_PCU_CR3_REG_FUNCTION 0x03 -#define SPR_CAPID4_OFFSET 0x94 -#define SPR_CAPID4_GET_PHYSICAL_CHOP(capid4) ((capid4 >> 6) & 3) -#define SPR_PHYSICAL_CHOP_XCC 0b11 -#define SPR_PHYSICAL_CHOP_MCC 0b01 - -#define SPR_XCC_DMI_PMON_ID 1 -#define SPR_XCC_PCIE_GEN5_0_PMON_ID 2 -#define SPR_XCC_PCIE_GEN5_1_PMON_ID 4 -#define SPR_XCC_PCIE_GEN5_2_PMON_ID 6 -#define SPR_XCC_PCIE_GEN5_3_PMON_ID 7 -#define SPR_XCC_PCIE_GEN5_4_PMON_ID 9 -#define SPR_XCC_IDX0_PMON_ID 0 -#define SPR_XCC_IDX1_PMON_ID 3 -#define SPR_XCC_IDX2_PMON_ID 5 -#define SPR_XCC_IDX3_PMON_ID 8 - -const std::map spr_xcc_sad_to_pmu_id_mapping = { - { 0, SPR_XCC_DMI_PMON_ID }, - { 1, SPR_XCC_PCIE_GEN5_0_PMON_ID }, - { 2, SPR_XCC_PCIE_GEN5_1_PMON_ID }, - { 3, SPR_XCC_PCIE_GEN5_2_PMON_ID }, - { 4, SPR_XCC_PCIE_GEN5_3_PMON_ID }, - { 5, SPR_XCC_PCIE_GEN5_4_PMON_ID }, - { 8, SPR_XCC_IDX0_PMON_ID }, - { 9, SPR_XCC_IDX1_PMON_ID }, - { 10, SPR_XCC_IDX2_PMON_ID }, - { 11, SPR_XCC_IDX3_PMON_ID } -}; - -#define SPR_MCC_DMI_PMON_ID 10 -#define SPR_MCC_PCIE_GEN5_0_PMON_ID 0 // assumption -#define SPR_MCC_PCIE_GEN5_1_PMON_ID 1 -#define SPR_MCC_PCIE_GEN5_2_PMON_ID 2 -#define SPR_MCC_PCIE_GEN5_3_PMON_ID 4 // assumption -#define SPR_MCC_PCIE_GEN5_4_PMON_ID 5 -#define SPR_MCC_IDX0_PMON_ID 3 - -const std::map spr_mcc_sad_to_pmu_id_mapping = { - { 0, SPR_MCC_PCIE_GEN5_0_PMON_ID }, - { 1, SPR_MCC_PCIE_GEN5_1_PMON_ID }, - { 2, SPR_MCC_PCIE_GEN5_2_PMON_ID }, - { 3, SPR_MCC_DMI_PMON_ID }, - { 4, SPR_MCC_PCIE_GEN5_3_PMON_ID }, - { 5, SPR_MCC_PCIE_GEN5_4_PMON_ID }, - { 8, SPR_MCC_IDX0_PMON_ID }, -}; - -static const std::string spr_xcc_iio_stack_names[] = { - "IIO Stack 0 - IDX0 ", - "IIO Stack 1 - DMI ", - "IIO Stack 2 - PCIe0 ", - "IIO Stack 3 - IDX1 ", - "IIO Stack 4 - PCIe1 ", - "IIO Stack 5 - IDX2 ", - "IIO Stack 6 - PCIe2 ", - "IIO Stack 7 - PCIe3", - "IIO Stack 8 - IDX3 ", - "IIO Stack 9 - PCIe4", - "IIO Stack 10 - NONE ", - "IIO Stack 11 - NONE ", -}; - -/* - * SPR MCC has 7 I/O stacks but PMON block for DMI has ID number 10. - * And just to follow such enumeration keep Stack 10 for DMI. - */ -static const std::string spr_mcc_iio_stack_names[] = { - "IIO Stack 0 - PCIe0 ", - "IIO Stack 1 - PCIe1 ", - "IIO Stack 2 - PCIe2 ", - "IIO Stack 3 - IDX0 ", - "IIO Stack 4 - PCIe3 ", - "IIO Stack 5 - PCIe4 ", - "IIO Stack 6 - NONE ", - "IIO Stack 7 - NONE ", - "IIO Stack 8 - NONE ", - "IIO Stack 9 - NONE ", - "IIO Stack 10 - DMI ", -}; - -// MS2IOSF stack IDs in CHA notation -#define GRR_PCH_DSA_GEN4_SAD_ID 0 -#define GRR_DLB_SAD_ID 1 -#define GRR_NIS_QAT_SAD_ID 2 - -#define GRR_PCH_DSA_GEN4_PMON_ID 2 -#define GRR_DLB_PMON_ID 1 -#define GRR_NIS_QAT_PMON_ID 0 - -// Stack 0 contains PCH, DSA and CPU PCIe Gen4 Complex -const std::map grr_sad_to_pmu_id_mapping = { - { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID }, - { GRR_DLB_SAD_ID, GRR_DLB_PMON_ID }, - { GRR_NIS_QAT_SAD_ID, GRR_NIS_QAT_PMON_ID }, -}; - -#define GRR_DLB_PART_ID 0 -#define GRR_NIS_PART_ID 0 -#define GRR_QAT_PART_ID 1 - -static const std::string grr_iio_stack_names[3] = { - "IIO Stack 0 - NIS/QAT ", - "IIO Stack 1 - HQM ", - "IIO Stack 2 - PCH/DSA/PCIe " -}; - -#define EMR_DMI_PMON_ID 7 -#define EMR_PCIE_GEN5_0_PMON_ID 1 -#define EMR_PCIE_GEN5_1_PMON_ID 2 -#define EMR_PCIE_GEN5_2_PMON_ID 3 -#define EMR_PCIE_GEN5_3_PMON_ID 8 -#define EMR_PCIE_GEN5_4_PMON_ID 6 -#define EMR_IDX0_PMON_ID 0 -#define EMR_IDX1_PMON_ID 4 -#define EMR_IDX2_PMON_ID 5 -#define EMR_IDX3_PMON_ID 9 - -const std::map emr_sad_to_pmu_id_mapping = { - { 0, EMR_DMI_PMON_ID }, - { 1, EMR_PCIE_GEN5_0_PMON_ID }, - { 2, EMR_PCIE_GEN5_1_PMON_ID }, - { 3, EMR_PCIE_GEN5_2_PMON_ID }, - { 4, EMR_PCIE_GEN5_3_PMON_ID }, - { 5, EMR_PCIE_GEN5_4_PMON_ID }, - { 8, EMR_IDX0_PMON_ID }, - { 9, EMR_IDX1_PMON_ID }, - { 10, EMR_IDX2_PMON_ID }, - { 11, EMR_IDX3_PMON_ID } -}; - -static const std::string emr_iio_stack_names[] = { - "IIO Stack 0 - IDX0 ", - "IIO Stack 1 - PCIe3 ", - "IIO Stack 2 - PCIe0 ", - "IIO Stack 3 - IDX1 ", - "IIO Stack 4 - PCIe1 ", - "IIO Stack 5 - IDX2 ", - "IIO Stack 6 - PCIe2 ", - "IIO Stack 7 - DMI", - "IIO Stack 8 - IDX3 ", - "IIO Stack 9 - PCIe4", - "IIO Stack 10 - NONE ", - "IIO Stack 11 - NONE ", -}; - -enum EagleStreamPlatformStacks -{ - esDMI = 0, - esPCIe0, - esPCIe1, - esPCIe2, - esPCIe3, - esPCIe4, - esDINO0, - esDINO1, - esDINO2, - esDINO3, - esEndOfList -}; - -const std::vector spr_xcc_stacks_enumeration = { - /* esDMI */ SPR_XCC_DMI_PMON_ID, - /* esPCIe0 */ SPR_XCC_PCIE_GEN5_0_PMON_ID, - /* esPCIe1 */ SPR_XCC_PCIE_GEN5_1_PMON_ID, - /* esPCIe2 */ SPR_XCC_PCIE_GEN5_2_PMON_ID, - /* esPCIe3 */ SPR_XCC_PCIE_GEN5_3_PMON_ID, - /* esPCIe4 */ SPR_XCC_PCIE_GEN5_4_PMON_ID, - /* esDINO0 */ SPR_XCC_IDX0_PMON_ID, - /* esDINO1 */ SPR_XCC_IDX1_PMON_ID, - /* esDINO2 */ SPR_XCC_IDX2_PMON_ID, - /* esDINO3 */ SPR_XCC_IDX3_PMON_ID, -}; - -const std::vector spr_mcc_stacks_enumeration = { - /* esDMI */ SPR_MCC_DMI_PMON_ID, - /* esPCIe0 */ SPR_MCC_PCIE_GEN5_0_PMON_ID, - /* esPCIe1 */ SPR_MCC_PCIE_GEN5_1_PMON_ID, - /* esPCIe2 */ SPR_MCC_PCIE_GEN5_2_PMON_ID, - /* esPCIe3 */ SPR_MCC_PCIE_GEN5_3_PMON_ID, - /* esPCIe4 */ SPR_MCC_PCIE_GEN5_4_PMON_ID, - /* esDINO0 */ SPR_MCC_IDX0_PMON_ID, -}; - -const std::vector emr_stacks_enumeration = { - /* esDMI */ EMR_DMI_PMON_ID, - /* esPCIe0 */ EMR_PCIE_GEN5_0_PMON_ID, - /* esPCIe1 */ EMR_PCIE_GEN5_1_PMON_ID, - /* esPCIe2 */ EMR_PCIE_GEN5_2_PMON_ID, - /* esPCIe3 */ EMR_PCIE_GEN5_3_PMON_ID, - /* esPCIe4 */ EMR_PCIE_GEN5_4_PMON_ID, - /* esDINO0 */ EMR_IDX0_PMON_ID, - /* esDINO1 */ EMR_IDX1_PMON_ID, - /* esDINO2 */ EMR_IDX2_PMON_ID, - /* esDINO3 */ EMR_IDX3_PMON_ID, -}; - -enum class EagleStreamSupportedTypes -{ - esInvalid = -1, - esSprXcc, - esSprMcc, - esEmrXcc -}; - -typedef EagleStreamSupportedTypes estype; - -const std::map> es_stacks_enumeration = { - {estype::esSprXcc, spr_xcc_stacks_enumeration}, - {estype::esSprMcc, spr_mcc_stacks_enumeration}, - {estype::esEmrXcc, emr_stacks_enumeration }, -}; - -const std::map es_stack_names = { - {estype::esSprXcc, spr_xcc_iio_stack_names}, - {estype::esSprMcc, spr_mcc_iio_stack_names}, - {estype::esEmrXcc, emr_iio_stack_names }, -}; - -const std::map> es_sad_to_pmu_id_mapping = { - {estype::esSprXcc, spr_xcc_sad_to_pmu_id_mapping}, - {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping}, - {estype::esEmrXcc, emr_sad_to_pmu_id_mapping }, -}; - -#define SRF_PE0_PMON_ID 3 -#define SRF_PE1_PMON_ID 4 -#define SRF_PE2_PMON_ID 2 -#define SRF_PE3_PMON_ID 5 -/* - * There are platform configuration when FlexUPI stacks (stacks 5 and 6) are enabled as - * PCIe stack and PCIe ports are disabled (ports 2 and 3) and vice sersa. See details here: - * In these cases the PMON IDs are different. - * So, defines with _FLEX_ are applicable for cases when FlexUPI stacks - * are working as PCIe ports. - */ -#define SRF_PE4_PMON_ID 11 -#define SRF_FLEX_PE4_PMON_ID 13 -#define SRF_PE5_PMON_ID 12 -#define SRF_FLEX_PE5_PMON_ID 10 - -#define SRF_PE6_PMON_ID 0 -#define SRF_PE7_PMON_ID 7 -#define SRF_PE8_PMON_ID 8 -#define SRF_HC0_PMON_ID 1 -#define SRF_HC1_PMON_ID 6 -#define SRF_HC2_PMON_ID 9 -#define SRF_HC3_PMON_ID 14 - -#define SRF_PE0_SAD_BUS_ID 2 -#define SRF_PE1_SAD_BUS_ID 3 -#define SRF_PE2_SAD_BUS_ID 1 -#define SRF_PE3_SAD_BUS_ID 4 -#define SRF_PE4_SAD_BUS_ID 29 -#define SRF_FLEX_PE4_SAD_BUS_ID SRF_PE4_SAD_BUS_ID -#define SRF_PE5_SAD_BUS_ID 26 -#define SRF_FLEX_PE5_SAD_BUS_ID SRF_PE5_SAD_BUS_ID -#define SRF_PE6_SAD_BUS_ID 0 // UPI0 -#define SRF_PE7_SAD_BUS_ID 5 // UPI1 -#define SRF_PE8_SAD_BUS_ID 28 // UPI2 -#define SRF_UBOXA_SAD_BUS_ID 30 -#define SRF_UBOXB_SAD_BUS_ID 31 - -const std::set srf_pcie_stacks({ - SRF_PE0_SAD_BUS_ID, - SRF_PE1_SAD_BUS_ID, - SRF_PE2_SAD_BUS_ID, - SRF_PE3_SAD_BUS_ID, - SRF_PE4_SAD_BUS_ID, - SRF_FLEX_PE4_SAD_BUS_ID, - SRF_PE5_SAD_BUS_ID, - SRF_FLEX_PE5_SAD_BUS_ID, - SRF_PE6_SAD_BUS_ID, - SRF_PE7_SAD_BUS_ID, - SRF_PE8_SAD_BUS_ID, -}); - -#define SRF_HC0_SAD_BUS_ID 8 -#define SRF_HC1_SAD_BUS_ID 12 -#define SRF_HC2_SAD_BUS_ID 20 -#define SRF_HC3_SAD_BUS_ID 16 - -const std::map srf_sad_to_pmu_id_mapping = { - { SRF_PE0_SAD_BUS_ID, SRF_PE0_PMON_ID }, - { SRF_PE1_SAD_BUS_ID, SRF_PE1_PMON_ID }, - { SRF_PE2_SAD_BUS_ID, SRF_PE2_PMON_ID }, - { SRF_PE3_SAD_BUS_ID, SRF_PE3_PMON_ID }, - { SRF_PE4_SAD_BUS_ID, SRF_PE4_PMON_ID }, - { SRF_FLEX_PE4_SAD_BUS_ID, SRF_FLEX_PE4_PMON_ID }, - { SRF_PE5_SAD_BUS_ID, SRF_PE5_PMON_ID }, - { SRF_FLEX_PE5_SAD_BUS_ID, SRF_FLEX_PE5_PMON_ID }, - { SRF_PE6_SAD_BUS_ID, SRF_PE6_PMON_ID }, - { SRF_PE7_SAD_BUS_ID, SRF_PE7_PMON_ID }, - { SRF_PE8_SAD_BUS_ID, SRF_PE8_PMON_ID }, - { SRF_HC0_SAD_BUS_ID, SRF_HC0_PMON_ID }, - { SRF_HC1_SAD_BUS_ID, SRF_HC1_PMON_ID }, - { SRF_HC2_SAD_BUS_ID, SRF_HC2_PMON_ID }, - { SRF_HC3_SAD_BUS_ID, SRF_HC3_PMON_ID }, -}; - -#define SRF_DSA_IAX_PART_NUMBER 0 -#define SRF_HQM_PART_NUMBER 5 -#define SRF_QAT_PART_NUMBER 4 - -static const std::string srf_iio_stack_names[] = { - "IIO Stack 0 - PCIe6 ", // SRF_PE6_PMON_ID 0 - "IIO Stack 1 - HCx0 ", // SRF_HC0_PMON_ID 1 - "IIO Stack 2 - PCIe2 ", // SRF_PE2_PMON_ID 2 - "IIO Stack 3 - PCIe0 ", // SRF_PE0_PMON_ID 3 - "IIO Stack 4 - PCIe1 ", // SRF_PE1_PMON_ID 4 - "IIO Stack 5 - PCIe3 ", // SRF_PE3_PMON_ID 5 - "IIO Stack 6 - HCx1 ", // SRF_HC1_PMON_ID 6 - "IIO Stack 7 - PCIe7 ", // SRF_PE7_PMON_ID 7 - "IIO Stack 8 - PCIe8 ", // SRF_PE8_PMON_ID 8 - "IIO Stack 9 - HCx3 ", // SRF_HC3_PMON_ID 9 - "IIO Stack 10 - Flex PCIe5", // SRF_FLEX_PE5_PMON_ID 10 - "IIO Stack 11 - PCIe4 ", // SRF_PE4_PMON_ID 11 - "IIO Stack 12 - PCIe5 ", // SRF_PE5_PMON_ID 12 - "IIO Stack 13 - Flex PCIe4", // SRF_FLEX_PE4_PMON_ID 13 - "IIO Stack 14 - HCx2 ", // SRF_HC2_PMON_ID 14 -}; - struct iio_counter : public counter { std::vector data; }; @@ -537,143 +87,6 @@ class PcmIioOutputBuilder { std::unique_ptr getDisplayBuilder(struct pcm_iio_config& config); -class IPlatformMapping { -private: - uint32_t m_sockets; - uint32_t m_model; -protected: - void probeDeviceRange(std::vector &child_pci_devs, int domain, int secondary, int subordinate); -public: - IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} - virtual ~IPlatformMapping() {}; - static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count); - virtual bool pciTreeDiscover(std::vector& iios) = 0; - - uint32_t socketsCount() const { return m_sockets; } - uint32_t cpuId() const { return m_model; } -}; - -// Mapping for SkyLake Server. -class PurleyPlatformMapping: public IPlatformMapping { -private: - void getUboxBusNumbers(std::vector& ubox); -public: - PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} - ~PurleyPlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; -}; - -class IPlatformMapping10Nm: public IPlatformMapping { -private: -public: - IPlatformMapping10Nm(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} - ~IPlatformMapping10Nm() = default; - bool getSadIdRootBusMap(uint32_t socket_id, std::map& sad_id_bus_map); -}; - -// Mapping for IceLake Server. -class WhitleyPlatformMapping: public IPlatformMapping10Nm { -private: - const bool icx_d; - const std::map& sad_to_pmu_id_mapping; - const std::string * iio_stack_names; -public: - WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count), - icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), - sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping), - iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names) - { - } - ~WhitleyPlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; -}; - -// Mapping for Snowridge. -class JacobsvillePlatformMapping: public IPlatformMapping10Nm { -private: -public: - JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} - ~JacobsvillePlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; - bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); -}; - -class EagleStreamPlatformMapping: public IPlatformMapping -{ -private: - bool getRootBuses(std::map> &root_buses); - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool isDmiStack(int unit); - bool isPcieStack(int unit); - bool isDinoStack(int unit); - std::uint32_t m_chop; - EagleStreamSupportedTypes m_es_type; -public: - EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {} - ~EagleStreamPlatformMapping() = default; - bool setChopValue(); - bool isXccPlatform() const { return m_chop == kXccChop; } - - const std::uint32_t kXccChop = 0b11; - const std::uint32_t kMccChop = 0b01; - - bool pciTreeDiscover(std::vector& iios) override; -}; - -class LoganvillePlatform: public IPlatformMapping10Nm { -private: - bool loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); - bool loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); - bool loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); -public: - LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} - ~LoganvillePlatform() = default; - bool pciTreeDiscover(std::vector& iios) override; -}; - -class Xeon6thNextGenPlatform: public IPlatformMapping { -private: - bool getRootBuses(std::map> &root_buses); -protected: - virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; -public: - Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} - virtual ~Xeon6thNextGenPlatform() = default; - - bool pciTreeDiscover(std::vector& iios) override; -}; - -class BirchStreamPlatform: public Xeon6thNextGenPlatform { -private: - bool isPcieStack(int unit); - bool isRootHcStack(int unit); - bool isPartHcStack(int unit); - bool isUboxStack(int unit); - - bool birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); -protected: - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; -public: - BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} - ~BirchStreamPlatform() = default; -}; - -class KasseyvillePlatform: public Xeon6thNextGenPlatform { -private: - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool isUboxStack(int unit) - { - return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; - } -public: - KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} - ~KasseyvillePlatform() = default; -}; - int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map &ofm, std::string key, uint64 numValue); class CounterHandlerStrategy; @@ -701,8 +114,6 @@ class PcmIioDataCollector { static constexpr int COUNTERS_NUMBER = 4; }; -void initializeIOStacksStructure( std::vector& iios ); - void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap); void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap); diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp new file mode 100644 index 00000000..d3cf19dd --- /dev/null +++ b/src/pcm-iio-topology.cpp @@ -0,0 +1,1106 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2017-2025, Intel Corporation + +// written by Patrick Lu, +// Aaron Cruz +// Alexander Antonov +// and others + +#include "pcm-iio-topology.h" + +void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) +{ + for (uint16_t bus = 0; bus < 256; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci pci_dev; + pci_dev.bdf.busno = (uint8_t)bus; + pci_dev.bdf.devno = device; + pci_dev.bdf.funcno = function; + if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SKX_SOCKETID_UBOX_DID)) { + ubox.push_back(bus); + } + } + } + } +} + +bool PurleyPlatformMapping::pciTreeDiscover(std::vector& iios) +{ + std::vector ubox; + getUboxBusNumbers(ubox); + if (ubox.empty()) { + cerr << "UBOXs were not found! Program aborted" << endl; + return false; + } + + for (uint32_t socket_id = 0; socket_id < socketsCount(); socket_id++) { + if (!PciHandleType::exists(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM)) { + cerr << "No access to PCICFG\n" << endl; + return false; + } + uint64 cpubusno = 0; + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = socket_id; + PciHandleType h(0, ubox[socket_id], SKX_UBOX_DEVICE_NUM, SKX_UBOX_FUNCTION_NUM); + h.read64(ROOT_BUSES_OFFSET, &cpubusno); + + iio_on_socket.stacks.reserve(6); + for (int stack_id = 0; stack_id < 6; stack_id++) { + struct iio_stack stack; + stack.iio_unit_id = stack_id; + stack.busno = (uint8_t)(cpubusno >> (stack_id * SKX_BUS_NUM_STRIDE)); + stack.stack_name = skx_iio_stack_names[stack_id]; + for (uint8_t part_id = 0; part_id < 4; part_id++) { + struct iio_bifurcated_part part; + part.part_id = part_id; + struct pci *pci = &part.root_pci_dev; + struct bdf *bdf = &pci->bdf; + bdf->busno = stack.busno; + bdf->devno = part_id; + bdf->funcno = 0; + /* This is a workaround to catch some IIO stack does not exist */ + if (stack_id != 0 && stack.busno == 0) { + pci->exist = false; + } + else if (probe_pci(pci)) { + /* FIXME: for 0:0.0, we may need to scan from secondary switch down; lgtm [cpp/fixme-comment] */ + for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev; + child_pci_dev.bdf.busno = bus; + child_pci_dev.bdf.devno = device; + child_pci_dev.bdf.funcno = function; + if (probe_pci(&child_pci_dev)) { + part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + } + stack.parts.push_back(part); + } + + iio_on_socket.stacks.push_back(stack); + } + iios.push_back(iio_on_socket); + } + + return true; +} + +bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map& sad_id_bus_map) +{ + for (uint16_t bus = 0; bus < 256; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci pci_dev; + pci_dev.bdf.busno = (uint8_t)bus; + pci_dev.bdf.devno = device; + pci_dev.bdf.funcno = function; + if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SNR_ICX_MESH2IIO_MMAP_DID)) { + + PciHandleType h(0, bus, device, function); + std::uint32_t sad_ctrl_cfg; + h.read32(SNR_ICX_SAD_CONTROL_CFG_OFFSET, &sad_ctrl_cfg); + if (sad_ctrl_cfg == (std::numeric_limits::max)()) { + cerr << "Could not read SAD_CONTROL_CFG" << endl; + return false; + } + + if ((sad_ctrl_cfg & 0xf) == socket_id) { + uint8_t sid = (sad_ctrl_cfg >> 4) & 0x7; + sad_id_bus_map.insert(std::pair(sid, (uint8_t)bus)); + } + } + } + } + } + + if (sad_id_bus_map.empty()) { + cerr << "Could not find Root Port bus numbers" << endl; + return false; + } + + return true; +} + +bool WhitleyPlatformMapping::pciTreeDiscover(std::vector& iios) +{ + for (uint32_t socket = 0; socket < socketsCount(); socket++) { + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = socket; + std::map sad_id_bus_map; + if (!getSadIdRootBusMap(socket, sad_id_bus_map)) { + return false; + } + + { + struct iio_stack stack; + stack.iio_unit_id = sad_to_pmu_id_mapping.at(ICX_MCP_SAD_ID); + stack.stack_name = iio_stack_names[stack.iio_unit_id]; + iio_on_socket.stacks.push_back(stack); + } + + for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { + int sad_id = sad_id_bus_pair->first; + if (sad_to_pmu_id_mapping.find(sad_id) == + sad_to_pmu_id_mapping.end()) { + cerr << "Unknown SAD ID: " << sad_id << endl; + return false; + } + + if (sad_id == ICX_MCP_SAD_ID) { + continue; + } + + struct iio_stack stack; + int root_bus = sad_id_bus_pair->second; + if (sad_id == ICX_CBDMA_DMI_SAD_ID) { + // There is one DMA Controller on each socket + stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id); + stack.busno = root_bus; + stack.stack_name = iio_stack_names[stack.iio_unit_id]; + + // PCH is on socket 0 only + if (socket == 0) { + struct iio_bifurcated_part pch_part; + struct pci *pci = &pch_part.root_pci_dev; + struct bdf *bdf = &pci->bdf; + pch_part.part_id = ICX_PCH_PART_ID; + bdf->busno = root_bus; + bdf->devno = 0x00; + bdf->funcno = 0x00; + if (probe_pci(pci)) { + // Probe child devices only under PCH part. + for (uint8_t bus = pci->secondary_bus_number; bus <= pci->subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev; + child_pci_dev.bdf.busno = bus; + child_pci_dev.bdf.devno = device; + child_pci_dev.bdf.funcno = function; + if (probe_pci(&child_pci_dev)) { + pch_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(pch_part); + } + } + + struct iio_bifurcated_part part; + part.part_id = ICX_CBDMA_PART_ID; + struct pci *pci = &part.root_pci_dev; + struct bdf *bdf = &pci->bdf; + bdf->busno = root_bus; + bdf->devno = 0x01; + bdf->funcno = 0x00; + if (probe_pci(pci)) + stack.parts.push_back(part); + + iio_on_socket.stacks.push_back(stack); + continue; + } + stack.busno = root_bus; + stack.iio_unit_id = sad_to_pmu_id_mapping.at(sad_id); + stack.stack_name = iio_stack_names[stack.iio_unit_id]; + for (int slot = 2; slot < 6; slot++) { + struct pci pci; + pci.bdf.busno = root_bus; + pci.bdf.devno = slot; + pci.bdf.funcno = 0x00; + if (!probe_pci(&pci)) { + continue; + } + struct iio_bifurcated_part part; + part.part_id = slot - 2; + part.root_pci_dev = pci; + + for (uint8_t bus = pci.secondary_bus_number; bus <= pci.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev; + child_pci_dev.bdf.busno = bus; + child_pci_dev.bdf.devno = device; + child_pci_dev.bdf.funcno = function; + if (probe_pci(&child_pci_dev)) { + part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(part); + } + iio_on_socket.stacks.push_back(stack); + } + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + iios.push_back(iio_on_socket); + } + return true; +} + +bool JacobsvillePlatformMapping::JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack) +{ + uint16_t expected_dev_id; + auto sad_id = sad_id_bus_pair.first; + switch (sad_id) { + case SNR_HQM_SAD_ID: + expected_dev_id = HQM_DID; + break; + case SNR_NIS_SAD_ID: + expected_dev_id = NIS_DID; + break; + case SNR_QAT_SAD_ID: + expected_dev_id = QAT_DID; + break; + default: + return false; + } + stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id); + stack.stack_name = snr_iio_stack_names[stack.iio_unit_id]; + for (uint16_t bus = sad_id_bus_pair.second; bus < 256; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci pci_dev; + pci_dev.bdf.busno = (uint8_t)bus; + pci_dev.bdf.devno = device; + pci_dev.bdf.funcno = function; + if (probe_pci(&pci_dev)) { + if (expected_dev_id == pci_dev.device_id) { + struct iio_bifurcated_part part; + part.part_id = SNR_ACCELERATOR_PART_ID; + part.root_pci_dev = pci_dev; + stack.busno = (uint8_t)bus; + stack.parts.push_back(part); + return true; + } + } + } + } + } + return false; +} + +bool JacobsvillePlatformMapping::pciTreeDiscover(std::vector& iios) +{ + std::map sad_id_bus_map; + if (!getSadIdRootBusMap(0, sad_id_bus_map)) { + return false; + } + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = 0; + if (sad_id_bus_map.size() != snr_sad_to_pmu_id_mapping.size()) { + cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << snr_sad_to_pmu_id_mapping.size() << endl; + return false; + } + + for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { + int sad_id = sad_id_bus_pair->first; + struct iio_stack stack; + switch (sad_id) { + case SNR_CBDMA_DMI_SAD_ID: + { + int root_bus = sad_id_bus_pair->second; + stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id); + stack.stack_name = snr_iio_stack_names[stack.iio_unit_id]; + stack.busno = root_bus; + // DMA Controller + struct iio_bifurcated_part part; + part.part_id = 0; + struct pci pci_dev; + pci_dev.bdf.busno = root_bus; + pci_dev.bdf.devno = 0x01; + pci_dev.bdf.funcno = 0x00; + if (probe_pci(&pci_dev)) { + part.root_pci_dev = pci_dev; + stack.parts.push_back(part); + } + + part.part_id = 4; + pci_dev.bdf.busno = root_bus; + pci_dev.bdf.devno = 0x00; + pci_dev.bdf.funcno = 0x00; + if (probe_pci(&pci_dev)) { + for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev; + child_pci_dev.bdf.busno = bus; + child_pci_dev.bdf.devno = device; + child_pci_dev.bdf.funcno = function; + if (probe_pci(&child_pci_dev)) { + part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + part.root_pci_dev = pci_dev; + stack.parts.push_back(part); + } + } + break; + case SNR_PCIE_GEN3_SAD_ID: + { + int root_bus = sad_id_bus_pair->second; + stack.busno = root_bus; + stack.iio_unit_id = snr_sad_to_pmu_id_mapping.at(sad_id); + stack.stack_name = snr_iio_stack_names[stack.iio_unit_id]; + for (int slot = 4; slot < 8; slot++) { + struct pci pci_dev; + pci_dev.bdf.busno = root_bus; + pci_dev.bdf.devno = slot; + pci_dev.bdf.funcno = 0x00; + if (!probe_pci(&pci_dev)) { + continue; + } + int part_id = 4 + pci_dev.device_id - SNR_ROOT_PORT_A_DID; + if ((part_id < 0) || (part_id > 4)) { + cerr << "Invalid part ID " << part_id << endl; + return false; + } + struct iio_bifurcated_part part; + part.part_id = part_id; + part.root_pci_dev = pci_dev; + for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev; + child_pci_dev.bdf.busno = bus; + child_pci_dev.bdf.devno = device; + child_pci_dev.bdf.funcno = function; + if (probe_pci(&child_pci_dev)) { + part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(part); + } + } + break; + case SNR_HQM_SAD_ID: + case SNR_NIS_SAD_ID: + case SNR_QAT_SAD_ID: + JacobsvilleAccelerators(*sad_id_bus_pair, stack); + break; + default: + cerr << "Unknown SAD ID: " << sad_id << endl; + return false; + } + iio_on_socket.stacks.push_back(stack); + } + + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + + iios.push_back(iio_on_socket); + + return true; +} + +bool EagleStreamPlatformMapping::setChopValue() +{ + for (uint16_t b = 0; b < 256; b++) { + struct pci pci_dev(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION); + if (!(probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(SPR_PCU_CR3_DID))) { + continue; + } + + std::uint32_t capid4; + PciHandleType h(0, b, SPR_PCU_CR3_REG_DEVICE, SPR_PCU_CR3_REG_FUNCTION); + h.read32(SPR_CAPID4_OFFSET, &capid4); + if (capid4 == (std::numeric_limits::max)()) { + std::cerr << "Cannot read PCU RC3 register" << std::endl; + return false; + } + capid4 = SPR_CAPID4_GET_PHYSICAL_CHOP(capid4); + if (capid4 == kXccChop || capid4 == kMccChop) { + m_chop = capid4; + m_es_type = cpuId() == PCM::SPR ? (m_chop == kXccChop ? estype::esSprXcc : estype::esSprMcc) : estype::esEmrXcc; + } + else { + std::cerr << "Unknown chop value " << capid4 << std::endl; + return false; + } + return true; + } + std::cerr << "Cannot find PCU RC3 registers on the system. Device ID is " << std::hex << SPR_PCU_CR3_DID << std::dec << std::endl; + return false; +} + +bool EagleStreamPlatformMapping::getRootBuses(std::map> &root_buses) +{ + bool mapped = true; + for (uint32_t domain = 0; mapped; domain++) { + mapped = false; + for (uint16_t b = 0; b < 256; b++) { + for (uint8_t d = 0; d < 32; d++) { + for (uint8_t f = 0; f < 8; f++) { + struct pci pci_dev(domain, b, d, f); + if (!probe_pci(&pci_dev)) { + break; + } + if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) { + continue; + } + + std::uint32_t cpuBusValid; + std::vector cpuBusNo; + int package_id; + + if (get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id) == false) + { + return false; + } + + const auto& sad_to_pmu_id_mapping = es_sad_to_pmu_id_mapping.at(m_es_type); + for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) { + if (!((cpuBusValid >> cpuBusId) & 0x1)) + { + cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl; + continue; + } + if (sad_to_pmu_id_mapping.find(cpuBusId) == sad_to_pmu_id_mapping.end()) + { + cerr << "Cannot map CPU bus " << cpuBusId << " to IO PMU ID" << endl; + continue; + } + int pmuId = sad_to_pmu_id_mapping.at(cpuBusId); + int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff; + root_buses[package_id][pmuId] = bdf(domain, rootBus, 0, 0); + cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ") to IO PMU #" + << pmuId << " package " << package_id << endl; + mapped = true; + } + } + } + } + } + return !root_buses.empty(); +} + +bool EagleStreamPlatformMapping::eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + struct iio_stack stack; + stack.iio_unit_id = unit; + stack.stack_name = es_stack_names.at(m_es_type)[unit]; + stack.busno = address.busno; + stack.domain = address.domainno; + struct iio_bifurcated_part pch_part; + struct pci *pci = &pch_part.root_pci_dev; + auto dmi_part_id = SPR_DMI_PART_ID; + pch_part.part_id = dmi_part_id; + pci->bdf = address; + if (!probe_pci(pci)) { + cerr << "Failed to probe DMI Stack: address: " << std::setw(4) << std::setfill('0') << std::hex << address.domainno << + std::setw(2) << std::setfill('0') << ":" << address.busno << ":" << address.devno << + "." << address.funcno << std::dec << endl; + return false; + } + + /* Scan devices behind PCH port only */ + if (!iio_on_socket.socket_id) + probeDeviceRange(pch_part.child_pci_devs, pci->bdf.domainno, pci->secondary_bus_number, pci->subordinate_bus_number); + + pci->parts_no.push_back(dmi_part_id); + + stack.parts.push_back(pch_part); + iio_on_socket.stacks.push_back(stack); + return true; +} + +bool EagleStreamPlatformMapping::eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + /* + * Stacks that manage PCIe 4.0 (device 2,4,6,8) and 5.0 (device 1,3,5,7) Root Ports. + */ + struct iio_stack stack; + stack.domain = address.domainno; + stack.busno = address.busno; + stack.iio_unit_id = unit; + stack.stack_name = es_stack_names.at(m_es_type)[unit]; + for (int slot = 1; slot < 9; ++slot) + { + // Check if port is enabled + struct pci root_pci_dev; + root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0); + if (probe_pci(&root_pci_dev)) + { + struct iio_bifurcated_part part; + // Bifurcated Root Ports to channel mapping on SPR + part.part_id = slot - 1; + part.root_pci_dev = root_pci_dev; + for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) { + for (uint8_t d = 0; d < 32; ++d) { + for (uint8_t f = 0; f < 8; ++f) { + struct pci child_pci_dev(address.domainno, b, d, f); + if (probe_pci(&child_pci_dev)) { + child_pci_dev.parts_no.push_back(part.part_id); + part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(part); + } + } + iio_on_socket.stacks.push_back(stack); + return true; +} + +bool EagleStreamPlatformMapping::eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + struct iio_stack stack; + stack.iio_unit_id = unit; + stack.domain = address.domainno; + stack.busno = address.busno; + + // Channel mappings are checked on B0 stepping + auto rb = address.busno; + const std::vector acceleratorBuses{ rb, rb + 1, rb + 2, rb + 3 }; + stack.stack_name = es_stack_names.at(m_es_type)[unit]; + for (auto& b : acceleratorBuses) { + for (auto d = 0; d < 32; ++d) { + for (auto f = 0; f < 8; ++f) { + struct iio_bifurcated_part part; + struct pci pci_dev(address.domainno, b, d, f); + + if (probe_pci(&pci_dev)) { + if (pci_dev.isIntelDevice()) { + switch (pci_dev.device_id) { + case DSA_DID: + pci_dev.parts_no.push_back(0); + pci_dev.parts_no.push_back(1); + pci_dev.parts_no.push_back(2); + break; + case IAX_DID: + pci_dev.parts_no.push_back(0); + pci_dev.parts_no.push_back(1); + pci_dev.parts_no.push_back(2); + break; + case HQMV2_DID: + pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_HQM_PART_ID : SPR_MCC_HQM_PART_ID); + break; + case QATV2_DID: + pci_dev.parts_no.push_back(isXccPlatform() ? SPR_XCC_QAT_PART_ID : SPR_MCC_QAT_PART_ID); + break; + default: + continue; + } + part.child_pci_devs.push_back(pci_dev); + } + stack.parts.push_back(part); + } + } + } + } + + iio_on_socket.stacks.push_back(stack); + return true; +} + +bool EagleStreamPlatformMapping::isDmiStack(int unit) +{ + const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type); + + return stacks_enumeration[esDMI] == unit; +} + +bool EagleStreamPlatformMapping::isPcieStack(int unit) +{ + const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type); + + return stacks_enumeration[esPCIe0] == unit || stacks_enumeration[esPCIe1] == unit || + stacks_enumeration[esPCIe2] == unit || stacks_enumeration[esPCIe3] == unit || + stacks_enumeration[esPCIe4] == unit; +} + +bool EagleStreamPlatformMapping::isDinoStack(int unit) +{ + const auto& stacks_enumeration = es_stacks_enumeration.at(m_es_type); + + return stacks_enumeration[esDINO0] == unit || stacks_enumeration[esDINO1] == unit || + stacks_enumeration[esDINO2] == unit || stacks_enumeration[esDINO3] == unit; +} + +bool EagleStreamPlatformMapping::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + if (isDmiStack(unit)) { + return eagleStreamDmiStackProbe(unit, address, iio_on_socket); + } + else if (isPcieStack(unit)) { + return eagleStreamPciStackProbe(unit, address, iio_on_socket); + } + else if (isDinoStack(unit)) { + return eagleStreamAcceleratorStackProbe(unit, address, iio_on_socket); + } + + return false; +} + +bool EagleStreamPlatformMapping::pciTreeDiscover(std::vector& iios) +{ + if (!setChopValue()) return false; + + std::map> root_buses; + if (!getRootBuses(root_buses)) + { + return false; + } + + for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) { + auto rbs_on_socket = iter->second; + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = iter->first; + for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) { + if (!stackProbe(rb->first, rb->second, iio_on_socket)) { + return false; + } + } + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + iios.push_back(iio_on_socket); + } + + return true; +} + +bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) +{ + struct iio_stack stack; + stack.busno = root_bus; + stack.iio_unit_id = stack_pmon_id; + stack.stack_name = grr_iio_stack_names[stack_pmon_id]; + + struct iio_bifurcated_part pch_part; + pch_part.part_id = 7; + struct pci* pci_dev = &pch_part.root_pci_dev; + pci_dev->bdf.busno = root_bus; + + if (probe_pci(pci_dev)) { + probeDeviceRange(pch_part.child_pci_devs, pci_dev->bdf.domainno, pci_dev->secondary_bus_number, pci_dev->subordinate_bus_number); + stack.parts.push_back(pch_part); + iio_on_socket.stacks.push_back(stack); + return true; + } + + return false; +} + +bool LoganvillePlatform::loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) +{ + struct iio_stack stack; + stack.busno = root_bus; + stack.iio_unit_id = stack_pmon_id; + stack.stack_name = grr_iio_stack_names[stack_pmon_id]; + + struct iio_bifurcated_part dlb_part; + dlb_part.part_id = GRR_DLB_PART_ID; + + for (uint8_t bus = root_bus; bus < 255; bus++) { + struct pci pci_dev(bus, 0x00, 0x00); + if (probe_pci(&pci_dev) && pci_dev.isIntelDeviceById(HQMV25_DID)) { + dlb_part.root_pci_dev = pci_dev; + // Check Virtual RPs for DLB + for (uint8_t device = 0; device < 2; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev(bus, device, function); + if (probe_pci(&child_pci_dev)) { + dlb_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + stack.parts.push_back(dlb_part); + iio_on_socket.stacks.push_back(stack); + return true; + } + } + + return false; +} + +bool LoganvillePlatform::loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) +{ + struct iio_stack stack; + stack.busno = root_bus; + stack.iio_unit_id = stack_pmon_id; + stack.stack_name = grr_iio_stack_names[stack_pmon_id]; + + // Probe NIS + { + struct iio_bifurcated_part nis_part; + nis_part.part_id = GRR_NIS_PART_ID; + struct pci pci_dev(root_bus, 0x04, 0x00); + if (probe_pci(&pci_dev)) { + nis_part.root_pci_dev = pci_dev; + for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 2; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev(bus, device, function); + if (probe_pci(&child_pci_dev)) { + nis_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(nis_part); + } + } + + // Probe QAT + { + struct iio_bifurcated_part qat_part; + qat_part.part_id = GRR_QAT_PART_ID; + struct pci pci_dev(root_bus, 0x05, 0x00); + if (probe_pci(&pci_dev)) { + qat_part.root_pci_dev = pci_dev; + for (uint8_t bus = pci_dev.secondary_bus_number; bus <= pci_dev.subordinate_bus_number; bus++) { + for (uint8_t device = 0; device < 17; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_pci_dev(bus, device, function); + if (probe_pci(&child_pci_dev)) { + qat_part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(qat_part); + } + } + + iio_on_socket.stacks.push_back(stack); + return true; +} + +bool LoganvillePlatform::pciTreeDiscover(std::vector& iios) +{ + std::map sad_id_bus_map; + if (!getSadIdRootBusMap(0, sad_id_bus_map)) { + return false; + } + + if (sad_id_bus_map.size() != grr_sad_to_pmu_id_mapping.size()) { + cerr << "Found unexpected number of stacks: " << sad_id_bus_map.size() << ", expected: " << grr_sad_to_pmu_id_mapping.size() << endl; + return false; + } + + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = 0; + + for (auto sad_id_bus_pair = sad_id_bus_map.cbegin(); sad_id_bus_pair != sad_id_bus_map.cend(); ++sad_id_bus_pair) { + if (grr_sad_to_pmu_id_mapping.find(sad_id_bus_pair->first) == grr_sad_to_pmu_id_mapping.end()) { + cerr << "Cannot map SAD ID to PMON ID. Unknown ID: " << sad_id_bus_pair->first << endl; + return false; + } + int stack_pmon_id = grr_sad_to_pmu_id_mapping.at(sad_id_bus_pair->first); + int root_bus = sad_id_bus_pair->second; + switch (stack_pmon_id) { + case GRR_PCH_DSA_GEN4_PMON_ID: + if (!loganvillePchDsaPciStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { + return false; + } + break; + case GRR_DLB_PMON_ID: + if (!loganvilleDlbStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { + return false; + } + break; + case GRR_NIS_QAT_PMON_ID: + if (!loganvilleNacStackProbe(iio_on_socket, root_bus, stack_pmon_id)) { + return false; + } + break; + default: + return false; + } + } + + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + + iios.push_back(iio_on_socket); + + return true; +} + +bool Xeon6thNextGenPlatform::getRootBuses(std::map> &root_buses) +{ + bool mapped = true; + for (uint32_t domain = 0; mapped; domain++) { + mapped = false; + for (uint16_t b = 0; b < 256; b++) { + for (uint8_t d = 0; d < 32; d++) { + for (uint8_t f = 0; f < 8; f++) { + struct pci pci_dev(domain, b, d, f); + if (!probe_pci(&pci_dev)) { + break; + } + if (!pci_dev.isIntelDeviceById(SPR_MSM_DEV_ID)) { + continue; + } + + std::uint32_t cpuBusValid; + std::vector cpuBusNo; + int package_id; + + if (!get_cpu_bus(domain, b, d, f, cpuBusValid, cpuBusNo, package_id)) { + return false; + } + + for (int cpuBusId = 0; cpuBusId < SPR_MSM_CPUBUSNO_MAX; ++cpuBusId) { + if (!((cpuBusValid >> cpuBusId) & 0x1)) { + cout << "CPU bus " << cpuBusId << " is disabled on package " << package_id << endl; + continue; + } + int rootBus = (cpuBusNo[(int)(cpuBusId / 4)] >> ((cpuBusId % 4) * 8)) & 0xff; + root_buses[package_id][cpuBusId] = bdf(domain, rootBus, 0, 0); + cout << "Mapped CPU bus #" << cpuBusId << " (domain " << domain << " bus " << std::hex << rootBus << std::dec << ")" + << " package " << package_id << endl; + mapped = true; + } + } + } + } + } + return !root_buses.empty(); +} + +bool Xeon6thNextGenPlatform::pciTreeDiscover(std::vector& iios) +{ + std::map> root_buses; + if (!getRootBuses(root_buses)) + { + return false; + } + + for (auto iter = root_buses.cbegin(); iter != root_buses.cend(); ++iter) { + auto rbs_on_socket = iter->second; + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = iter->first; + for (auto rb = rbs_on_socket.cbegin(); rb != rbs_on_socket.cend(); ++rb) { + if (!stackProbe(rb->first, rb->second, iio_on_socket)) { + return false; + } + } + std::sort(iio_on_socket.stacks.begin(), iio_on_socket.stacks.end()); + iios.push_back(iio_on_socket); + } + + return true; +} + +bool BirchStreamPlatform::birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + /* + * All stacks manage PCIe 5.0 Root Ports. Bifurcated Root Ports A-H appear as devices 2-9. + */ + struct iio_stack stack; + stack.domain = address.domainno; + stack.busno = address.busno; + stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit); + stack.stack_name = srf_iio_stack_names[stack.iio_unit_id]; + for (int slot = 2; slot < 9; ++slot) + { + struct pci root_pci_dev; + root_pci_dev.bdf = bdf(address.domainno, address.busno, slot, 0x0); + if (probe_pci(&root_pci_dev)) + { + struct iio_bifurcated_part part; + part.part_id = slot - 2; + part.root_pci_dev = root_pci_dev; + for (uint8_t b = root_pci_dev.secondary_bus_number; b <= root_pci_dev.subordinate_bus_number; ++b) { + for (uint8_t d = 0; d < 32; ++d) { + for (uint8_t f = 0; f < 8; ++f) { + struct pci child_pci_dev(address.domainno, b, d, f); + if (probe_pci(&child_pci_dev)) { + child_pci_dev.parts_no.push_back(part.part_id); + part.child_pci_devs.push_back(child_pci_dev); + } + } + } + } + stack.parts.push_back(part); + } + } + iio_on_socket.stacks.push_back(stack); + return true; +} + +bool BirchStreamPlatform::birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + struct iio_stack stack; + stack.iio_unit_id = srf_sad_to_pmu_id_mapping.at(unit); + stack.domain = address.domainno; + stack.busno = address.busno; + stack.stack_name = srf_iio_stack_names[stack.iio_unit_id]; + + /* + * Instance of DSA(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 1, function 0 + * Instance of IAX(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (8, 12, 20, 16), device 2, function 0 + * Instance of QAT(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (9, 13, 21, 17), device 0, function 0 + * Instance of HQM(0, 1, 2, 3) appears as PCIe device with SAD Bus ID (10, 14, 22, 18), device 0, function 0 + */ + auto process_pci_dev = [](int domainno, int busno, int devno, int part_number, iio_bifurcated_part& part) + { + struct pci pci_dev(domainno, busno, devno, 0); + if (probe_pci(&pci_dev) && pci_dev.isIntelDevice()) { + part.part_id = part_number; + pci_dev.parts_no.push_back(part_number); + part.child_pci_devs.push_back(pci_dev); + return true; + } + return false; + }; + + auto add_pci_part = [&](int domainno, int busno, int devno, int part_number) { + struct iio_bifurcated_part part; + if (process_pci_dev(domainno, busno, devno, part_number, part)) { + stack.parts.push_back(part); + } + }; + + add_pci_part(address.domainno, address.busno, 1, SRF_DSA_IAX_PART_NUMBER); + add_pci_part(address.domainno, address.busno, 2, SRF_DSA_IAX_PART_NUMBER); + + add_pci_part(address.domainno, address.busno + 1, 0, SRF_QAT_PART_NUMBER); + + /* Bus number for HQM is higher on 3 than DSA bus number */ + add_pci_part(address.domainno, address.busno + 3, 0, SRF_HQM_PART_NUMBER); + + if (!stack.parts.empty()) { + iio_on_socket.stacks.push_back(stack); + } + + return true; +} + +bool BirchStreamPlatform::isPcieStack(int unit) +{ + return srf_pcie_stacks.find(unit) != srf_pcie_stacks.end(); +} + +/* + * HC is the name of DINO stacks as we had on SPR + */ +bool BirchStreamPlatform::isRootHcStack(int unit) +{ + return SRF_HC0_SAD_BUS_ID == unit || SRF_HC1_SAD_BUS_ID == unit || + SRF_HC2_SAD_BUS_ID == unit || SRF_HC3_SAD_BUS_ID == unit; +} + +bool BirchStreamPlatform::isPartHcStack(int unit) +{ + return isRootHcStack(unit - 1) || isRootHcStack(unit - 2); +} + +bool BirchStreamPlatform::isUboxStack(int unit) +{ + return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; +} + +bool BirchStreamPlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + if (isPcieStack(unit)) { + return birchStreamPciStackProbe(unit, address, iio_on_socket); + } + else if (isRootHcStack(unit)) { + return birchStreamAcceleratorStackProbe(unit, address, iio_on_socket); + } + else if (isPartHcStack(unit)) { + cout << "Found a part of HC stack. Stack ID - " << unit << " domain " << address.domainno + << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << ". Don't probe it again." << endl; + return true; + } + else if (isUboxStack(unit)) { + cout << "Found UBOX stack. Stack ID - " << unit << " domain " << address.domainno + << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl; + return true; + } + + cout << "Unknown stack ID " << unit << " domain " << address.domainno << " bus " << std::hex << std::setfill('0') << std::setw(2) << (int)address.busno << std::dec << endl; + + return false; +} + +const std::string generate_stack_str(const int unit) +{ + static const std::string stack_str = "Stack "; + std::stringstream ss; + ss << stack_str << std::setw(2) << unit; + return ss.str(); +} + +bool KasseyvillePlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) +{ + // Skip UBOX buses + if (isUboxStack(unit)) return true; + + // To suppress compilation warning + (void)address; + + struct iio_stack stack; + stack.iio_unit_id = unit; + stack.stack_name = generate_stack_str(unit); + iio_on_socket.stacks.push_back(stack); + return true; +} + +void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int domain, int secondary, int subordinate) +{ + for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) { + for (uint8_t device = 0; device < 32; device++) { + for (uint8_t function = 0; function < 8; function++) { + struct pci child_dev; + child_dev.bdf.domainno = domain; + child_dev.bdf.busno = bus; + child_dev.bdf.devno = device; + child_dev.bdf.funcno = function; + if (probe_pci(&child_dev)) { + if (secondary < child_dev.secondary_bus_number && subordinate < child_dev.subordinate_bus_number) { + probeDeviceRange(child_dev.child_pci_devs, domain, child_dev.secondary_bus_number, child_dev.subordinate_bus_number); + } + pci_devs.push_back(child_dev); + } + } + } + } +} + +std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count) +{ + switch (cpu_family_model) { + case PCM::SKX: + return std::unique_ptr{new PurleyPlatformMapping(cpu_family_model, sockets_count)}; + case PCM::ICX: + return std::unique_ptr{new WhitleyPlatformMapping(cpu_family_model, sockets_count)}; + case PCM::SNOWRIDGE: + return std::unique_ptr{new JacobsvillePlatformMapping(cpu_family_model, sockets_count)}; + case PCM::SPR: + case PCM::EMR: + return std::unique_ptr{new EagleStreamPlatformMapping(cpu_family_model, sockets_count)}; + case PCM::GRR: + return std::unique_ptr{new LoganvillePlatform(cpu_family_model, sockets_count)}; + case PCM::SRF: + case PCM::GNR: + return std::unique_ptr{new BirchStreamPlatform(cpu_family_model, sockets_count)}; + case PCM::GNR_D: + std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for Graniterapids-D is provided" << std::endl; + return std::unique_ptr{new KasseyvillePlatform(cpu_family_model, sockets_count)}; + default: + return nullptr; + } +} + +void initializeIOStacksStructure( std::vector& iios ) +{ + PCM * m = PCM::getInstance(); + auto mapping = IPlatformMapping::getPlatformMapping(m->getCPUFamilyModel(), m->getNumSockets()); + if (!mapping) { + cerr << "Failed to discover pci tree: unknown platform" << endl; + exit(EXIT_FAILURE); + } + + if (!mapping->pciTreeDiscover(iios)) { + exit(EXIT_FAILURE); + } +} \ No newline at end of file diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h new file mode 100644 index 00000000..ce4726b4 --- /dev/null +++ b/src/pcm-iio-topology.h @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2017-2025, Intel Corporation + +// written by Patrick Lu, +// Aaron Cruz +// Alexander Antonov +// and others +#pragma once + +#include "cpucounters.h" + +#ifdef _MSC_VER + #include + #include "windows/windriver.h" +#else + #include +#endif + +#include +#include +#include +#include +#include // std::length_error +#include +#include +#include +#include + +#ifdef _MSC_VER + #include "freegetopt/getopt.h" +#endif + +#include "lspci.h" +#include "utils.h" + +using namespace std; +using namespace pcm; + +#define QAT_DID 0x18DA +#define NIS_DID 0x18D1 +#define HQM_DID 0x270B + +#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT) +#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS) + +#define ROOT_BUSES_OFFSET 0xCC +#define ROOT_BUSES_OFFSET_2 0xD0 + +#define SKX_SOCKETID_UBOX_DID 0x2014 +#define SKX_UBOX_DEVICE_NUM 0x08 +#define SKX_UBOX_FUNCTION_NUM 0x02 +#define SKX_BUS_NUM_STRIDE 8 +//the below LNID and GID applies to Skylake Server +#define SKX_UNC_SOCKETID_UBOX_LNID_OFFSET 0xC0 +#define SKX_UNC_SOCKETID_UBOX_GID_OFFSET 0xD4 + +static const std::string iio_stack_names[6] = { + "IIO Stack 0 - CBDMA/DMI ", + "IIO Stack 1 - PCIe0 ", + "IIO Stack 2 - PCIe1 ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - MCP0 ", + "IIO Stack 5 - MCP1 " +}; + +static const std::string skx_iio_stack_names[6] = { + "IIO Stack 0 - CBDMA/DMI ", + "IIO Stack 1 - PCIe0 ", + "IIO Stack 2 - PCIe1 ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - MCP0 ", + "IIO Stack 5 - MCP1 " +}; + +static const std::string icx_iio_stack_names[6] = { + "IIO Stack 0 - PCIe0 ", + "IIO Stack 1 - PCIe1 ", + "IIO Stack 2 - MCP ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - PCIe3 ", + "IIO Stack 5 - CBDMA/DMI " +}; + +static const std::string icx_d_iio_stack_names[6] = { + "IIO Stack 0 - MCP ", + "IIO Stack 1 - PCIe0 ", + "IIO Stack 2 - CBDMA/DMI ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - PCIe3 ", + "IIO Stack 5 - PCIe1 " +}; + +static const std::string snr_iio_stack_names[5] = { + "IIO Stack 0 - QAT ", + "IIO Stack 1 - CBDMA/DMI ", + "IIO Stack 2 - NIS ", + "IIO Stack 3 - HQM ", + "IIO Stack 4 - PCIe " +}; + +#define ICX_CBDMA_DMI_SAD_ID 0 +#define ICX_MCP_SAD_ID 3 + +#define ICX_PCH_PART_ID 0 +#define ICX_CBDMA_PART_ID 3 + +#define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4 +#define SNR_ICX_MESH2IIO_MMAP_DID 0x09A2 + +#define ICX_VMD_PCI_DEVNO 0x00 +#define ICX_VMD_PCI_FUNCNO 0x05 + +static const std::map icx_sad_to_pmu_id_mapping = { + { ICX_CBDMA_DMI_SAD_ID, 5 }, + { 1, 0 }, + { 2, 1 }, + { ICX_MCP_SAD_ID, 2 }, + { 4, 3 }, + { 5, 4 } +}; + +static const std::map icx_d_sad_to_pmu_id_mapping = { + { ICX_CBDMA_DMI_SAD_ID, 2 }, + { 1, 5 }, + { 2, 1 }, + { ICX_MCP_SAD_ID, 0 }, + { 4, 3 }, + { 5, 4 } +}; + +#define SNR_ACCELERATOR_PART_ID 4 + +#define SNR_ROOT_PORT_A_DID 0x334A + +#define SNR_CBDMA_DMI_SAD_ID 0 +#define SNR_PCIE_GEN3_SAD_ID 1 +#define SNR_HQM_SAD_ID 2 +#define SNR_NIS_SAD_ID 3 +#define SNR_QAT_SAD_ID 4 + +static const std::map snr_sad_to_pmu_id_mapping = { + { SNR_CBDMA_DMI_SAD_ID, 1 }, + { SNR_PCIE_GEN3_SAD_ID, 4 }, + { SNR_HQM_SAD_ID , 3 }, + { SNR_NIS_SAD_ID , 2 }, + { SNR_QAT_SAD_ID , 0 } +}; + +#define HQMV2_DID 0x2710 // Hardware Queue Manager v2 +#define HQMV25_DID 0x2714 // Hardware Queue Manager v2.5 +#define DSA_DID 0x0b25 // Data Streaming Accelerator (DSA) +#define IAX_DID 0x0cfe // In-Memory Database Analytics Accelerator (IAX) +#define QATV2_DID 0x4940 // QuickAssist (CPM) v2 + +#define SPR_DMI_PART_ID 7 +#define SPR_XCC_HQM_PART_ID 5 +#define SPR_MCC_HQM_PART_ID 4 +#define SPR_XCC_QAT_PART_ID 4 +#define SPR_MCC_QAT_PART_ID 5 +#define SPR_SAD_CONTROL_CFG_OFFSET SNR_ICX_SAD_CONTROL_CFG_OFFSET + +#define SPR_PCU_CR3_DID 0x325b +#define SPR_PCU_CR3_REG_DEVICE 0x1e +#define SPR_PCU_CR3_REG_FUNCTION 0x03 +#define SPR_CAPID4_OFFSET 0x94 +#define SPR_CAPID4_GET_PHYSICAL_CHOP(capid4) ((capid4 >> 6) & 3) +#define SPR_PHYSICAL_CHOP_XCC 0b11 +#define SPR_PHYSICAL_CHOP_MCC 0b01 + +#define SPR_XCC_DMI_PMON_ID 1 +#define SPR_XCC_PCIE_GEN5_0_PMON_ID 2 +#define SPR_XCC_PCIE_GEN5_1_PMON_ID 4 +#define SPR_XCC_PCIE_GEN5_2_PMON_ID 6 +#define SPR_XCC_PCIE_GEN5_3_PMON_ID 7 +#define SPR_XCC_PCIE_GEN5_4_PMON_ID 9 +#define SPR_XCC_IDX0_PMON_ID 0 +#define SPR_XCC_IDX1_PMON_ID 3 +#define SPR_XCC_IDX2_PMON_ID 5 +#define SPR_XCC_IDX3_PMON_ID 8 + +const std::map spr_xcc_sad_to_pmu_id_mapping = { + { 0, SPR_XCC_DMI_PMON_ID }, + { 1, SPR_XCC_PCIE_GEN5_0_PMON_ID }, + { 2, SPR_XCC_PCIE_GEN5_1_PMON_ID }, + { 3, SPR_XCC_PCIE_GEN5_2_PMON_ID }, + { 4, SPR_XCC_PCIE_GEN5_3_PMON_ID }, + { 5, SPR_XCC_PCIE_GEN5_4_PMON_ID }, + { 8, SPR_XCC_IDX0_PMON_ID }, + { 9, SPR_XCC_IDX1_PMON_ID }, + { 10, SPR_XCC_IDX2_PMON_ID }, + { 11, SPR_XCC_IDX3_PMON_ID } +}; + +#define SPR_MCC_DMI_PMON_ID 10 +#define SPR_MCC_PCIE_GEN5_0_PMON_ID 0 // assumption +#define SPR_MCC_PCIE_GEN5_1_PMON_ID 1 +#define SPR_MCC_PCIE_GEN5_2_PMON_ID 2 +#define SPR_MCC_PCIE_GEN5_3_PMON_ID 4 // assumption +#define SPR_MCC_PCIE_GEN5_4_PMON_ID 5 +#define SPR_MCC_IDX0_PMON_ID 3 + +const std::map spr_mcc_sad_to_pmu_id_mapping = { + { 0, SPR_MCC_PCIE_GEN5_0_PMON_ID }, + { 1, SPR_MCC_PCIE_GEN5_1_PMON_ID }, + { 2, SPR_MCC_PCIE_GEN5_2_PMON_ID }, + { 3, SPR_MCC_DMI_PMON_ID }, + { 4, SPR_MCC_PCIE_GEN5_3_PMON_ID }, + { 5, SPR_MCC_PCIE_GEN5_4_PMON_ID }, + { 8, SPR_MCC_IDX0_PMON_ID }, +}; + +static const std::string spr_xcc_iio_stack_names[] = { + "IIO Stack 0 - IDX0 ", + "IIO Stack 1 - DMI ", + "IIO Stack 2 - PCIe0 ", + "IIO Stack 3 - IDX1 ", + "IIO Stack 4 - PCIe1 ", + "IIO Stack 5 - IDX2 ", + "IIO Stack 6 - PCIe2 ", + "IIO Stack 7 - PCIe3", + "IIO Stack 8 - IDX3 ", + "IIO Stack 9 - PCIe4", + "IIO Stack 10 - NONE ", + "IIO Stack 11 - NONE ", +}; + +/* + * SPR MCC has 7 I/O stacks but PMON block for DMI has ID number 10. + * And just to follow such enumeration keep Stack 10 for DMI. + */ +static const std::string spr_mcc_iio_stack_names[] = { + "IIO Stack 0 - PCIe0 ", + "IIO Stack 1 - PCIe1 ", + "IIO Stack 2 - PCIe2 ", + "IIO Stack 3 - IDX0 ", + "IIO Stack 4 - PCIe3 ", + "IIO Stack 5 - PCIe4 ", + "IIO Stack 6 - NONE ", + "IIO Stack 7 - NONE ", + "IIO Stack 8 - NONE ", + "IIO Stack 9 - NONE ", + "IIO Stack 10 - DMI ", +}; + +// MS2IOSF stack IDs in CHA notation +#define GRR_PCH_DSA_GEN4_SAD_ID 0 +#define GRR_DLB_SAD_ID 1 +#define GRR_NIS_QAT_SAD_ID 2 + +#define GRR_PCH_DSA_GEN4_PMON_ID 2 +#define GRR_DLB_PMON_ID 1 +#define GRR_NIS_QAT_PMON_ID 0 + +// Stack 0 contains PCH, DSA and CPU PCIe Gen4 Complex +const std::map grr_sad_to_pmu_id_mapping = { + { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID }, + { GRR_DLB_SAD_ID, GRR_DLB_PMON_ID }, + { GRR_NIS_QAT_SAD_ID, GRR_NIS_QAT_PMON_ID }, +}; + +#define GRR_DLB_PART_ID 0 +#define GRR_NIS_PART_ID 0 +#define GRR_QAT_PART_ID 1 + +static const std::string grr_iio_stack_names[3] = { + "IIO Stack 0 - NIS/QAT ", + "IIO Stack 1 - HQM ", + "IIO Stack 2 - PCH/DSA/PCIe " +}; + +#define EMR_DMI_PMON_ID 7 +#define EMR_PCIE_GEN5_0_PMON_ID 1 +#define EMR_PCIE_GEN5_1_PMON_ID 2 +#define EMR_PCIE_GEN5_2_PMON_ID 3 +#define EMR_PCIE_GEN5_3_PMON_ID 8 +#define EMR_PCIE_GEN5_4_PMON_ID 6 +#define EMR_IDX0_PMON_ID 0 +#define EMR_IDX1_PMON_ID 4 +#define EMR_IDX2_PMON_ID 5 +#define EMR_IDX3_PMON_ID 9 + +const std::map emr_sad_to_pmu_id_mapping = { + { 0, EMR_DMI_PMON_ID }, + { 1, EMR_PCIE_GEN5_0_PMON_ID }, + { 2, EMR_PCIE_GEN5_1_PMON_ID }, + { 3, EMR_PCIE_GEN5_2_PMON_ID }, + { 4, EMR_PCIE_GEN5_3_PMON_ID }, + { 5, EMR_PCIE_GEN5_4_PMON_ID }, + { 8, EMR_IDX0_PMON_ID }, + { 9, EMR_IDX1_PMON_ID }, + { 10, EMR_IDX2_PMON_ID }, + { 11, EMR_IDX3_PMON_ID } +}; + +static const std::string emr_iio_stack_names[] = { + "IIO Stack 0 - IDX0 ", + "IIO Stack 1 - PCIe3 ", + "IIO Stack 2 - PCIe0 ", + "IIO Stack 3 - IDX1 ", + "IIO Stack 4 - PCIe1 ", + "IIO Stack 5 - IDX2 ", + "IIO Stack 6 - PCIe2 ", + "IIO Stack 7 - DMI", + "IIO Stack 8 - IDX3 ", + "IIO Stack 9 - PCIe4", + "IIO Stack 10 - NONE ", + "IIO Stack 11 - NONE ", +}; + +enum EagleStreamPlatformStacks +{ + esDMI = 0, + esPCIe0, + esPCIe1, + esPCIe2, + esPCIe3, + esPCIe4, + esDINO0, + esDINO1, + esDINO2, + esDINO3, + esEndOfList +}; + +const std::vector spr_xcc_stacks_enumeration = { + /* esDMI */ SPR_XCC_DMI_PMON_ID, + /* esPCIe0 */ SPR_XCC_PCIE_GEN5_0_PMON_ID, + /* esPCIe1 */ SPR_XCC_PCIE_GEN5_1_PMON_ID, + /* esPCIe2 */ SPR_XCC_PCIE_GEN5_2_PMON_ID, + /* esPCIe3 */ SPR_XCC_PCIE_GEN5_3_PMON_ID, + /* esPCIe4 */ SPR_XCC_PCIE_GEN5_4_PMON_ID, + /* esDINO0 */ SPR_XCC_IDX0_PMON_ID, + /* esDINO1 */ SPR_XCC_IDX1_PMON_ID, + /* esDINO2 */ SPR_XCC_IDX2_PMON_ID, + /* esDINO3 */ SPR_XCC_IDX3_PMON_ID, +}; + +const std::vector spr_mcc_stacks_enumeration = { + /* esDMI */ SPR_MCC_DMI_PMON_ID, + /* esPCIe0 */ SPR_MCC_PCIE_GEN5_0_PMON_ID, + /* esPCIe1 */ SPR_MCC_PCIE_GEN5_1_PMON_ID, + /* esPCIe2 */ SPR_MCC_PCIE_GEN5_2_PMON_ID, + /* esPCIe3 */ SPR_MCC_PCIE_GEN5_3_PMON_ID, + /* esPCIe4 */ SPR_MCC_PCIE_GEN5_4_PMON_ID, + /* esDINO0 */ SPR_MCC_IDX0_PMON_ID, +}; + +const std::vector emr_stacks_enumeration = { + /* esDMI */ EMR_DMI_PMON_ID, + /* esPCIe0 */ EMR_PCIE_GEN5_0_PMON_ID, + /* esPCIe1 */ EMR_PCIE_GEN5_1_PMON_ID, + /* esPCIe2 */ EMR_PCIE_GEN5_2_PMON_ID, + /* esPCIe3 */ EMR_PCIE_GEN5_3_PMON_ID, + /* esPCIe4 */ EMR_PCIE_GEN5_4_PMON_ID, + /* esDINO0 */ EMR_IDX0_PMON_ID, + /* esDINO1 */ EMR_IDX1_PMON_ID, + /* esDINO2 */ EMR_IDX2_PMON_ID, + /* esDINO3 */ EMR_IDX3_PMON_ID, +}; + +enum class EagleStreamSupportedTypes +{ + esInvalid = -1, + esSprXcc, + esSprMcc, + esEmrXcc +}; + +typedef EagleStreamSupportedTypes estype; + +const std::map> es_stacks_enumeration = { + {estype::esSprXcc, spr_xcc_stacks_enumeration}, + {estype::esSprMcc, spr_mcc_stacks_enumeration}, + {estype::esEmrXcc, emr_stacks_enumeration }, +}; + +const std::map es_stack_names = { + {estype::esSprXcc, spr_xcc_iio_stack_names}, + {estype::esSprMcc, spr_mcc_iio_stack_names}, + {estype::esEmrXcc, emr_iio_stack_names }, +}; + +const std::map> es_sad_to_pmu_id_mapping = { + {estype::esSprXcc, spr_xcc_sad_to_pmu_id_mapping}, + {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping}, + {estype::esEmrXcc, emr_sad_to_pmu_id_mapping }, +}; + +#define SRF_PE0_PMON_ID 3 +#define SRF_PE1_PMON_ID 4 +#define SRF_PE2_PMON_ID 2 +#define SRF_PE3_PMON_ID 5 +/* + * There are platform configuration when FlexUPI stacks (stacks 5 and 6) are enabled as + * PCIe stack and PCIe ports are disabled (ports 2 and 3) and vice sersa. See details here: + * In these cases the PMON IDs are different. + * So, defines with _FLEX_ are applicable for cases when FlexUPI stacks + * are working as PCIe ports. + */ +#define SRF_PE4_PMON_ID 11 +#define SRF_FLEX_PE4_PMON_ID 13 +#define SRF_PE5_PMON_ID 12 +#define SRF_FLEX_PE5_PMON_ID 10 + +#define SRF_PE6_PMON_ID 0 +#define SRF_PE7_PMON_ID 7 +#define SRF_PE8_PMON_ID 8 +#define SRF_HC0_PMON_ID 1 +#define SRF_HC1_PMON_ID 6 +#define SRF_HC2_PMON_ID 9 +#define SRF_HC3_PMON_ID 14 + +#define SRF_PE0_SAD_BUS_ID 2 +#define SRF_PE1_SAD_BUS_ID 3 +#define SRF_PE2_SAD_BUS_ID 1 +#define SRF_PE3_SAD_BUS_ID 4 +#define SRF_PE4_SAD_BUS_ID 29 +#define SRF_FLEX_PE4_SAD_BUS_ID SRF_PE4_SAD_BUS_ID +#define SRF_PE5_SAD_BUS_ID 26 +#define SRF_FLEX_PE5_SAD_BUS_ID SRF_PE5_SAD_BUS_ID +#define SRF_PE6_SAD_BUS_ID 0 // UPI0 +#define SRF_PE7_SAD_BUS_ID 5 // UPI1 +#define SRF_PE8_SAD_BUS_ID 28 // UPI2 +#define SRF_UBOXA_SAD_BUS_ID 30 +#define SRF_UBOXB_SAD_BUS_ID 31 + +const std::set srf_pcie_stacks({ + SRF_PE0_SAD_BUS_ID, + SRF_PE1_SAD_BUS_ID, + SRF_PE2_SAD_BUS_ID, + SRF_PE3_SAD_BUS_ID, + SRF_PE4_SAD_BUS_ID, + SRF_FLEX_PE4_SAD_BUS_ID, + SRF_PE5_SAD_BUS_ID, + SRF_FLEX_PE5_SAD_BUS_ID, + SRF_PE6_SAD_BUS_ID, + SRF_PE7_SAD_BUS_ID, + SRF_PE8_SAD_BUS_ID, +}); + +#define SRF_HC0_SAD_BUS_ID 8 +#define SRF_HC1_SAD_BUS_ID 12 +#define SRF_HC2_SAD_BUS_ID 20 +#define SRF_HC3_SAD_BUS_ID 16 + +const std::map srf_sad_to_pmu_id_mapping = { + { SRF_PE0_SAD_BUS_ID, SRF_PE0_PMON_ID }, + { SRF_PE1_SAD_BUS_ID, SRF_PE1_PMON_ID }, + { SRF_PE2_SAD_BUS_ID, SRF_PE2_PMON_ID }, + { SRF_PE3_SAD_BUS_ID, SRF_PE3_PMON_ID }, + { SRF_PE4_SAD_BUS_ID, SRF_PE4_PMON_ID }, + { SRF_FLEX_PE4_SAD_BUS_ID, SRF_FLEX_PE4_PMON_ID }, + { SRF_PE5_SAD_BUS_ID, SRF_PE5_PMON_ID }, + { SRF_FLEX_PE5_SAD_BUS_ID, SRF_FLEX_PE5_PMON_ID }, + { SRF_PE6_SAD_BUS_ID, SRF_PE6_PMON_ID }, + { SRF_PE7_SAD_BUS_ID, SRF_PE7_PMON_ID }, + { SRF_PE8_SAD_BUS_ID, SRF_PE8_PMON_ID }, + { SRF_HC0_SAD_BUS_ID, SRF_HC0_PMON_ID }, + { SRF_HC1_SAD_BUS_ID, SRF_HC1_PMON_ID }, + { SRF_HC2_SAD_BUS_ID, SRF_HC2_PMON_ID }, + { SRF_HC3_SAD_BUS_ID, SRF_HC3_PMON_ID }, +}; + +#define SRF_DSA_IAX_PART_NUMBER 0 +#define SRF_HQM_PART_NUMBER 5 +#define SRF_QAT_PART_NUMBER 4 + +static const std::string srf_iio_stack_names[] = { + "IIO Stack 0 - PCIe6 ", // SRF_PE6_PMON_ID 0 + "IIO Stack 1 - HCx0 ", // SRF_HC0_PMON_ID 1 + "IIO Stack 2 - PCIe2 ", // SRF_PE2_PMON_ID 2 + "IIO Stack 3 - PCIe0 ", // SRF_PE0_PMON_ID 3 + "IIO Stack 4 - PCIe1 ", // SRF_PE1_PMON_ID 4 + "IIO Stack 5 - PCIe3 ", // SRF_PE3_PMON_ID 5 + "IIO Stack 6 - HCx1 ", // SRF_HC1_PMON_ID 6 + "IIO Stack 7 - PCIe7 ", // SRF_PE7_PMON_ID 7 + "IIO Stack 8 - PCIe8 ", // SRF_PE8_PMON_ID 8 + "IIO Stack 9 - HCx3 ", // SRF_HC3_PMON_ID 9 + "IIO Stack 10 - Flex PCIe5", // SRF_FLEX_PE5_PMON_ID 10 + "IIO Stack 11 - PCIe4 ", // SRF_PE4_PMON_ID 11 + "IIO Stack 12 - PCIe5 ", // SRF_PE5_PMON_ID 12 + "IIO Stack 13 - Flex PCIe4", // SRF_FLEX_PE4_PMON_ID 13 + "IIO Stack 14 - HCx2 ", // SRF_HC2_PMON_ID 14 +}; + +class IPlatformMapping { +private: + uint32_t m_sockets; + uint32_t m_model; +protected: + void probeDeviceRange(std::vector &child_pci_devs, int domain, int secondary, int subordinate); +public: + IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} + virtual ~IPlatformMapping() {}; + static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count); + virtual bool pciTreeDiscover(std::vector& iios) = 0; + + uint32_t socketsCount() const { return m_sockets; } + uint32_t cpuId() const { return m_model; } +}; + +// Mapping for SkyLake Server. +class PurleyPlatformMapping: public IPlatformMapping { +private: + void getUboxBusNumbers(std::vector& ubox); +public: + PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + ~PurleyPlatformMapping() = default; + bool pciTreeDiscover(std::vector& iios) override; +}; + +class IPlatformMapping10Nm: public IPlatformMapping { +private: +public: + IPlatformMapping10Nm(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + ~IPlatformMapping10Nm() = default; + bool getSadIdRootBusMap(uint32_t socket_id, std::map& sad_id_bus_map); +}; + +// Mapping for IceLake Server. +class WhitleyPlatformMapping: public IPlatformMapping10Nm { +private: + const bool icx_d; + const std::map& sad_to_pmu_id_mapping; + const std::string * iio_stack_names; +public: + WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count), + icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), + sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping), + iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names) + { + } + ~WhitleyPlatformMapping() = default; + bool pciTreeDiscover(std::vector& iios) override; +}; + +// Mapping for Snowridge. +class JacobsvillePlatformMapping: public IPlatformMapping10Nm { +private: +public: + JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} + ~JacobsvillePlatformMapping() = default; + bool pciTreeDiscover(std::vector& iios) override; + bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); +}; + +class EagleStreamPlatformMapping: public IPlatformMapping +{ +private: + bool getRootBuses(std::map> &root_buses); + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool isDmiStack(int unit); + bool isPcieStack(int unit); + bool isDinoStack(int unit); + std::uint32_t m_chop; + EagleStreamSupportedTypes m_es_type; +public: + EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {} + ~EagleStreamPlatformMapping() = default; + bool setChopValue(); + bool isXccPlatform() const { return m_chop == kXccChop; } + + const std::uint32_t kXccChop = 0b11; + const std::uint32_t kMccChop = 0b01; + + bool pciTreeDiscover(std::vector& iios) override; +}; + +class LoganvillePlatform: public IPlatformMapping10Nm { +private: + bool loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); + bool loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); + bool loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); +public: + LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} + ~LoganvillePlatform() = default; + bool pciTreeDiscover(std::vector& iios) override; +}; + +class Xeon6thNextGenPlatform: public IPlatformMapping { +private: + bool getRootBuses(std::map> &root_buses); +protected: + virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; +public: + Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + virtual ~Xeon6thNextGenPlatform() = default; + + virtual bool pciTreeDiscover(std::vector& iios) override; +}; + +class BirchStreamPlatform: public Xeon6thNextGenPlatform { +private: + bool isPcieStack(int unit); + bool isRootHcStack(int unit); + bool isPartHcStack(int unit); + bool isUboxStack(int unit); + + bool birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); +protected: + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; +public: + BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} + ~BirchStreamPlatform() = default; +}; + +class KasseyvillePlatform: public Xeon6thNextGenPlatform { +private: + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool isUboxStack(int unit) + { + return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; + } +public: + KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} + ~KasseyvillePlatform() = default; +}; + +void initializeIOStacksStructure( std::vector& iios ); \ No newline at end of file diff --git a/src/pcm-iio.cpp b/src/pcm-iio.cpp index 7a044d7c..859d3f43 100644 --- a/src/pcm-iio.cpp +++ b/src/pcm-iio.cpp @@ -1,8 +1,9 @@ // SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2017-2022, Intel Corporation +// Copyright (c) 2017-2025, Intel Corporation // written by Patrick Lu, -// Aaron Cruz +// Aaron Cruz, +// Alexander Antonov // and others #include "pcm-iio-pmu.h" diff --git a/tests/utests/CMakeLists.txt b/tests/utests/CMakeLists.txt index d789d0ba..a0ba54a3 100644 --- a/tests/utests/CMakeLists.txt +++ b/tests/utests/CMakeLists.txt @@ -15,7 +15,7 @@ if(APPLE) endif() file(GLOB LSPCI_TEST_FILES lspci-utest.cpp ${CMAKE_SOURCE_DIR}/src/lspci.cpp) -file(GLOB PCM_IIO_TEST_FILES pcm-iio-utest.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-pmu.cpp) +file(GLOB PCM_IIO_TEST_FILES pcm-iio-utest.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-pmu.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-topology.cpp) if(APPLE) set(LIBS PcmMsr Threads::Threads PCM_STATIC) From 1dc9c8f194e4a2c75b3547b91775fabfedd9e434 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 04:24:25 -0700 Subject: [PATCH 24/54] Cleanup in pcm-iio-topology Regroup the code to avoid creation maps etc by default and decrease memory consumption --- src/pcm-iio-pmu.cpp | 1 + src/pcm-iio-pmu.h | 3 +- src/pcm-iio-topology.cpp | 563 ++++++++++++++++++++++++++++++++++++++ src/pcm-iio-topology.h | 577 --------------------------------------- 4 files changed, 565 insertions(+), 579 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index ddfcf745..f459d1ab 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -5,6 +5,7 @@ // Aaron Cruz // Alexander Antonov // and others +#include #include "pcm-iio-pmu.h" #include "pcm-iio-topology.h" diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index ab88a17b..31a4f029 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -7,8 +7,6 @@ // and others #pragma once -#include "cpucounters.h" - #ifdef _MSC_VER #include #include "windows/windriver.h" @@ -26,6 +24,7 @@ #include "lspci.h" #include "utils.h" +#include "cpucounters.h" using namespace std; using namespace pcm; diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index d3cf19dd..8a3dee14 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -5,9 +5,184 @@ // Aaron Cruz // Alexander Antonov // and others +#include +#include +#include +#include +#include #include "pcm-iio-topology.h" +#define QAT_DID 0x18DA +#define NIS_DID 0x18D1 +#define HQM_DID 0x270B + +#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT) +#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS) + +#define ROOT_BUSES_OFFSET 0xCC +#define ROOT_BUSES_OFFSET_2 0xD0 + +#define SKX_SOCKETID_UBOX_DID 0x2014 +#define SKX_UBOX_DEVICE_NUM 0x08 +#define SKX_UBOX_FUNCTION_NUM 0x02 +#define SKX_BUS_NUM_STRIDE 8 +//the below LNID and GID applies to Skylake Server +#define SKX_UNC_SOCKETID_UBOX_LNID_OFFSET 0xC0 +#define SKX_UNC_SOCKETID_UBOX_GID_OFFSET 0xD4 + +#define ICX_CBDMA_DMI_SAD_ID 0 +#define ICX_MCP_SAD_ID 3 + +#define ICX_PCH_PART_ID 0 +#define ICX_CBDMA_PART_ID 3 + +#define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4 +#define SNR_ICX_MESH2IIO_MMAP_DID 0x09A2 + +#define ICX_VMD_PCI_DEVNO 0x00 +#define ICX_VMD_PCI_FUNCNO 0x05 + +#define SNR_ACCELERATOR_PART_ID 4 + +#define SNR_ROOT_PORT_A_DID 0x334A + +#define SNR_CBDMA_DMI_SAD_ID 0 +#define SNR_PCIE_GEN3_SAD_ID 1 +#define SNR_HQM_SAD_ID 2 +#define SNR_NIS_SAD_ID 3 +#define SNR_QAT_SAD_ID 4 + +#define HQMV2_DID 0x2710 // Hardware Queue Manager v2 +#define HQMV25_DID 0x2714 // Hardware Queue Manager v2.5 +#define DSA_DID 0x0b25 // Data Streaming Accelerator (DSA) +#define IAX_DID 0x0cfe // In-Memory Database Analytics Accelerator (IAX) +#define QATV2_DID 0x4940 // QuickAssist (CPM) v2 + +#define SPR_DMI_PART_ID 7 +#define SPR_XCC_HQM_PART_ID 5 +#define SPR_MCC_HQM_PART_ID 4 +#define SPR_XCC_QAT_PART_ID 4 +#define SPR_MCC_QAT_PART_ID 5 +#define SPR_SAD_CONTROL_CFG_OFFSET SNR_ICX_SAD_CONTROL_CFG_OFFSET + +#define SPR_PCU_CR3_DID 0x325b +#define SPR_PCU_CR3_REG_DEVICE 0x1e +#define SPR_PCU_CR3_REG_FUNCTION 0x03 +#define SPR_CAPID4_OFFSET 0x94 +#define SPR_CAPID4_GET_PHYSICAL_CHOP(capid4) ((capid4 >> 6) & 3) +#define SPR_PHYSICAL_CHOP_XCC 0b11 +#define SPR_PHYSICAL_CHOP_MCC 0b01 + +#define SPR_XCC_DMI_PMON_ID 1 +#define SPR_XCC_PCIE_GEN5_0_PMON_ID 2 +#define SPR_XCC_PCIE_GEN5_1_PMON_ID 4 +#define SPR_XCC_PCIE_GEN5_2_PMON_ID 6 +#define SPR_XCC_PCIE_GEN5_3_PMON_ID 7 +#define SPR_XCC_PCIE_GEN5_4_PMON_ID 9 +#define SPR_XCC_IDX0_PMON_ID 0 +#define SPR_XCC_IDX1_PMON_ID 3 +#define SPR_XCC_IDX2_PMON_ID 5 +#define SPR_XCC_IDX3_PMON_ID 8 + +#define SPR_MCC_DMI_PMON_ID 10 +#define SPR_MCC_PCIE_GEN5_0_PMON_ID 0 // assumption +#define SPR_MCC_PCIE_GEN5_1_PMON_ID 1 +#define SPR_MCC_PCIE_GEN5_2_PMON_ID 2 +#define SPR_MCC_PCIE_GEN5_3_PMON_ID 4 // assumption +#define SPR_MCC_PCIE_GEN5_4_PMON_ID 5 +#define SPR_MCC_IDX0_PMON_ID 3 + +// MS2IOSF stack IDs in CHA notation +#define GRR_PCH_DSA_GEN4_SAD_ID 0 +#define GRR_DLB_SAD_ID 1 +#define GRR_NIS_QAT_SAD_ID 2 + +#define GRR_PCH_DSA_GEN4_PMON_ID 2 +#define GRR_DLB_PMON_ID 1 +#define GRR_NIS_QAT_PMON_ID 0 + +#define GRR_DLB_PART_ID 0 +#define GRR_NIS_PART_ID 0 +#define GRR_QAT_PART_ID 1 + +#define EMR_DMI_PMON_ID 7 +#define EMR_PCIE_GEN5_0_PMON_ID 1 +#define EMR_PCIE_GEN5_1_PMON_ID 2 +#define EMR_PCIE_GEN5_2_PMON_ID 3 +#define EMR_PCIE_GEN5_3_PMON_ID 8 +#define EMR_PCIE_GEN5_4_PMON_ID 6 +#define EMR_IDX0_PMON_ID 0 +#define EMR_IDX1_PMON_ID 4 +#define EMR_IDX2_PMON_ID 5 +#define EMR_IDX3_PMON_ID 9 + +#define SRF_PE0_PMON_ID 3 +#define SRF_PE1_PMON_ID 4 +#define SRF_PE2_PMON_ID 2 +#define SRF_PE3_PMON_ID 5 +/* + * There are platform configuration when FlexUPI stacks (stacks 5 and 6) are enabled as + * PCIe stack and PCIe ports are disabled (ports 2 and 3) and vice sersa. See details here: + * In these cases the PMON IDs are different. + * So, defines with _FLEX_ are applicable for cases when FlexUPI stacks + * are working as PCIe ports. + */ +#define SRF_PE4_PMON_ID 11 +#define SRF_FLEX_PE4_PMON_ID 13 +#define SRF_PE5_PMON_ID 12 +#define SRF_FLEX_PE5_PMON_ID 10 + +#define SRF_PE6_PMON_ID 0 +#define SRF_PE7_PMON_ID 7 +#define SRF_PE8_PMON_ID 8 +#define SRF_HC0_PMON_ID 1 +#define SRF_HC1_PMON_ID 6 +#define SRF_HC2_PMON_ID 9 +#define SRF_HC3_PMON_ID 14 + +#define SRF_PE0_SAD_BUS_ID 2 +#define SRF_PE1_SAD_BUS_ID 3 +#define SRF_PE2_SAD_BUS_ID 1 +#define SRF_PE3_SAD_BUS_ID 4 +#define SRF_PE4_SAD_BUS_ID 29 +#define SRF_FLEX_PE4_SAD_BUS_ID SRF_PE4_SAD_BUS_ID +#define SRF_PE5_SAD_BUS_ID 26 +#define SRF_FLEX_PE5_SAD_BUS_ID SRF_PE5_SAD_BUS_ID +#define SRF_PE6_SAD_BUS_ID 0 // UPI0 +#define SRF_PE7_SAD_BUS_ID 5 // UPI1 +#define SRF_PE8_SAD_BUS_ID 28 // UPI2 +#define SRF_UBOXA_SAD_BUS_ID 30 +#define SRF_UBOXB_SAD_BUS_ID 31 + +#define SRF_HC0_SAD_BUS_ID 8 +#define SRF_HC1_SAD_BUS_ID 12 +#define SRF_HC2_SAD_BUS_ID 20 +#define SRF_HC3_SAD_BUS_ID 16 + +#define SRF_DSA_IAX_PART_NUMBER 0 +#define SRF_HQM_PART_NUMBER 5 +#define SRF_QAT_PART_NUMBER 4 + +// Mapping for SkyLake Server. +class PurleyPlatformMapping: public IPlatformMapping { +private: + void getUboxBusNumbers(std::vector& ubox); + + const std::string skx_iio_stack_names[6] = { + "IIO Stack 0 - CBDMA/DMI ", + "IIO Stack 1 - PCIe0 ", + "IIO Stack 2 - PCIe1 ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - MCP0 ", + "IIO Stack 5 - MCP1 " + }; +public: + PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + ~PurleyPlatformMapping() = default; + bool pciTreeDiscover(std::vector& iios) override; +}; + void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) { for (uint16_t bus = 0; bus < 256; bus++) { @@ -90,6 +265,14 @@ bool PurleyPlatformMapping::pciTreeDiscover(std::vector& sad_id_bus_map); +}; + bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map& sad_id_bus_map) { for (uint16_t bus = 0; bus < 256; bus++) { @@ -126,6 +309,59 @@ bool IPlatformMapping10Nm::getSadIdRootBusMap(uint32_t socket_id, std::map& sad_to_pmu_id_mapping; + const std::string * iio_stack_names; + + const std::string icx_iio_stack_names[6] = { + "IIO Stack 0 - PCIe0 ", + "IIO Stack 1 - PCIe1 ", + "IIO Stack 2 - MCP ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - PCIe3 ", + "IIO Stack 5 - CBDMA/DMI " + }; + + const std::string icx_d_iio_stack_names[6] = { + "IIO Stack 0 - MCP ", + "IIO Stack 1 - PCIe0 ", + "IIO Stack 2 - CBDMA/DMI ", + "IIO Stack 3 - PCIe2 ", + "IIO Stack 4 - PCIe3 ", + "IIO Stack 5 - PCIe1 " + }; + + const std::map icx_sad_to_pmu_id_mapping = { + { ICX_CBDMA_DMI_SAD_ID, 5 }, + { 1, 0 }, + { 2, 1 }, + { ICX_MCP_SAD_ID, 2 }, + { 4, 3 }, + { 5, 4 } + }; + + const std::map icx_d_sad_to_pmu_id_mapping = { + { ICX_CBDMA_DMI_SAD_ID, 2 }, + { 1, 5 }, + { 2, 1 }, + { ICX_MCP_SAD_ID, 0 }, + { 4, 3 }, + { 5, 4 } + }; +public: + WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count), + icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), + sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping), + iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names) + { + } + ~WhitleyPlatformMapping() = default; + bool pciTreeDiscover(std::vector& iios) override; +}; + bool WhitleyPlatformMapping::pciTreeDiscover(std::vector& iios) { for (uint32_t socket = 0; socket < socketsCount(); socket++) { @@ -242,6 +478,31 @@ bool WhitleyPlatformMapping::pciTreeDiscover(std::vector snr_sad_to_pmu_id_mapping = { + { SNR_CBDMA_DMI_SAD_ID, 1 }, + { SNR_PCIE_GEN3_SAD_ID, 4 }, + { SNR_HQM_SAD_ID , 3 }, + { SNR_NIS_SAD_ID , 2 }, + { SNR_QAT_SAD_ID , 0 } + }; + + const std::string snr_iio_stack_names[5] = { + "IIO Stack 0 - QAT ", + "IIO Stack 1 - CBDMA/DMI ", + "IIO Stack 2 - NIS ", + "IIO Stack 3 - HQM ", + "IIO Stack 4 - PCIe " + }; +public: + JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} + ~JacobsvillePlatformMapping() = default; + bool pciTreeDiscover(std::vector& iios) override; + bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); +}; + bool JacobsvillePlatformMapping::JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack) { uint16_t expected_dev_id; @@ -400,6 +661,194 @@ bool JacobsvillePlatformMapping::pciTreeDiscover(std::vector> &root_buses); + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool isDmiStack(int unit); + bool isPcieStack(int unit); + bool isDinoStack(int unit); + std::uint32_t m_chop; + + enum class EagleStreamSupportedTypes + { + esInvalid = -1, + esSprXcc, + esSprMcc, + esEmrXcc + }; + + typedef EagleStreamSupportedTypes estype; + EagleStreamSupportedTypes m_es_type; + + const std::map spr_xcc_sad_to_pmu_id_mapping = { + { 0, SPR_XCC_DMI_PMON_ID }, + { 1, SPR_XCC_PCIE_GEN5_0_PMON_ID }, + { 2, SPR_XCC_PCIE_GEN5_1_PMON_ID }, + { 3, SPR_XCC_PCIE_GEN5_2_PMON_ID }, + { 4, SPR_XCC_PCIE_GEN5_3_PMON_ID }, + { 5, SPR_XCC_PCIE_GEN5_4_PMON_ID }, + { 8, SPR_XCC_IDX0_PMON_ID }, + { 9, SPR_XCC_IDX1_PMON_ID }, + { 10, SPR_XCC_IDX2_PMON_ID }, + { 11, SPR_XCC_IDX3_PMON_ID } + }; + + const std::map spr_mcc_sad_to_pmu_id_mapping = { + { 0, SPR_MCC_PCIE_GEN5_0_PMON_ID }, + { 1, SPR_MCC_PCIE_GEN5_1_PMON_ID }, + { 2, SPR_MCC_PCIE_GEN5_2_PMON_ID }, + { 3, SPR_MCC_DMI_PMON_ID }, + { 4, SPR_MCC_PCIE_GEN5_3_PMON_ID }, + { 5, SPR_MCC_PCIE_GEN5_4_PMON_ID }, + { 8, SPR_MCC_IDX0_PMON_ID }, + }; + + const std::string spr_xcc_iio_stack_names[12] = { + "IIO Stack 0 - IDX0 ", + "IIO Stack 1 - DMI ", + "IIO Stack 2 - PCIe0 ", + "IIO Stack 3 - IDX1 ", + "IIO Stack 4 - PCIe1 ", + "IIO Stack 5 - IDX2 ", + "IIO Stack 6 - PCIe2 ", + "IIO Stack 7 - PCIe3", + "IIO Stack 8 - IDX3 ", + "IIO Stack 9 - PCIe4", + "IIO Stack 10 - NONE ", + "IIO Stack 11 - NONE ", + }; + + /* + * SPR MCC has 7 I/O stacks but PMON block for DMI has ID number 10. + * And just to follow such enumeration keep Stack 10 for DMI. + */ + const std::string spr_mcc_iio_stack_names[11] = { + "IIO Stack 0 - PCIe0 ", + "IIO Stack 1 - PCIe1 ", + "IIO Stack 2 - PCIe2 ", + "IIO Stack 3 - IDX0 ", + "IIO Stack 4 - PCIe3 ", + "IIO Stack 5 - PCIe4 ", + "IIO Stack 6 - NONE ", + "IIO Stack 7 - NONE ", + "IIO Stack 8 - NONE ", + "IIO Stack 9 - NONE ", + "IIO Stack 10 - DMI ", + }; + + const std::map emr_sad_to_pmu_id_mapping = { + { 0, EMR_DMI_PMON_ID }, + { 1, EMR_PCIE_GEN5_0_PMON_ID }, + { 2, EMR_PCIE_GEN5_1_PMON_ID }, + { 3, EMR_PCIE_GEN5_2_PMON_ID }, + { 4, EMR_PCIE_GEN5_3_PMON_ID }, + { 5, EMR_PCIE_GEN5_4_PMON_ID }, + { 8, EMR_IDX0_PMON_ID }, + { 9, EMR_IDX1_PMON_ID }, + { 10, EMR_IDX2_PMON_ID }, + { 11, EMR_IDX3_PMON_ID } + }; + + const std::string emr_iio_stack_names[12] = { + "IIO Stack 0 - IDX0 ", + "IIO Stack 1 - PCIe3 ", + "IIO Stack 2 - PCIe0 ", + "IIO Stack 3 - IDX1 ", + "IIO Stack 4 - PCIe1 ", + "IIO Stack 5 - IDX2 ", + "IIO Stack 6 - PCIe2 ", + "IIO Stack 7 - DMI", + "IIO Stack 8 - IDX3 ", + "IIO Stack 9 - PCIe4", + "IIO Stack 10 - NONE ", + "IIO Stack 11 - NONE ", + }; + + enum EagleStreamPlatformStacks + { + esDMI = 0, + esPCIe0, + esPCIe1, + esPCIe2, + esPCIe3, + esPCIe4, + esDINO0, + esDINO1, + esDINO2, + esDINO3, + esEndOfList + }; + + const std::vector spr_xcc_stacks_enumeration = { + /* esDMI */ SPR_XCC_DMI_PMON_ID, + /* esPCIe0 */ SPR_XCC_PCIE_GEN5_0_PMON_ID, + /* esPCIe1 */ SPR_XCC_PCIE_GEN5_1_PMON_ID, + /* esPCIe2 */ SPR_XCC_PCIE_GEN5_2_PMON_ID, + /* esPCIe3 */ SPR_XCC_PCIE_GEN5_3_PMON_ID, + /* esPCIe4 */ SPR_XCC_PCIE_GEN5_4_PMON_ID, + /* esDINO0 */ SPR_XCC_IDX0_PMON_ID, + /* esDINO1 */ SPR_XCC_IDX1_PMON_ID, + /* esDINO2 */ SPR_XCC_IDX2_PMON_ID, + /* esDINO3 */ SPR_XCC_IDX3_PMON_ID, + }; + + const std::vector spr_mcc_stacks_enumeration = { + /* esDMI */ SPR_MCC_DMI_PMON_ID, + /* esPCIe0 */ SPR_MCC_PCIE_GEN5_0_PMON_ID, + /* esPCIe1 */ SPR_MCC_PCIE_GEN5_1_PMON_ID, + /* esPCIe2 */ SPR_MCC_PCIE_GEN5_2_PMON_ID, + /* esPCIe3 */ SPR_MCC_PCIE_GEN5_3_PMON_ID, + /* esPCIe4 */ SPR_MCC_PCIE_GEN5_4_PMON_ID, + /* esDINO0 */ SPR_MCC_IDX0_PMON_ID, + }; + + const std::vector emr_stacks_enumeration = { + /* esDMI */ EMR_DMI_PMON_ID, + /* esPCIe0 */ EMR_PCIE_GEN5_0_PMON_ID, + /* esPCIe1 */ EMR_PCIE_GEN5_1_PMON_ID, + /* esPCIe2 */ EMR_PCIE_GEN5_2_PMON_ID, + /* esPCIe3 */ EMR_PCIE_GEN5_3_PMON_ID, + /* esPCIe4 */ EMR_PCIE_GEN5_4_PMON_ID, + /* esDINO0 */ EMR_IDX0_PMON_ID, + /* esDINO1 */ EMR_IDX1_PMON_ID, + /* esDINO2 */ EMR_IDX2_PMON_ID, + /* esDINO3 */ EMR_IDX3_PMON_ID, + }; + + const std::map> es_stacks_enumeration = { + {estype::esSprXcc, spr_xcc_stacks_enumeration}, + {estype::esSprMcc, spr_mcc_stacks_enumeration}, + {estype::esEmrXcc, emr_stacks_enumeration }, + }; + + const std::map es_stack_names = { + {estype::esSprXcc, spr_xcc_iio_stack_names}, + {estype::esSprMcc, spr_mcc_iio_stack_names}, + {estype::esEmrXcc, emr_iio_stack_names }, + }; + + const std::map> es_sad_to_pmu_id_mapping = { + {estype::esSprXcc, spr_xcc_sad_to_pmu_id_mapping}, + {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping}, + {estype::esEmrXcc, emr_sad_to_pmu_id_mapping }, + }; +public: + EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {} + ~EagleStreamPlatformMapping() = default; + bool setChopValue(); + bool isXccPlatform() const { return m_chop == kXccChop; } + + const std::uint32_t kXccChop = 0b11; + const std::uint32_t kMccChop = 0b01; + + bool pciTreeDiscover(std::vector& iios) override; +}; + bool EagleStreamPlatformMapping::setChopValue() { for (uint16_t b = 0; b < 256; b++) { @@ -666,6 +1115,30 @@ bool EagleStreamPlatformMapping::pciTreeDiscover(std::vector grr_sad_to_pmu_id_mapping = { + { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID }, + { GRR_DLB_SAD_ID, GRR_DLB_PMON_ID }, + { GRR_NIS_QAT_SAD_ID, GRR_NIS_QAT_PMON_ID }, + }; +public: + LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} + ~LoganvillePlatform() = default; + bool pciTreeDiscover(std::vector& iios) override; +}; + bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) { struct iio_stack stack; @@ -823,6 +1296,18 @@ bool LoganvillePlatform::pciTreeDiscover(std::vector> &root_buses); +protected: + virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; +public: + Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + virtual ~Xeon6thNextGenPlatform() = default; + + virtual bool pciTreeDiscover(std::vector& iios) override; +}; + bool Xeon6thNextGenPlatform::getRootBuses(std::map> &root_buses) { bool mapped = true; @@ -889,6 +1374,72 @@ bool Xeon6thNextGenPlatform::pciTreeDiscover(std::vector srf_sad_to_pmu_id_mapping = { + { SRF_PE0_SAD_BUS_ID, SRF_PE0_PMON_ID }, + { SRF_PE1_SAD_BUS_ID, SRF_PE1_PMON_ID }, + { SRF_PE2_SAD_BUS_ID, SRF_PE2_PMON_ID }, + { SRF_PE3_SAD_BUS_ID, SRF_PE3_PMON_ID }, + { SRF_PE4_SAD_BUS_ID, SRF_PE4_PMON_ID }, + { SRF_FLEX_PE4_SAD_BUS_ID, SRF_FLEX_PE4_PMON_ID }, + { SRF_PE5_SAD_BUS_ID, SRF_PE5_PMON_ID }, + { SRF_FLEX_PE5_SAD_BUS_ID, SRF_FLEX_PE5_PMON_ID }, + { SRF_PE6_SAD_BUS_ID, SRF_PE6_PMON_ID }, + { SRF_PE7_SAD_BUS_ID, SRF_PE7_PMON_ID }, + { SRF_PE8_SAD_BUS_ID, SRF_PE8_PMON_ID }, + { SRF_HC0_SAD_BUS_ID, SRF_HC0_PMON_ID }, + { SRF_HC1_SAD_BUS_ID, SRF_HC1_PMON_ID }, + { SRF_HC2_SAD_BUS_ID, SRF_HC2_PMON_ID }, + { SRF_HC3_SAD_BUS_ID, SRF_HC3_PMON_ID }, + }; + + const std::unordered_set srf_pcie_stacks = { + SRF_PE0_SAD_BUS_ID, + SRF_PE1_SAD_BUS_ID, + SRF_PE2_SAD_BUS_ID, + SRF_PE3_SAD_BUS_ID, + SRF_PE4_SAD_BUS_ID, + SRF_FLEX_PE4_SAD_BUS_ID, + SRF_PE5_SAD_BUS_ID, + SRF_FLEX_PE5_SAD_BUS_ID, + SRF_PE6_SAD_BUS_ID, + SRF_PE7_SAD_BUS_ID, + SRF_PE8_SAD_BUS_ID + }; +protected: + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; +public: + BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} + ~BirchStreamPlatform() = default; +}; + bool BirchStreamPlatform::birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) { /* @@ -1030,6 +1581,18 @@ const std::string generate_stack_str(const int unit) return ss.str(); } +class KasseyvillePlatform: public Xeon6thNextGenPlatform { +private: + bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); + bool isUboxStack(int unit) + { + return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; + } +public: + KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} + ~KasseyvillePlatform() = default; +}; + bool KasseyvillePlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) { // Skip UBOX buses diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index ce4726b4..912070e2 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -7,8 +7,6 @@ // and others #pragma once -#include "cpucounters.h" - #ifdef _MSC_VER #include #include "windows/windriver.h" @@ -17,472 +15,18 @@ #endif #include -#include -#include -#include -#include // std::length_error #include -#include #include -#include #ifdef _MSC_VER #include "freegetopt/getopt.h" #endif #include "lspci.h" -#include "utils.h" using namespace std; using namespace pcm; -#define QAT_DID 0x18DA -#define NIS_DID 0x18D1 -#define HQM_DID 0x270B - -#define GRR_QAT_VRP_DID 0x5789 // Virtual Root Port to integrated QuickAssist (GRR QAT) -#define GRR_NIS_VRP_DID 0x5788 // VRP to Network Interface and Scheduler (GRR NIS) - -#define ROOT_BUSES_OFFSET 0xCC -#define ROOT_BUSES_OFFSET_2 0xD0 - -#define SKX_SOCKETID_UBOX_DID 0x2014 -#define SKX_UBOX_DEVICE_NUM 0x08 -#define SKX_UBOX_FUNCTION_NUM 0x02 -#define SKX_BUS_NUM_STRIDE 8 -//the below LNID and GID applies to Skylake Server -#define SKX_UNC_SOCKETID_UBOX_LNID_OFFSET 0xC0 -#define SKX_UNC_SOCKETID_UBOX_GID_OFFSET 0xD4 - -static const std::string iio_stack_names[6] = { - "IIO Stack 0 - CBDMA/DMI ", - "IIO Stack 1 - PCIe0 ", - "IIO Stack 2 - PCIe1 ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - MCP0 ", - "IIO Stack 5 - MCP1 " -}; - -static const std::string skx_iio_stack_names[6] = { - "IIO Stack 0 - CBDMA/DMI ", - "IIO Stack 1 - PCIe0 ", - "IIO Stack 2 - PCIe1 ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - MCP0 ", - "IIO Stack 5 - MCP1 " -}; - -static const std::string icx_iio_stack_names[6] = { - "IIO Stack 0 - PCIe0 ", - "IIO Stack 1 - PCIe1 ", - "IIO Stack 2 - MCP ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - PCIe3 ", - "IIO Stack 5 - CBDMA/DMI " -}; - -static const std::string icx_d_iio_stack_names[6] = { - "IIO Stack 0 - MCP ", - "IIO Stack 1 - PCIe0 ", - "IIO Stack 2 - CBDMA/DMI ", - "IIO Stack 3 - PCIe2 ", - "IIO Stack 4 - PCIe3 ", - "IIO Stack 5 - PCIe1 " -}; - -static const std::string snr_iio_stack_names[5] = { - "IIO Stack 0 - QAT ", - "IIO Stack 1 - CBDMA/DMI ", - "IIO Stack 2 - NIS ", - "IIO Stack 3 - HQM ", - "IIO Stack 4 - PCIe " -}; - -#define ICX_CBDMA_DMI_SAD_ID 0 -#define ICX_MCP_SAD_ID 3 - -#define ICX_PCH_PART_ID 0 -#define ICX_CBDMA_PART_ID 3 - -#define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4 -#define SNR_ICX_MESH2IIO_MMAP_DID 0x09A2 - -#define ICX_VMD_PCI_DEVNO 0x00 -#define ICX_VMD_PCI_FUNCNO 0x05 - -static const std::map icx_sad_to_pmu_id_mapping = { - { ICX_CBDMA_DMI_SAD_ID, 5 }, - { 1, 0 }, - { 2, 1 }, - { ICX_MCP_SAD_ID, 2 }, - { 4, 3 }, - { 5, 4 } -}; - -static const std::map icx_d_sad_to_pmu_id_mapping = { - { ICX_CBDMA_DMI_SAD_ID, 2 }, - { 1, 5 }, - { 2, 1 }, - { ICX_MCP_SAD_ID, 0 }, - { 4, 3 }, - { 5, 4 } -}; - -#define SNR_ACCELERATOR_PART_ID 4 - -#define SNR_ROOT_PORT_A_DID 0x334A - -#define SNR_CBDMA_DMI_SAD_ID 0 -#define SNR_PCIE_GEN3_SAD_ID 1 -#define SNR_HQM_SAD_ID 2 -#define SNR_NIS_SAD_ID 3 -#define SNR_QAT_SAD_ID 4 - -static const std::map snr_sad_to_pmu_id_mapping = { - { SNR_CBDMA_DMI_SAD_ID, 1 }, - { SNR_PCIE_GEN3_SAD_ID, 4 }, - { SNR_HQM_SAD_ID , 3 }, - { SNR_NIS_SAD_ID , 2 }, - { SNR_QAT_SAD_ID , 0 } -}; - -#define HQMV2_DID 0x2710 // Hardware Queue Manager v2 -#define HQMV25_DID 0x2714 // Hardware Queue Manager v2.5 -#define DSA_DID 0x0b25 // Data Streaming Accelerator (DSA) -#define IAX_DID 0x0cfe // In-Memory Database Analytics Accelerator (IAX) -#define QATV2_DID 0x4940 // QuickAssist (CPM) v2 - -#define SPR_DMI_PART_ID 7 -#define SPR_XCC_HQM_PART_ID 5 -#define SPR_MCC_HQM_PART_ID 4 -#define SPR_XCC_QAT_PART_ID 4 -#define SPR_MCC_QAT_PART_ID 5 -#define SPR_SAD_CONTROL_CFG_OFFSET SNR_ICX_SAD_CONTROL_CFG_OFFSET - -#define SPR_PCU_CR3_DID 0x325b -#define SPR_PCU_CR3_REG_DEVICE 0x1e -#define SPR_PCU_CR3_REG_FUNCTION 0x03 -#define SPR_CAPID4_OFFSET 0x94 -#define SPR_CAPID4_GET_PHYSICAL_CHOP(capid4) ((capid4 >> 6) & 3) -#define SPR_PHYSICAL_CHOP_XCC 0b11 -#define SPR_PHYSICAL_CHOP_MCC 0b01 - -#define SPR_XCC_DMI_PMON_ID 1 -#define SPR_XCC_PCIE_GEN5_0_PMON_ID 2 -#define SPR_XCC_PCIE_GEN5_1_PMON_ID 4 -#define SPR_XCC_PCIE_GEN5_2_PMON_ID 6 -#define SPR_XCC_PCIE_GEN5_3_PMON_ID 7 -#define SPR_XCC_PCIE_GEN5_4_PMON_ID 9 -#define SPR_XCC_IDX0_PMON_ID 0 -#define SPR_XCC_IDX1_PMON_ID 3 -#define SPR_XCC_IDX2_PMON_ID 5 -#define SPR_XCC_IDX3_PMON_ID 8 - -const std::map spr_xcc_sad_to_pmu_id_mapping = { - { 0, SPR_XCC_DMI_PMON_ID }, - { 1, SPR_XCC_PCIE_GEN5_0_PMON_ID }, - { 2, SPR_XCC_PCIE_GEN5_1_PMON_ID }, - { 3, SPR_XCC_PCIE_GEN5_2_PMON_ID }, - { 4, SPR_XCC_PCIE_GEN5_3_PMON_ID }, - { 5, SPR_XCC_PCIE_GEN5_4_PMON_ID }, - { 8, SPR_XCC_IDX0_PMON_ID }, - { 9, SPR_XCC_IDX1_PMON_ID }, - { 10, SPR_XCC_IDX2_PMON_ID }, - { 11, SPR_XCC_IDX3_PMON_ID } -}; - -#define SPR_MCC_DMI_PMON_ID 10 -#define SPR_MCC_PCIE_GEN5_0_PMON_ID 0 // assumption -#define SPR_MCC_PCIE_GEN5_1_PMON_ID 1 -#define SPR_MCC_PCIE_GEN5_2_PMON_ID 2 -#define SPR_MCC_PCIE_GEN5_3_PMON_ID 4 // assumption -#define SPR_MCC_PCIE_GEN5_4_PMON_ID 5 -#define SPR_MCC_IDX0_PMON_ID 3 - -const std::map spr_mcc_sad_to_pmu_id_mapping = { - { 0, SPR_MCC_PCIE_GEN5_0_PMON_ID }, - { 1, SPR_MCC_PCIE_GEN5_1_PMON_ID }, - { 2, SPR_MCC_PCIE_GEN5_2_PMON_ID }, - { 3, SPR_MCC_DMI_PMON_ID }, - { 4, SPR_MCC_PCIE_GEN5_3_PMON_ID }, - { 5, SPR_MCC_PCIE_GEN5_4_PMON_ID }, - { 8, SPR_MCC_IDX0_PMON_ID }, -}; - -static const std::string spr_xcc_iio_stack_names[] = { - "IIO Stack 0 - IDX0 ", - "IIO Stack 1 - DMI ", - "IIO Stack 2 - PCIe0 ", - "IIO Stack 3 - IDX1 ", - "IIO Stack 4 - PCIe1 ", - "IIO Stack 5 - IDX2 ", - "IIO Stack 6 - PCIe2 ", - "IIO Stack 7 - PCIe3", - "IIO Stack 8 - IDX3 ", - "IIO Stack 9 - PCIe4", - "IIO Stack 10 - NONE ", - "IIO Stack 11 - NONE ", -}; - -/* - * SPR MCC has 7 I/O stacks but PMON block for DMI has ID number 10. - * And just to follow such enumeration keep Stack 10 for DMI. - */ -static const std::string spr_mcc_iio_stack_names[] = { - "IIO Stack 0 - PCIe0 ", - "IIO Stack 1 - PCIe1 ", - "IIO Stack 2 - PCIe2 ", - "IIO Stack 3 - IDX0 ", - "IIO Stack 4 - PCIe3 ", - "IIO Stack 5 - PCIe4 ", - "IIO Stack 6 - NONE ", - "IIO Stack 7 - NONE ", - "IIO Stack 8 - NONE ", - "IIO Stack 9 - NONE ", - "IIO Stack 10 - DMI ", -}; - -// MS2IOSF stack IDs in CHA notation -#define GRR_PCH_DSA_GEN4_SAD_ID 0 -#define GRR_DLB_SAD_ID 1 -#define GRR_NIS_QAT_SAD_ID 2 - -#define GRR_PCH_DSA_GEN4_PMON_ID 2 -#define GRR_DLB_PMON_ID 1 -#define GRR_NIS_QAT_PMON_ID 0 - -// Stack 0 contains PCH, DSA and CPU PCIe Gen4 Complex -const std::map grr_sad_to_pmu_id_mapping = { - { GRR_PCH_DSA_GEN4_SAD_ID, GRR_PCH_DSA_GEN4_PMON_ID }, - { GRR_DLB_SAD_ID, GRR_DLB_PMON_ID }, - { GRR_NIS_QAT_SAD_ID, GRR_NIS_QAT_PMON_ID }, -}; - -#define GRR_DLB_PART_ID 0 -#define GRR_NIS_PART_ID 0 -#define GRR_QAT_PART_ID 1 - -static const std::string grr_iio_stack_names[3] = { - "IIO Stack 0 - NIS/QAT ", - "IIO Stack 1 - HQM ", - "IIO Stack 2 - PCH/DSA/PCIe " -}; - -#define EMR_DMI_PMON_ID 7 -#define EMR_PCIE_GEN5_0_PMON_ID 1 -#define EMR_PCIE_GEN5_1_PMON_ID 2 -#define EMR_PCIE_GEN5_2_PMON_ID 3 -#define EMR_PCIE_GEN5_3_PMON_ID 8 -#define EMR_PCIE_GEN5_4_PMON_ID 6 -#define EMR_IDX0_PMON_ID 0 -#define EMR_IDX1_PMON_ID 4 -#define EMR_IDX2_PMON_ID 5 -#define EMR_IDX3_PMON_ID 9 - -const std::map emr_sad_to_pmu_id_mapping = { - { 0, EMR_DMI_PMON_ID }, - { 1, EMR_PCIE_GEN5_0_PMON_ID }, - { 2, EMR_PCIE_GEN5_1_PMON_ID }, - { 3, EMR_PCIE_GEN5_2_PMON_ID }, - { 4, EMR_PCIE_GEN5_3_PMON_ID }, - { 5, EMR_PCIE_GEN5_4_PMON_ID }, - { 8, EMR_IDX0_PMON_ID }, - { 9, EMR_IDX1_PMON_ID }, - { 10, EMR_IDX2_PMON_ID }, - { 11, EMR_IDX3_PMON_ID } -}; - -static const std::string emr_iio_stack_names[] = { - "IIO Stack 0 - IDX0 ", - "IIO Stack 1 - PCIe3 ", - "IIO Stack 2 - PCIe0 ", - "IIO Stack 3 - IDX1 ", - "IIO Stack 4 - PCIe1 ", - "IIO Stack 5 - IDX2 ", - "IIO Stack 6 - PCIe2 ", - "IIO Stack 7 - DMI", - "IIO Stack 8 - IDX3 ", - "IIO Stack 9 - PCIe4", - "IIO Stack 10 - NONE ", - "IIO Stack 11 - NONE ", -}; - -enum EagleStreamPlatformStacks -{ - esDMI = 0, - esPCIe0, - esPCIe1, - esPCIe2, - esPCIe3, - esPCIe4, - esDINO0, - esDINO1, - esDINO2, - esDINO3, - esEndOfList -}; - -const std::vector spr_xcc_stacks_enumeration = { - /* esDMI */ SPR_XCC_DMI_PMON_ID, - /* esPCIe0 */ SPR_XCC_PCIE_GEN5_0_PMON_ID, - /* esPCIe1 */ SPR_XCC_PCIE_GEN5_1_PMON_ID, - /* esPCIe2 */ SPR_XCC_PCIE_GEN5_2_PMON_ID, - /* esPCIe3 */ SPR_XCC_PCIE_GEN5_3_PMON_ID, - /* esPCIe4 */ SPR_XCC_PCIE_GEN5_4_PMON_ID, - /* esDINO0 */ SPR_XCC_IDX0_PMON_ID, - /* esDINO1 */ SPR_XCC_IDX1_PMON_ID, - /* esDINO2 */ SPR_XCC_IDX2_PMON_ID, - /* esDINO3 */ SPR_XCC_IDX3_PMON_ID, -}; - -const std::vector spr_mcc_stacks_enumeration = { - /* esDMI */ SPR_MCC_DMI_PMON_ID, - /* esPCIe0 */ SPR_MCC_PCIE_GEN5_0_PMON_ID, - /* esPCIe1 */ SPR_MCC_PCIE_GEN5_1_PMON_ID, - /* esPCIe2 */ SPR_MCC_PCIE_GEN5_2_PMON_ID, - /* esPCIe3 */ SPR_MCC_PCIE_GEN5_3_PMON_ID, - /* esPCIe4 */ SPR_MCC_PCIE_GEN5_4_PMON_ID, - /* esDINO0 */ SPR_MCC_IDX0_PMON_ID, -}; - -const std::vector emr_stacks_enumeration = { - /* esDMI */ EMR_DMI_PMON_ID, - /* esPCIe0 */ EMR_PCIE_GEN5_0_PMON_ID, - /* esPCIe1 */ EMR_PCIE_GEN5_1_PMON_ID, - /* esPCIe2 */ EMR_PCIE_GEN5_2_PMON_ID, - /* esPCIe3 */ EMR_PCIE_GEN5_3_PMON_ID, - /* esPCIe4 */ EMR_PCIE_GEN5_4_PMON_ID, - /* esDINO0 */ EMR_IDX0_PMON_ID, - /* esDINO1 */ EMR_IDX1_PMON_ID, - /* esDINO2 */ EMR_IDX2_PMON_ID, - /* esDINO3 */ EMR_IDX3_PMON_ID, -}; - -enum class EagleStreamSupportedTypes -{ - esInvalid = -1, - esSprXcc, - esSprMcc, - esEmrXcc -}; - -typedef EagleStreamSupportedTypes estype; - -const std::map> es_stacks_enumeration = { - {estype::esSprXcc, spr_xcc_stacks_enumeration}, - {estype::esSprMcc, spr_mcc_stacks_enumeration}, - {estype::esEmrXcc, emr_stacks_enumeration }, -}; - -const std::map es_stack_names = { - {estype::esSprXcc, spr_xcc_iio_stack_names}, - {estype::esSprMcc, spr_mcc_iio_stack_names}, - {estype::esEmrXcc, emr_iio_stack_names }, -}; - -const std::map> es_sad_to_pmu_id_mapping = { - {estype::esSprXcc, spr_xcc_sad_to_pmu_id_mapping}, - {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping}, - {estype::esEmrXcc, emr_sad_to_pmu_id_mapping }, -}; - -#define SRF_PE0_PMON_ID 3 -#define SRF_PE1_PMON_ID 4 -#define SRF_PE2_PMON_ID 2 -#define SRF_PE3_PMON_ID 5 -/* - * There are platform configuration when FlexUPI stacks (stacks 5 and 6) are enabled as - * PCIe stack and PCIe ports are disabled (ports 2 and 3) and vice sersa. See details here: - * In these cases the PMON IDs are different. - * So, defines with _FLEX_ are applicable for cases when FlexUPI stacks - * are working as PCIe ports. - */ -#define SRF_PE4_PMON_ID 11 -#define SRF_FLEX_PE4_PMON_ID 13 -#define SRF_PE5_PMON_ID 12 -#define SRF_FLEX_PE5_PMON_ID 10 - -#define SRF_PE6_PMON_ID 0 -#define SRF_PE7_PMON_ID 7 -#define SRF_PE8_PMON_ID 8 -#define SRF_HC0_PMON_ID 1 -#define SRF_HC1_PMON_ID 6 -#define SRF_HC2_PMON_ID 9 -#define SRF_HC3_PMON_ID 14 - -#define SRF_PE0_SAD_BUS_ID 2 -#define SRF_PE1_SAD_BUS_ID 3 -#define SRF_PE2_SAD_BUS_ID 1 -#define SRF_PE3_SAD_BUS_ID 4 -#define SRF_PE4_SAD_BUS_ID 29 -#define SRF_FLEX_PE4_SAD_BUS_ID SRF_PE4_SAD_BUS_ID -#define SRF_PE5_SAD_BUS_ID 26 -#define SRF_FLEX_PE5_SAD_BUS_ID SRF_PE5_SAD_BUS_ID -#define SRF_PE6_SAD_BUS_ID 0 // UPI0 -#define SRF_PE7_SAD_BUS_ID 5 // UPI1 -#define SRF_PE8_SAD_BUS_ID 28 // UPI2 -#define SRF_UBOXA_SAD_BUS_ID 30 -#define SRF_UBOXB_SAD_BUS_ID 31 - -const std::set srf_pcie_stacks({ - SRF_PE0_SAD_BUS_ID, - SRF_PE1_SAD_BUS_ID, - SRF_PE2_SAD_BUS_ID, - SRF_PE3_SAD_BUS_ID, - SRF_PE4_SAD_BUS_ID, - SRF_FLEX_PE4_SAD_BUS_ID, - SRF_PE5_SAD_BUS_ID, - SRF_FLEX_PE5_SAD_BUS_ID, - SRF_PE6_SAD_BUS_ID, - SRF_PE7_SAD_BUS_ID, - SRF_PE8_SAD_BUS_ID, -}); - -#define SRF_HC0_SAD_BUS_ID 8 -#define SRF_HC1_SAD_BUS_ID 12 -#define SRF_HC2_SAD_BUS_ID 20 -#define SRF_HC3_SAD_BUS_ID 16 - -const std::map srf_sad_to_pmu_id_mapping = { - { SRF_PE0_SAD_BUS_ID, SRF_PE0_PMON_ID }, - { SRF_PE1_SAD_BUS_ID, SRF_PE1_PMON_ID }, - { SRF_PE2_SAD_BUS_ID, SRF_PE2_PMON_ID }, - { SRF_PE3_SAD_BUS_ID, SRF_PE3_PMON_ID }, - { SRF_PE4_SAD_BUS_ID, SRF_PE4_PMON_ID }, - { SRF_FLEX_PE4_SAD_BUS_ID, SRF_FLEX_PE4_PMON_ID }, - { SRF_PE5_SAD_BUS_ID, SRF_PE5_PMON_ID }, - { SRF_FLEX_PE5_SAD_BUS_ID, SRF_FLEX_PE5_PMON_ID }, - { SRF_PE6_SAD_BUS_ID, SRF_PE6_PMON_ID }, - { SRF_PE7_SAD_BUS_ID, SRF_PE7_PMON_ID }, - { SRF_PE8_SAD_BUS_ID, SRF_PE8_PMON_ID }, - { SRF_HC0_SAD_BUS_ID, SRF_HC0_PMON_ID }, - { SRF_HC1_SAD_BUS_ID, SRF_HC1_PMON_ID }, - { SRF_HC2_SAD_BUS_ID, SRF_HC2_PMON_ID }, - { SRF_HC3_SAD_BUS_ID, SRF_HC3_PMON_ID }, -}; - -#define SRF_DSA_IAX_PART_NUMBER 0 -#define SRF_HQM_PART_NUMBER 5 -#define SRF_QAT_PART_NUMBER 4 - -static const std::string srf_iio_stack_names[] = { - "IIO Stack 0 - PCIe6 ", // SRF_PE6_PMON_ID 0 - "IIO Stack 1 - HCx0 ", // SRF_HC0_PMON_ID 1 - "IIO Stack 2 - PCIe2 ", // SRF_PE2_PMON_ID 2 - "IIO Stack 3 - PCIe0 ", // SRF_PE0_PMON_ID 3 - "IIO Stack 4 - PCIe1 ", // SRF_PE1_PMON_ID 4 - "IIO Stack 5 - PCIe3 ", // SRF_PE3_PMON_ID 5 - "IIO Stack 6 - HCx1 ", // SRF_HC1_PMON_ID 6 - "IIO Stack 7 - PCIe7 ", // SRF_PE7_PMON_ID 7 - "IIO Stack 8 - PCIe8 ", // SRF_PE8_PMON_ID 8 - "IIO Stack 9 - HCx3 ", // SRF_HC3_PMON_ID 9 - "IIO Stack 10 - Flex PCIe5", // SRF_FLEX_PE5_PMON_ID 10 - "IIO Stack 11 - PCIe4 ", // SRF_PE4_PMON_ID 11 - "IIO Stack 12 - PCIe5 ", // SRF_PE5_PMON_ID 12 - "IIO Stack 13 - Flex PCIe4", // SRF_FLEX_PE4_PMON_ID 13 - "IIO Stack 14 - HCx2 ", // SRF_HC2_PMON_ID 14 -}; - class IPlatformMapping { private: uint32_t m_sockets; @@ -499,125 +43,4 @@ class IPlatformMapping { uint32_t cpuId() const { return m_model; } }; -// Mapping for SkyLake Server. -class PurleyPlatformMapping: public IPlatformMapping { -private: - void getUboxBusNumbers(std::vector& ubox); -public: - PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} - ~PurleyPlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; -}; - -class IPlatformMapping10Nm: public IPlatformMapping { -private: -public: - IPlatformMapping10Nm(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} - ~IPlatformMapping10Nm() = default; - bool getSadIdRootBusMap(uint32_t socket_id, std::map& sad_id_bus_map); -}; - -// Mapping for IceLake Server. -class WhitleyPlatformMapping: public IPlatformMapping10Nm { -private: - const bool icx_d; - const std::map& sad_to_pmu_id_mapping; - const std::string * iio_stack_names; -public: - WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count), - icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), - sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping), - iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names) - { - } - ~WhitleyPlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; -}; - -// Mapping for Snowridge. -class JacobsvillePlatformMapping: public IPlatformMapping10Nm { -private: -public: - JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} - ~JacobsvillePlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; - bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); -}; - -class EagleStreamPlatformMapping: public IPlatformMapping -{ -private: - bool getRootBuses(std::map> &root_buses); - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool eagleStreamDmiStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool eagleStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool eagleStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool isDmiStack(int unit); - bool isPcieStack(int unit); - bool isDinoStack(int unit); - std::uint32_t m_chop; - EagleStreamSupportedTypes m_es_type; -public: - EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {} - ~EagleStreamPlatformMapping() = default; - bool setChopValue(); - bool isXccPlatform() const { return m_chop == kXccChop; } - - const std::uint32_t kXccChop = 0b11; - const std::uint32_t kMccChop = 0b01; - - bool pciTreeDiscover(std::vector& iios) override; -}; - -class LoganvillePlatform: public IPlatformMapping10Nm { -private: - bool loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); - bool loganvilleDlbStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); - bool loganvilleNacStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id); -public: - LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} - ~LoganvillePlatform() = default; - bool pciTreeDiscover(std::vector& iios) override; -}; - -class Xeon6thNextGenPlatform: public IPlatformMapping { -private: - bool getRootBuses(std::map> &root_buses); -protected: - virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; -public: - Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} - virtual ~Xeon6thNextGenPlatform() = default; - - virtual bool pciTreeDiscover(std::vector& iios) override; -}; - -class BirchStreamPlatform: public Xeon6thNextGenPlatform { -private: - bool isPcieStack(int unit); - bool isRootHcStack(int unit); - bool isPartHcStack(int unit); - bool isUboxStack(int unit); - - bool birchStreamPciStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool birchStreamAcceleratorStackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); -protected: - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; -public: - BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} - ~BirchStreamPlatform() = default; -}; - -class KasseyvillePlatform: public Xeon6thNextGenPlatform { -private: - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool isUboxStack(int unit) - { - return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; - } -public: - KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} - ~KasseyvillePlatform() = default; -}; - void initializeIOStacksStructure( std::vector& iios ); \ No newline at end of file From 88e4f4297710ace8b8443d586e3345930286cc0f Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 30 Sep 2025 04:28:39 -0700 Subject: [PATCH 25/54] Cosmetic changes --- src/cpucounters.h | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/src/cpucounters.h b/src/cpucounters.h index 2f7d649a..2fa25248 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -313,7 +313,7 @@ class IDX_PMU std::vector counterFilterENG; std::vector counterFilterTC; std::vector counterFilterPGSZ; - std::vector counterFilterXFERSZ; + std::vector counterFilterXFERSZ; IDX_PMU(const bool perfMode_, const uint32 numaNode_, @@ -570,7 +570,6 @@ class SimpleCounterState friend uint64 getNumberOfEvents(const T & before, const T & after); friend class PCM; uint64 data; - public: SimpleCounterState() : data(0) { } @@ -1757,7 +1756,7 @@ class PCM_API PCM One needs to call this method when your program finishes or/and you are not going to use the performance counting routines anymore. -*/ + */ void cleanup(const bool silent = false); /*! \brief Forces PMU reset @@ -1835,7 +1834,7 @@ class PCM_API PCM \return Number of sockets in the system */ uint32 getNumSockets() const; - + /*! \brief Reads the accel type in the system \return acceltype */ @@ -1853,7 +1852,7 @@ class PCM_API PCM /*! \brief Sets the Number of AccelCounters in the system \return number of counters - */ + */ void setNumberofAccelCounters(uint32 input); /*! \brief Reads number of online sockets (CPUs) in the system @@ -2426,19 +2425,18 @@ class PCM_API PCM //! \brief Control QAT telemetry service //! \param dev device index - //! \param operation control code + //! \param operation control code void controlQATTelemetry(uint32 dev, uint32 operation); //! \brief Program IDX events //! \param events config of event to program - //! \param filters_wq filters(work queue) of event to program - //! \param filters_eng filters(engine) of event to program - //! \param filters_tc filters(traffic class) of event to program - //! \param filters_pgsz filters(page size) of event to program - //! \param filters_xfersz filters(transfer size) of event to program + //! \param filters_wq filters(work queue) of event to program + //! \param filters_eng filters(engine) of event to program + //! \param filters_tc filters(traffic class) of event to program + //! \param filters_pgsz filters(page size) of event to program + //! \param filters_xfersz filters(transfer size) of event to program void programIDXAccelCounters(uint32 accel, std::vector &events, std::vector &filters_wq, std::vector &filters_eng, std::vector &filters_tc, std::vector &filters_pgsz, std::vector &filters_xfersz); - //! \brief Get the state of IIO counter //! \param socket socket of the IIO stack //! \param IIOStack id of the IIO stack @@ -2672,7 +2670,7 @@ class PCM_API PCM || cpu_family_model == PCM::GNR_D ); } - + bool memoryTrafficMetricsAvailable() const { return (!(isAtom() || cpu_family_model == PCM::CLARKDALE)) From 1f649213ccf485762f13d43c7f6e4da716f52be3 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Wed, 8 Oct 2025 01:52:57 -0700 Subject: [PATCH 26/54] Add wrapper for getting stack index --- src/pcm-iio-pmu.cpp | 4 ++-- src/pcm-iio-pmu.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index f459d1ab..5351f338 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -454,7 +454,7 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) for (const auto& socket : m_config.iios) { for (const auto& stack : socket.stacks) { auto iio_unit_id = stack.iio_unit_id; - uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; + uint32_t idx = getStackIndex(socket.socket_id, iio_unit_id); m_before[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx); } } @@ -462,7 +462,7 @@ result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) for (const auto& socket : m_config.iios) { for (const auto& stack : socket.stacks) { auto iio_unit_id = stack.iio_unit_id; - uint32_t idx = m_stacks_count * socket.socket_id + iio_unit_id; + uint32_t idx = getStackIndex(socket.socket_id, iio_unit_id); m_after[idx] = strategy->getCounterState(socket.socket_id, iio_unit_id, ctr.idx); uint64_t raw_result = getNumberOfEvents(m_before[idx], m_after[idx]); uint64_t trans_result = static_cast(raw_result * ctr.multiplier * m_time_scaling_factor); diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 31a4f029..5eee5667 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -110,6 +110,8 @@ class PcmIioDataCollector { result_content getSample(struct iio_counter & ctr); void initializeCounterHandlers(); + uint32_t getStackIndex(uint32_t socket_id, uint32_t io_unit_id) const { return m_stacks_count * socket_id + io_unit_id; } + static constexpr int COUNTERS_NUMBER = 4; }; From 153caaf761bbf7c907ecb8515f21958d26308cdb Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Wed, 8 Oct 2025 01:53:17 -0700 Subject: [PATCH 27/54] Add logs to load_events() --- src/utils.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/utils.cpp b/src/utils.cpp index 29caec0a..915bf5f0 100644 --- a/src/utils.cpp +++ b/src/utils.cpp @@ -1196,6 +1196,7 @@ int load_events(const std::string &fn, std::map &ofm, if (!in.is_open()) { const auto alt_fn = getInstallPathPrefix() + fn; + std::cout << "INFO: Couldn't load event config file " << fn << ", trying to load it from PCM install path: " << alt_fn << std::endl; in.open(alt_fn); if (!in.is_open()) { From 9170a93219f5f30ed360a029fd6dd61e91c832e7 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Thu, 9 Oct 2025 05:22:53 -0700 Subject: [PATCH 28/54] Introduce static member cpuFamilyModelToUArchCodename() --- src/cpucounters.cpp | 26 +++++++++++++++++--------- src/cpucounters.h | 12 +++++++++++- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index b662fa3c..5c62f4de 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -4980,12 +4980,8 @@ bool PCM::PMUinUse() return false; } -const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const +const char * PCM::cpuFamilyModelToUArchCodename(const int32 cpu_family_model_, const int32 cpu_stepping_) { - auto cpu_family_model_ = cpu_family_model_param; - if(cpu_family_model_ < 0) - cpu_family_model_ = this->cpu_family_model; - switch(cpu_family_model_) { case CENTERTON: @@ -5068,16 +5064,16 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const case ARL: return "Arrow Lake"; case SKX: - if (cpu_family_model_param >= 0) + if (cpu_stepping_ < 0) { - // query for specified cpu_family_model_param, stepping not provided + // Stepping is not provided return "Skylake-SP, Cascade Lake-SP"; } - if (isCLX()) + if (isCLX(cpu_family_model_, cpu_stepping_)) { return "Cascade Lake-SP"; } - if (isCPX()) + if (isCPX(cpu_family_model_, cpu_stepping_)) { return "Cooper Lake"; } @@ -5100,6 +5096,18 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const return "unknown"; } +const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const +{ + auto cpu_family_model_ = cpu_family_model_param; + auto cpu_stepping_ = -1; + if (cpu_family_model_ < 0) { + cpu_family_model_ = this->cpu_family_model; + cpu_stepping_ = this->cpu_stepping; + } + + return cpuFamilyModelToUArchCodename(cpu_family_model_, cpu_stepping_); +} + #ifdef PCM_USE_PERF void PCM::closePerfHandles(const bool silent) { diff --git a/src/cpucounters.h b/src/cpucounters.h index 2fa25248..173a0ce2 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1281,9 +1281,14 @@ class PCM_API PCM void programCXLCM(const uint64* events); void cleanupUncorePMUs(const bool silent = false); + static bool isCLX(int cpu_family_model_, int cpu_stepping_) + { + return (PCM::SKX == cpu_family_model_) && (cpu_stepping_ > 4 && cpu_stepping_ < 8); + } + bool isCLX() const // Cascade Lake-SP { - return (PCM::SKX == cpu_family_model) && (cpu_stepping > 4 && cpu_stepping < 8); + return isCLX(cpu_family_model, cpu_stepping); } static bool isCPX(int cpu_family_model_, int cpu_stepping_) // Cooper Lake @@ -2467,6 +2472,11 @@ class PCM_API PCM //! \param cpu_family_model_ cpu model (if no parameter provided the codename of the detected CPU is returned) const char * getUArchCodename(const int32 cpu_family_model_ = -1) const; + //! \brief Convert CPU Family/Model/Stepping to microarchitecture codename + //! \param cpu_family_model_ cpu family model + //! \param cpu_stepping necessary for some CPU models to distinguish between different microarchitectures + static const char * cpuFamilyModelToUArchCodename(const int32 cpu_family_model_, const int32 cpu_stepping_ = -1); + //! \brief Get Brand string of processor static std::string getCPUBrandString(); std::string getCPUFamilyModelString(); From 32a724a7ab94a83c8261fa0bd5c8745a2226f8dd Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Wed, 8 Oct 2025 06:56:36 -0700 Subject: [PATCH 29/54] Use cpu_model number in iio_evt_parse_context instead of pointer to PCM instance --- src/pcm-iio-pmu.cpp | 13 ++++++------- src/pcm-iio-pmu.h | 2 +- tests/utests/pcm-iio-utest.cpp | 6 ++++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 5351f338..680d451a 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -275,9 +275,9 @@ std::unique_ptr getDisplayBuilder(struct pcm_iio_config& co return displayBuilder; } -ccr* get_ccr(PCM* m, uint64_t& ccr) +ccr* get_ccr(uint32 cpu_family_model, uint64_t& ccr) { - switch (m->getCPUFamilyModel()) + switch (cpu_family_model) { case PCM::SKX: return new pcm::ccr(ccr, ccr::ccr_type::skx); @@ -291,7 +291,7 @@ ccr* get_ccr(PCM* m, uint64_t& ccr) case PCM::GNR_D: return new pcm::ccr(ccr, ccr::ccr_type::icx); default: - cerr << m->getCPUFamilyModelString() << " is not supported! Program aborted" << endl; + std::cerr << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is not supported! Program aborted" << std::endl; exit(EXIT_FAILURE); } } @@ -299,7 +299,6 @@ ccr* get_ccr(PCM* m, uint64_t& ccr) int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, std::map &ofm, std::string key, uint64 numValue) { iio_evt_parse_context *context = (iio_evt_parse_context *)cb_ctx; - PCM *m = context->m; if (cb_type == EVT_LINE_START) //this event will be called per line(start) { @@ -307,7 +306,7 @@ int iio_evt_parse_handler(evt_cb_type cb_type, void *cb_ctx, counter &base_ctr, } else if (cb_type == EVT_LINE_FIELD) //this event will be called per field of line { - std::unique_ptr pccr(get_ccr(m, context->ctr.ccr)); + std::unique_ptr pccr(get_ccr(context->cpu_family_model, context->ctr.ccr)); switch (ofm[key]) { case PCM::OPCODE: @@ -445,7 +444,7 @@ void PcmIioDataCollector::collectData() result_content PcmIioDataCollector::getSample(struct iio_counter & ctr) { uint64 rawEvents[COUNTERS_NUMBER] = {0}; - std::unique_ptr pccr(get_ccr(m_pcm, ctr.ccr)); + std::unique_ptr pccr(get_ccr(m_pcm->getCPUFamilyModel(), ctr.ccr)); rawEvents[ctr.idx] = pccr->get_ccr_value(); auto strategy = m_strategies[static_cast(ctr.type)]; @@ -502,7 +501,7 @@ void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventN map opcodeFieldMap; fillOpcodeFieldMapForPCIeEvents( opcodeFieldMap ); - evt_ctx.m = m; + evt_ctx.cpu_family_model = m->getCPUFamilyModel(); evt_ctx.ctrs.clear();//fill the ctrs by evt_handler call back func. try diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index 5eee5667..ec203278 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -37,7 +37,7 @@ struct iio_counter : public counter { typedef struct { - PCM *m; + uint32 cpu_family_model; iio_counter ctr; vector ctrs; } iio_evt_parse_context; diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp index 2072156c..ed1fd16a 100644 --- a/tests/utests/pcm-iio-utest.cpp +++ b/tests/utests/pcm-iio-utest.cpp @@ -16,10 +16,8 @@ class LoadEventsTest : public ::testing::Test { protected: void SetUp() override { - fillOpcodeFieldMapForPCIeEvents(opcodeFieldMap); - evt_ctx.m = PCM::getInstance(); evt_ctx.ctrs.clear(); } @@ -67,6 +65,8 @@ TEST_F(LoadEventsTest, TestLoadEventsAlternateVersion) { const std::string eventFile = "opCode-6-174.txt"; + evt_ctx.cpu_family_model = PCM_CPU_FAMILY_MODEL(6, 174); + // Test the alternate version of load_events without nameMap ASSERT_NO_THROW({ load_events(eventFile, opcodeFieldMap, iio_evt_parse_handler, &evt_ctx); @@ -141,6 +141,8 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) {3, 0x41, 0xc0, 0x0, 0x0, 1, "IOMMU Mem Access", "Total", CounterType::iio}, }; + evt_ctx.cpu_family_model = PCM_CPU_FAMILY_MODEL(6, 174); + // 2. Load events using the existing function evt_ctx.ctrs.clear(); ASSERT_NO_THROW({ From 9dc951d58ea14dabe353f6260fa2a5ed24d84ca0 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 00:56:37 -0700 Subject: [PATCH 30/54] Add default implementation of IPlatformMapping --- src/pcm-iio-topology.cpp | 24 +++++++++++++++++++++++- src/pcm-iio-topology.h | 2 +- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 8a3dee14..fabcc04c 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1629,6 +1629,27 @@ void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int d } } +bool IPlatformMapping::pciTreeDiscover(std::vector& iios) +{ + const auto pcm = PCM::getInstance(); + int stacksNumber = static_cast(pcm->getMaxNumOfIOStacks()); + for (uint32_t socket = 0; socket < socketsCount(); socket++) + { + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = socket; + for (int unit = 0; unit < stacksNumber; unit++) + { + struct iio_stack stack; + stack.iio_unit_id = unit; + stack.stack_name = generate_stack_str(unit); + iio_on_socket.stacks.push_back(stack); + } + iios.push_back(iio_on_socket); + } + + return true; +} + std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count) { switch (cpu_family_model) { @@ -1650,7 +1671,8 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for Graniterapids-D is provided" << std::endl; return std::unique_ptr{new KasseyvillePlatform(cpu_family_model, sockets_count)}; default: - return nullptr; + std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is provided" << std::endl; + return std::unique_ptr{new IPlatformMapping(cpu_family_model, sockets_count)}; } } diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index 912070e2..a254e8e3 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -37,7 +37,7 @@ class IPlatformMapping { IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} virtual ~IPlatformMapping() {}; static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count); - virtual bool pciTreeDiscover(std::vector& iios) = 0; + virtual bool pciTreeDiscover(std::vector& iios); uint32_t socketsCount() const { return m_sockets; } uint32_t cpuId() const { return m_model; } From 448ed77fedc1ca9e36b81f0f23ca1fcb4f1f8de4 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 01:05:01 -0700 Subject: [PATCH 31/54] Remove dummy implementation for GNR-D --- src/pcm-iio-topology.cpp | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index fabcc04c..44a5fa8f 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1581,33 +1581,6 @@ const std::string generate_stack_str(const int unit) return ss.str(); } -class KasseyvillePlatform: public Xeon6thNextGenPlatform { -private: - bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket); - bool isUboxStack(int unit) - { - return SRF_UBOXA_SAD_BUS_ID == unit || SRF_UBOXB_SAD_BUS_ID == unit; - } -public: - KasseyvillePlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} - ~KasseyvillePlatform() = default; -}; - -bool KasseyvillePlatform::stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) -{ - // Skip UBOX buses - if (isUboxStack(unit)) return true; - - // To suppress compilation warning - (void)address; - - struct iio_stack stack; - stack.iio_unit_id = unit; - stack.stack_name = generate_stack_str(unit); - iio_on_socket.stacks.push_back(stack); - return true; -} - void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int domain, int secondary, int subordinate) { for (uint8_t bus = secondary; int(bus) <= subordinate; bus++) { @@ -1667,9 +1640,6 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f case PCM::SRF: case PCM::GNR: return std::unique_ptr{new BirchStreamPlatform(cpu_family_model, sockets_count)}; - case PCM::GNR_D: - std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for Graniterapids-D is provided" << std::endl; - return std::unique_ptr{new KasseyvillePlatform(cpu_family_model, sockets_count)}; default: std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is provided" << std::endl; return std::unique_ptr{new IPlatformMapping(cpu_family_model, sockets_count)}; From a7fd82f138a26b0d4d86d118449d4590a59300ad Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 01:08:36 -0700 Subject: [PATCH 32/54] Use make_unique in factory method --- src/pcm-iio-topology.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 44a5fa8f..e01e7bf8 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1627,22 +1627,22 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f { switch (cpu_family_model) { case PCM::SKX: - return std::unique_ptr{new PurleyPlatformMapping(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); case PCM::ICX: - return std::unique_ptr{new WhitleyPlatformMapping(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); case PCM::SNOWRIDGE: - return std::unique_ptr{new JacobsvillePlatformMapping(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); case PCM::SPR: case PCM::EMR: - return std::unique_ptr{new EagleStreamPlatformMapping(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); case PCM::GRR: - return std::unique_ptr{new LoganvillePlatform(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); case PCM::SRF: case PCM::GNR: - return std::unique_ptr{new BirchStreamPlatform(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); default: std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is provided" << std::endl; - return std::unique_ptr{new IPlatformMapping(cpu_family_model, sockets_count)}; + return std::make_unique(cpu_family_model, sockets_count); } } From ec54cdf364264b44a44dec04521e86d919a3a5ef Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 01:11:59 -0700 Subject: [PATCH 33/54] Move socketsCount() and cpuId() to protected part --- src/pcm-iio-topology.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index a254e8e3..2b222261 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -33,14 +33,14 @@ class IPlatformMapping { uint32_t m_model; protected: void probeDeviceRange(std::vector &child_pci_devs, int domain, int secondary, int subordinate); + + uint32_t socketsCount() const { return m_sockets; } + uint32_t cpuId() const { return m_model; } public: IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} virtual ~IPlatformMapping() {}; static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count); virtual bool pciTreeDiscover(std::vector& iios); - - uint32_t socketsCount() const { return m_sockets; } - uint32_t cpuId() const { return m_model; } }; void initializeIOStacksStructure( std::vector& iios ); \ No newline at end of file From ccb660172281475d7c2ce74c15788120c9bfe519 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 01:24:13 -0700 Subject: [PATCH 34/54] Use stacks count as input parameter --- src/pcm-iio-topology.cpp | 12 +++++------- src/pcm-iio-topology.h | 6 +++++- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index e01e7bf8..11068370 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1604,13 +1604,11 @@ void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int d bool IPlatformMapping::pciTreeDiscover(std::vector& iios) { - const auto pcm = PCM::getInstance(); - int stacksNumber = static_cast(pcm->getMaxNumOfIOStacks()); for (uint32_t socket = 0; socket < socketsCount(); socket++) { struct iio_stacks_on_socket iio_on_socket; iio_on_socket.socket_id = socket; - for (int unit = 0; unit < stacksNumber; unit++) + for (uint32_t unit = 0; unit < stacksCount(); unit++) { struct iio_stack stack; stack.iio_unit_id = unit; @@ -1623,7 +1621,7 @@ bool IPlatformMapping::pciTreeDiscover(std::vector& return true; } -std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count) +std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count, uint32_t stacks_count) { switch (cpu_family_model) { case PCM::SKX: @@ -1642,14 +1640,14 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f return std::make_unique(cpu_family_model, sockets_count); default: std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is provided" << std::endl; - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(cpu_family_model, sockets_count, stacks_count); } } void initializeIOStacksStructure( std::vector& iios ) { - PCM * m = PCM::getInstance(); - auto mapping = IPlatformMapping::getPlatformMapping(m->getCPUFamilyModel(), m->getNumSockets()); + PCM * pcm = PCM::getInstance(); + auto mapping = IPlatformMapping::getPlatformMapping(pcm->getCPUFamilyModel(), pcm->getNumSockets(), pcm->getMaxNumOfIOStacks()); if (!mapping) { cerr << "Failed to discover pci tree: unknown platform" << endl; exit(EXIT_FAILURE); diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index 2b222261..5b6c1236 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -31,15 +31,19 @@ class IPlatformMapping { private: uint32_t m_sockets; uint32_t m_model; + uint32_t m_stacks = 0; protected: void probeDeviceRange(std::vector &child_pci_devs, int domain, int secondary, int subordinate); uint32_t socketsCount() const { return m_sockets; } uint32_t cpuId() const { return m_model; } + uint32_t stacksCount() const { return m_stacks; } public: IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} + IPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) : + m_sockets(sockets_count), m_model(cpu_model), m_stacks(stacks_count) {} virtual ~IPlatformMapping() {}; - static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count); + static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count); virtual bool pciTreeDiscover(std::vector& iios); }; From b583ff3522791f1ed82afc627064685f660e95f7 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 01:59:41 -0700 Subject: [PATCH 35/54] Update error handling flow --- src/pcm-iio-pmu.cpp | 18 +++++++++--------- src/pcm-iio-pmu.h | 2 -- src/pcm-iio-topology.cpp | 21 ++++++++++++--------- src/pcm-iio-topology.h | 2 +- 4 files changed, 22 insertions(+), 21 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 680d451a..cf859c6c 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -492,7 +492,7 @@ void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap) opcodeFieldMap["unit"] = PCM::UNIT_TYPE; } -void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap) +bool setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap) { PCM * m = PCM::getInstance(); @@ -508,12 +508,14 @@ void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventN { load_events(ev_file_name, opcodeFieldMap, iio_evt_parse_handler, (void *)&evt_ctx, nameMap); } - catch (std::exception & e) + catch (const std::exception & e) { - std::cerr << "Error info:" << e.what() << "\n"; - std::cerr << "The event configuration file (" << ev_file_name << ") cannot be loaded. Please verify the file. Exiting.\n"; - exit(EXIT_FAILURE); + std::cerr << "Error info:" << e.what() << std::endl; + std::cerr << "The event configuration file (" << ev_file_name << ") cannot be loaded. Please verify the file. Exiting." << std::endl; + return false; } + + return true; } bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) @@ -525,9 +527,7 @@ bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) return false; } - initializeIOStacksStructure(pmu_config.iios); - - setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap); + if (!initializeIOStacksStructure(pmu_config.iios)) return false; - return true; + return setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap); } diff --git a/src/pcm-iio-pmu.h b/src/pcm-iio-pmu.h index ec203278..25bc0ab9 100644 --- a/src/pcm-iio-pmu.h +++ b/src/pcm-iio-pmu.h @@ -117,7 +117,5 @@ class PcmIioDataCollector { void fillOpcodeFieldMapForPCIeEvents(map& opcodeFieldMap); -void setupPCIeEventContextAndNameMap( iio_evt_parse_context& evt_ctx, PCIeEventNameMap& nameMap); - bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config); diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 11068370..e936eb7a 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1644,16 +1644,19 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f } } -void initializeIOStacksStructure( std::vector& iios ) +bool initializeIOStacksStructure( std::vector& iios ) { - PCM * pcm = PCM::getInstance(); - auto mapping = IPlatformMapping::getPlatformMapping(pcm->getCPUFamilyModel(), pcm->getNumSockets(), pcm->getMaxNumOfIOStacks()); - if (!mapping) { - cerr << "Failed to discover pci tree: unknown platform" << endl; - exit(EXIT_FAILURE); + std::unique_ptr mapping = nullptr; + try + { + PCM * pcm = PCM::getInstance(); + mapping = IPlatformMapping::getPlatformMapping(pcm->getCPUFamilyModel(), pcm->getNumSockets(), pcm->getMaxNumOfIOStacks()); } - - if (!mapping->pciTreeDiscover(iios)) { - exit(EXIT_FAILURE); + catch (const std::exception & e) + { + std::cerr << "Error info:" << e.what() << std::endl; + return false; } + + return mapping->pciTreeDiscover(iios); } \ No newline at end of file diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index 5b6c1236..2e3e514d 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -47,4 +47,4 @@ class IPlatformMapping { virtual bool pciTreeDiscover(std::vector& iios); }; -void initializeIOStacksStructure( std::vector& iios ); \ No newline at end of file +bool initializeIOStacksStructure( std::vector& iios ); \ No newline at end of file From 5060f829300f0eb54f188a9f0901af13e22f87b9 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 02:19:26 -0700 Subject: [PATCH 36/54] Move initializeIOStacksStructure() to IPlatformMapping class --- src/pcm-iio-pmu.cpp | 2 +- src/pcm-iio-topology.cpp | 4 ++-- src/pcm-iio-topology.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index cf859c6c..274788e9 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -527,7 +527,7 @@ bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) return false; } - if (!initializeIOStacksStructure(pmu_config.iios)) return false; + if (!IPlatformMapping::initializeIOStacksStructure(pmu_config.iios)) return false; return setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap); } diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index e936eb7a..09b1f809 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1644,13 +1644,13 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f } } -bool initializeIOStacksStructure( std::vector& iios ) +bool IPlatformMapping::initializeIOStacksStructure( std::vector& iios ) { std::unique_ptr mapping = nullptr; try { PCM * pcm = PCM::getInstance(); - mapping = IPlatformMapping::getPlatformMapping(pcm->getCPUFamilyModel(), pcm->getNumSockets(), pcm->getMaxNumOfIOStacks()); + mapping = getPlatformMapping(pcm->getCPUFamilyModel(), pcm->getNumSockets(), pcm->getMaxNumOfIOStacks()); } catch (const std::exception & e) { diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index 2e3e514d..4fc103ec 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -42,9 +42,9 @@ class IPlatformMapping { IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} IPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) : m_sockets(sockets_count), m_model(cpu_model), m_stacks(stacks_count) {} - virtual ~IPlatformMapping() {}; + virtual ~IPlatformMapping() {} static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count); virtual bool pciTreeDiscover(std::vector& iios); -}; -bool initializeIOStacksStructure( std::vector& iios ); \ No newline at end of file + static bool initializeIOStacksStructure( std::vector& iios ); +}; From 4c4b6d1b19e905e17f83fbfbe3f6be8573a94f3e Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 02:37:11 -0700 Subject: [PATCH 37/54] Separate default implementation from IPlatformMapping interface class --- src/pcm-iio-topology.cpp | 59 ++++++++++++++++++++++------------------ src/pcm-iio-topology.h | 10 ++++--- 2 files changed, 39 insertions(+), 30 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 09b1f809..3c582adc 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -1573,12 +1573,38 @@ bool BirchStreamPlatform::stackProbe(int unit, const struct bdf &address, struct return false; } -const std::string generate_stack_str(const int unit) +class DefaultPlatformMapping : public IPlatformMapping { +protected: + const std::string stackIdToString(const int unit) + { + char buffer[64]; + snprintf(buffer, sizeof(buffer), "Stack %2d", unit); + return std::string(buffer); + } +public: + DefaultPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) + : IPlatformMapping(cpu_model, sockets_count, stacks_count) {} + + bool pciTreeDiscover(std::vector& iios) override; +}; + +bool DefaultPlatformMapping::pciTreeDiscover(std::vector& iios) { - static const std::string stack_str = "Stack "; - std::stringstream ss; - ss << stack_str << std::setw(2) << unit; - return ss.str(); + for (uint32_t socket = 0; socket < socketsCount(); socket++) + { + struct iio_stacks_on_socket iio_on_socket; + iio_on_socket.socket_id = socket; + for (uint32_t unit = 0; unit < stacksCount(); unit++) + { + struct iio_stack stack; + stack.iio_unit_id = unit; + stack.stack_name = stackIdToString(unit); + iio_on_socket.stacks.push_back(stack); + } + iios.push_back(iio_on_socket); + } + + return true; } void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int domain, int secondary, int subordinate) @@ -1602,25 +1628,6 @@ void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int d } } -bool IPlatformMapping::pciTreeDiscover(std::vector& iios) -{ - for (uint32_t socket = 0; socket < socketsCount(); socket++) - { - struct iio_stacks_on_socket iio_on_socket; - iio_on_socket.socket_id = socket; - for (uint32_t unit = 0; unit < stacksCount(); unit++) - { - struct iio_stack stack; - stack.iio_unit_id = unit; - stack.stack_name = generate_stack_str(unit); - iio_on_socket.stacks.push_back(stack); - } - iios.push_back(iio_on_socket); - } - - return true; -} - std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count, uint32_t stacks_count) { switch (cpu_family_model) { @@ -1640,11 +1647,11 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_f return std::make_unique(cpu_family_model, sockets_count); default: std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is provided" << std::endl; - return std::make_unique(cpu_family_model, sockets_count, stacks_count); + return std::make_unique(cpu_family_model, sockets_count, stacks_count); } } -bool IPlatformMapping::initializeIOStacksStructure( std::vector& iios ) +bool IPlatformMapping::initializeIOStacksStructure(std::vector& iios) { std::unique_ptr mapping = nullptr; try diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index 4fc103ec..c542b142 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -38,13 +38,15 @@ class IPlatformMapping { uint32_t socketsCount() const { return m_sockets; } uint32_t cpuId() const { return m_model; } uint32_t stacksCount() const { return m_stacks; } -public: + IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} IPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) : m_sockets(sockets_count), m_model(cpu_model), m_stacks(stacks_count) {} - virtual ~IPlatformMapping() {} + static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count); - virtual bool pciTreeDiscover(std::vector& iios); +public: + virtual ~IPlatformMapping() {} - static bool initializeIOStacksStructure( std::vector& iios ); + virtual bool pciTreeDiscover(std::vector& iios) = 0; + static bool initializeIOStacksStructure(std::vector& iios); }; From 8ac25146430e7590196ba7490cd3b67950891df7 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 02:43:14 -0700 Subject: [PATCH 38/54] Move pciTreeDiscover() to protected part --- src/pcm-iio-topology.cpp | 23 +++++++++++++---------- src/pcm-iio-topology.h | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 3c582adc..3e57e2bf 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -177,10 +177,11 @@ class PurleyPlatformMapping: public IPlatformMapping { "IIO Stack 4 - MCP0 ", "IIO Stack 5 - MCP1 " }; +protected: + bool pciTreeDiscover(std::vector& iios) override; public: PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} ~PurleyPlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; }; void PurleyPlatformMapping::getUboxBusNumbers(std::vector& ubox) @@ -351,6 +352,8 @@ class WhitleyPlatformMapping: public IPlatformMapping10Nm { { 4, 3 }, { 5, 4 } }; +protected: + bool pciTreeDiscover(std::vector& iios) override; public: WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count), icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), @@ -359,7 +362,6 @@ class WhitleyPlatformMapping: public IPlatformMapping10Nm { { } ~WhitleyPlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; }; bool WhitleyPlatformMapping::pciTreeDiscover(std::vector& iios) @@ -496,10 +498,11 @@ class JacobsvillePlatformMapping: public IPlatformMapping10Nm { "IIO Stack 3 - HQM ", "IIO Stack 4 - PCIe " }; +protected: + bool pciTreeDiscover(std::vector& iios) override; public: JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} ~JacobsvillePlatformMapping() = default; - bool pciTreeDiscover(std::vector& iios) override; bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); }; @@ -837,6 +840,8 @@ class EagleStreamPlatformMapping: public IPlatformMapping {estype::esSprMcc, spr_mcc_sad_to_pmu_id_mapping}, {estype::esEmrXcc, emr_sad_to_pmu_id_mapping }, }; +protected: + bool pciTreeDiscover(std::vector& iios) override; public: EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {} ~EagleStreamPlatformMapping() = default; @@ -845,8 +850,6 @@ class EagleStreamPlatformMapping: public IPlatformMapping const std::uint32_t kXccChop = 0b11; const std::uint32_t kMccChop = 0b01; - - bool pciTreeDiscover(std::vector& iios) override; }; bool EagleStreamPlatformMapping::setChopValue() @@ -1133,10 +1136,11 @@ class LoganvillePlatform: public IPlatformMapping10Nm { { GRR_DLB_SAD_ID, GRR_DLB_PMON_ID }, { GRR_NIS_QAT_SAD_ID, GRR_NIS_QAT_PMON_ID }, }; +protected: + bool pciTreeDiscover(std::vector& iios) override; public: LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} ~LoganvillePlatform() = default; - bool pciTreeDiscover(std::vector& iios) override; }; bool LoganvillePlatform::loganvillePchDsaPciStackProbe(struct iio_stacks_on_socket& iio_on_socket, int root_bus, int stack_pmon_id) @@ -1301,11 +1305,10 @@ class Xeon6thNextGenPlatform: public IPlatformMapping { bool getRootBuses(std::map> &root_buses); protected: virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; + virtual bool pciTreeDiscover(std::vector& iios) override; public: Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} virtual ~Xeon6thNextGenPlatform() = default; - - virtual bool pciTreeDiscover(std::vector& iios) override; }; bool Xeon6thNextGenPlatform::getRootBuses(std::map> &root_buses) @@ -1581,11 +1584,11 @@ class DefaultPlatformMapping : public IPlatformMapping { snprintf(buffer, sizeof(buffer), "Stack %2d", unit); return std::string(buffer); } + + bool pciTreeDiscover(std::vector& iios) override; public: DefaultPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) : IPlatformMapping(cpu_model, sockets_count, stacks_count) {} - - bool pciTreeDiscover(std::vector& iios) override; }; bool DefaultPlatformMapping::pciTreeDiscover(std::vector& iios) diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index c542b142..4b496385 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -43,10 +43,10 @@ class IPlatformMapping { IPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) : m_sockets(sockets_count), m_model(cpu_model), m_stacks(stacks_count) {} + virtual bool pciTreeDiscover(std::vector& iios) = 0; static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count); public: virtual ~IPlatformMapping() {} - virtual bool pciTreeDiscover(std::vector& iios) = 0; static bool initializeIOStacksStructure(std::vector& iios); }; From d1750b03a80a458d3227cb4590ed7d6db39c543f Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 02:52:07 -0700 Subject: [PATCH 39/54] Pass CPU family model, sockets/stacks count as input parameter --- src/pcm-iio-pmu.cpp | 2 +- src/pcm-iio-topology.cpp | 45 ++++++++++++++++++++-------------------- src/pcm-iio-topology.h | 10 ++++----- 3 files changed, 28 insertions(+), 29 deletions(-) diff --git a/src/pcm-iio-pmu.cpp b/src/pcm-iio-pmu.cpp index 274788e9..9b0dd49d 100644 --- a/src/pcm-iio-pmu.cpp +++ b/src/pcm-iio-pmu.cpp @@ -527,7 +527,7 @@ bool initializePCIeBWCounters(struct pcm_iio_pmu_config& pmu_config) return false; } - if (!IPlatformMapping::initializeIOStacksStructure(pmu_config.iios)) return false; + if (!IPlatformMapping::initializeIOStacksStructure(pmu_config.iios, m->getCPUFamilyModel(), m->getNumSockets(), m->getMaxNumOfIOStacks())) return false; return setupPCIeEventContextAndNameMap(pmu_config.evt_ctx, pmu_config.pcieEventNameMap); } diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 3e57e2bf..2851073d 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -180,7 +180,7 @@ class PurleyPlatformMapping: public IPlatformMapping { protected: bool pciTreeDiscover(std::vector& iios) override; public: - PurleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + PurleyPlatformMapping(int model, uint32_t sockets) : IPlatformMapping(model, sockets) {} ~PurleyPlatformMapping() = default; }; @@ -269,7 +269,7 @@ bool PurleyPlatformMapping::pciTreeDiscover(std::vector& sad_id_bus_map); }; @@ -355,7 +355,7 @@ class WhitleyPlatformMapping: public IPlatformMapping10Nm { protected: bool pciTreeDiscover(std::vector& iios) override; public: - WhitleyPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count), + WhitleyPlatformMapping(int model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets), icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping), iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names) @@ -501,7 +501,7 @@ class JacobsvillePlatformMapping: public IPlatformMapping10Nm { protected: bool pciTreeDiscover(std::vector& iios) override; public: - JacobsvillePlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} + JacobsvillePlatformMapping(int model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {} ~JacobsvillePlatformMapping() = default; bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); }; @@ -843,7 +843,7 @@ class EagleStreamPlatformMapping: public IPlatformMapping protected: bool pciTreeDiscover(std::vector& iios) override; public: - EagleStreamPlatformMapping(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count), m_chop(0), m_es_type(estype::esInvalid) {} + EagleStreamPlatformMapping(int model, uint32_t sockets) : IPlatformMapping(model, sockets), m_chop(0), m_es_type(estype::esInvalid) {} ~EagleStreamPlatformMapping() = default; bool setChopValue(); bool isXccPlatform() const { return m_chop == kXccChop; } @@ -1139,7 +1139,7 @@ class LoganvillePlatform: public IPlatformMapping10Nm { protected: bool pciTreeDiscover(std::vector& iios) override; public: - LoganvillePlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping10Nm(cpu_model, sockets_count) {} + LoganvillePlatform(int model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {} ~LoganvillePlatform() = default; }; @@ -1307,7 +1307,7 @@ class Xeon6thNextGenPlatform: public IPlatformMapping { virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; virtual bool pciTreeDiscover(std::vector& iios) override; public: - Xeon6thNextGenPlatform(int cpu_model, uint32_t sockets_count) : IPlatformMapping(cpu_model, sockets_count) {} + Xeon6thNextGenPlatform(int model, uint32_t sockets) : IPlatformMapping(model, sockets) {} virtual ~Xeon6thNextGenPlatform() = default; }; @@ -1439,7 +1439,7 @@ class BirchStreamPlatform: public Xeon6thNextGenPlatform { protected: bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; public: - BirchStreamPlatform(int cpu_model, uint32_t sockets_count) : Xeon6thNextGenPlatform(cpu_model, sockets_count) {} + BirchStreamPlatform(int model, uint32_t sockets) : Xeon6thNextGenPlatform(model, sockets) {} ~BirchStreamPlatform() = default; }; @@ -1587,8 +1587,8 @@ class DefaultPlatformMapping : public IPlatformMapping { bool pciTreeDiscover(std::vector& iios) override; public: - DefaultPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) - : IPlatformMapping(cpu_model, sockets_count, stacks_count) {} + DefaultPlatformMapping(int model, uint32_t sockets, uint32_t stacks) + : IPlatformMapping(model, sockets, stacks) {} }; bool DefaultPlatformMapping::pciTreeDiscover(std::vector& iios) @@ -1631,36 +1631,35 @@ void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int d } } -std::unique_ptr IPlatformMapping::getPlatformMapping(int cpu_family_model, uint32_t sockets_count, uint32_t stacks_count) +std::unique_ptr IPlatformMapping::getPlatformMapping(int model, uint32_t sockets, uint32_t stacks) { - switch (cpu_family_model) { + switch (model) { case PCM::SKX: - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(model, sockets); case PCM::ICX: - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(model, sockets); case PCM::SNOWRIDGE: - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(model, sockets); case PCM::SPR: case PCM::EMR: - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(model, sockets); case PCM::GRR: - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(model, sockets); case PCM::SRF: case PCM::GNR: - return std::make_unique(cpu_family_model, sockets_count); + return std::make_unique(model, sockets); default: - std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(cpu_family_model) << " is provided" << std::endl; - return std::make_unique(cpu_family_model, sockets_count, stacks_count); + std::cerr << "Warning: Only initial support (without attribution to PCIe devices) for " << PCM::cpuFamilyModelToUArchCodename(model) << " is provided" << std::endl; + return std::make_unique(model, sockets, stacks); } } -bool IPlatformMapping::initializeIOStacksStructure(std::vector& iios) +bool IPlatformMapping::initializeIOStacksStructure(std::vector& iios, int model, uint32_t sockets, uint32_t stacks) { std::unique_ptr mapping = nullptr; try { - PCM * pcm = PCM::getInstance(); - mapping = getPlatformMapping(pcm->getCPUFamilyModel(), pcm->getNumSockets(), pcm->getMaxNumOfIOStacks()); + mapping = getPlatformMapping(model, sockets, stacks); } catch (const std::exception & e) { diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index 4b496385..acf20052 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -39,14 +39,14 @@ class IPlatformMapping { uint32_t cpuId() const { return m_model; } uint32_t stacksCount() const { return m_stacks; } - IPlatformMapping(int cpu_model, uint32_t sockets_count) : m_sockets(sockets_count), m_model(cpu_model) {} - IPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count) : - m_sockets(sockets_count), m_model(cpu_model), m_stacks(stacks_count) {} + IPlatformMapping(int model, uint32_t sockets) : m_sockets(sockets), m_model(model) {} + IPlatformMapping(int model, uint32_t sockets, uint32_t stacks) : + m_sockets(sockets), m_model(model), m_stacks(stacks) {} virtual bool pciTreeDiscover(std::vector& iios) = 0; - static std::unique_ptr getPlatformMapping(int cpu_model, uint32_t sockets_count, uint32_t stacks_count); + static std::unique_ptr getPlatformMapping(int model, uint32_t sockets, uint32_t stacks); public: virtual ~IPlatformMapping() {} - static bool initializeIOStacksStructure(std::vector& iios); + static bool initializeIOStacksStructure(std::vector& iios, int model, uint32_t sockets, uint32_t stacks); }; From a597489ee94ccadb7bdb04f363336c2a2bff40e8 Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 03:03:24 -0700 Subject: [PATCH 40/54] Align type for model ID --- src/pcm-iio-topology.cpp | 24 ++++++++++++------------ src/pcm-iio-topology.h | 8 ++++---- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/pcm-iio-topology.cpp b/src/pcm-iio-topology.cpp index 2851073d..f53df228 100644 --- a/src/pcm-iio-topology.cpp +++ b/src/pcm-iio-topology.cpp @@ -180,7 +180,7 @@ class PurleyPlatformMapping: public IPlatformMapping { protected: bool pciTreeDiscover(std::vector& iios) override; public: - PurleyPlatformMapping(int model, uint32_t sockets) : IPlatformMapping(model, sockets) {} + PurleyPlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets) {} ~PurleyPlatformMapping() = default; }; @@ -269,7 +269,7 @@ bool PurleyPlatformMapping::pciTreeDiscover(std::vector& sad_id_bus_map); }; @@ -355,8 +355,8 @@ class WhitleyPlatformMapping: public IPlatformMapping10Nm { protected: bool pciTreeDiscover(std::vector& iios) override; public: - WhitleyPlatformMapping(int model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets), - icx_d(PCM::getInstance()->getCPUFamilyModelFromCPUID() == PCM::ICX_D), + WhitleyPlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets), + icx_d(model == PCM::ICX_D), sad_to_pmu_id_mapping(icx_d ? icx_d_sad_to_pmu_id_mapping : icx_sad_to_pmu_id_mapping), iio_stack_names(icx_d ? icx_d_iio_stack_names : icx_iio_stack_names) { @@ -501,7 +501,7 @@ class JacobsvillePlatformMapping: public IPlatformMapping10Nm { protected: bool pciTreeDiscover(std::vector& iios) override; public: - JacobsvillePlatformMapping(int model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {} + JacobsvillePlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {} ~JacobsvillePlatformMapping() = default; bool JacobsvilleAccelerators(const std::pair& sad_id_bus_pair, struct iio_stack& stack); }; @@ -843,7 +843,7 @@ class EagleStreamPlatformMapping: public IPlatformMapping protected: bool pciTreeDiscover(std::vector& iios) override; public: - EagleStreamPlatformMapping(int model, uint32_t sockets) : IPlatformMapping(model, sockets), m_chop(0), m_es_type(estype::esInvalid) {} + EagleStreamPlatformMapping(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets), m_chop(0), m_es_type(estype::esInvalid) {} ~EagleStreamPlatformMapping() = default; bool setChopValue(); bool isXccPlatform() const { return m_chop == kXccChop; } @@ -1139,7 +1139,7 @@ class LoganvillePlatform: public IPlatformMapping10Nm { protected: bool pciTreeDiscover(std::vector& iios) override; public: - LoganvillePlatform(int model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {} + LoganvillePlatform(uint32_t model, uint32_t sockets) : IPlatformMapping10Nm(model, sockets) {} ~LoganvillePlatform() = default; }; @@ -1307,7 +1307,7 @@ class Xeon6thNextGenPlatform: public IPlatformMapping { virtual bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) = 0; virtual bool pciTreeDiscover(std::vector& iios) override; public: - Xeon6thNextGenPlatform(int model, uint32_t sockets) : IPlatformMapping(model, sockets) {} + Xeon6thNextGenPlatform(uint32_t model, uint32_t sockets) : IPlatformMapping(model, sockets) {} virtual ~Xeon6thNextGenPlatform() = default; }; @@ -1439,7 +1439,7 @@ class BirchStreamPlatform: public Xeon6thNextGenPlatform { protected: bool stackProbe(int unit, const struct bdf &address, struct iio_stacks_on_socket &iio_on_socket) override; public: - BirchStreamPlatform(int model, uint32_t sockets) : Xeon6thNextGenPlatform(model, sockets) {} + BirchStreamPlatform(uint32_t model, uint32_t sockets) : Xeon6thNextGenPlatform(model, sockets) {} ~BirchStreamPlatform() = default; }; @@ -1587,7 +1587,7 @@ class DefaultPlatformMapping : public IPlatformMapping { bool pciTreeDiscover(std::vector& iios) override; public: - DefaultPlatformMapping(int model, uint32_t sockets, uint32_t stacks) + DefaultPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks) : IPlatformMapping(model, sockets, stacks) {} }; @@ -1631,7 +1631,7 @@ void IPlatformMapping::probeDeviceRange(std::vector &pci_devs, int d } } -std::unique_ptr IPlatformMapping::getPlatformMapping(int model, uint32_t sockets, uint32_t stacks) +std::unique_ptr IPlatformMapping::getPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks) { switch (model) { case PCM::SKX: @@ -1654,7 +1654,7 @@ std::unique_ptr IPlatformMapping::getPlatformMapping(int model } } -bool IPlatformMapping::initializeIOStacksStructure(std::vector& iios, int model, uint32_t sockets, uint32_t stacks) +bool IPlatformMapping::initializeIOStacksStructure(std::vector& iios, uint32_t model, uint32_t sockets, uint32_t stacks) { std::unique_ptr mapping = nullptr; try diff --git a/src/pcm-iio-topology.h b/src/pcm-iio-topology.h index acf20052..fa2cd425 100644 --- a/src/pcm-iio-topology.h +++ b/src/pcm-iio-topology.h @@ -39,14 +39,14 @@ class IPlatformMapping { uint32_t cpuId() const { return m_model; } uint32_t stacksCount() const { return m_stacks; } - IPlatformMapping(int model, uint32_t sockets) : m_sockets(sockets), m_model(model) {} - IPlatformMapping(int model, uint32_t sockets, uint32_t stacks) : + IPlatformMapping(uint32_t model, uint32_t sockets) : m_sockets(sockets), m_model(model) {} + IPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks) : m_sockets(sockets), m_model(model), m_stacks(stacks) {} virtual bool pciTreeDiscover(std::vector& iios) = 0; - static std::unique_ptr getPlatformMapping(int model, uint32_t sockets, uint32_t stacks); + static std::unique_ptr getPlatformMapping(uint32_t model, uint32_t sockets, uint32_t stacks); public: virtual ~IPlatformMapping() {} - static bool initializeIOStacksStructure(std::vector& iios, int model, uint32_t sockets, uint32_t stacks); + static bool initializeIOStacksStructure(std::vector& iios, uint32_t model, uint32_t sockets, uint32_t stacks); }; From 9f84781069f076173839acbbbad45b7a4d2e95ee Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 03:44:36 -0700 Subject: [PATCH 41/54] Add utest for DefaultPlatformMapping --- tests/utests/pcm-iio-utest.cpp | 37 +++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp index ed1fd16a..cf7abd2d 100644 --- a/tests/utests/pcm-iio-utest.cpp +++ b/tests/utests/pcm-iio-utest.cpp @@ -9,6 +9,7 @@ #include #include "utils.h" #include "pcm-iio-pmu.h" +#include "pcm-iio-topology.h" using namespace pcm; @@ -214,4 +215,38 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) EXPECT_TRUE(foundEvents[i]) << "Expected event " << expectedEvents[i].hname << "/" << expectedEvents[i].vname << " was not loaded"; } -} \ No newline at end of file +} + +class PcmIioTopologyTestBase: public ::testing::Test +{ +}; + +TEST_F(PcmIioTopologyTestBase, DefaultTopologyTest) +{ + // Use invalid value to trigger default platform mapping + const uint32_t model = PCM::END_OF_MODEL_LIST; + const uint32_t sockets = 2; + const uint32_t stacks = 12; + + const std::vector expectedStackNames = + { + "Stack 0", "Stack 1", "Stack 2", + "Stack 3", "Stack 4", "Stack 5", + "Stack 6", "Stack 7", "Stack 8", + "Stack 9", "Stack 10", "Stack 11" + }; + + std::vector iios; + ASSERT_TRUE(IPlatformMapping::initializeIOStacksStructure(iios, model, sockets, stacks)) << "Failed to initialize IIO stacks structure"; + + ASSERT_EQ(iios.size(), sockets) << "Number of sockets mismatch"; + for (const auto &iio_on_socket : iios) + { + ASSERT_EQ(iio_on_socket.stacks.size(), stacks) << "Number of stacks per socket mismatch"; + for (uint32_t unit = 0; unit < stacks; unit++) + { + ASSERT_EQ(iio_on_socket.stacks[unit].iio_unit_id, unit) << "Stack ID mismatch"; + EXPECT_EQ(iio_on_socket.stacks[unit].stack_name, expectedStackNames[unit]) << "Stack name mismatch"; + } + } +} From e1be67579d26e413be0a71ef7d4d62b2b565db1a Mon Sep 17 00:00:00 2001 From: Alexander Antonov Date: Tue, 14 Oct 2025 04:03:00 -0700 Subject: [PATCH 42/54] Remove useless comments from pcm-iio-utest file --- tests/utests/pcm-iio-utest.cpp | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/tests/utests/pcm-iio-utest.cpp b/tests/utests/pcm-iio-utest.cpp index cf7abd2d..76b6fe53 100644 --- a/tests/utests/pcm-iio-utest.cpp +++ b/tests/utests/pcm-iio-utest.cpp @@ -41,18 +41,15 @@ struct ExpectedEvent { bool operator==(const struct iio_counter& actual) const { - // Check if actual counter matches this expected event bool basic_match = ctr == actual.idx && hname == actual.h_event_name && vname == actual.v_event_name && multiplier == actual.multiplier; - // Check if ev_sel and umask were properly encoded in CCR bool ev_sel_match = (actual.ccr & 0xFF) == ev_sel; bool umask_match = ((actual.ccr >> 8) & 0xFF) == umask; - // Check ch_mask and fc_mask fields bool ch_mask_match = (((actual.ccr >> 36) & 0xFFF) == ch_mask); bool fc_mask_match = (((actual.ccr >> 48) & 0x7) == fc_mask); @@ -68,12 +65,10 @@ TEST_F(LoadEventsTest, TestLoadEventsAlternateVersion) evt_ctx.cpu_family_model = PCM_CPU_FAMILY_MODEL(6, 174); - // Test the alternate version of load_events without nameMap ASSERT_NO_THROW({ load_events(eventFile, opcodeFieldMap, iio_evt_parse_handler, &evt_ctx); }); - // Verify events were loaded ASSERT_FALSE(evt_ctx.ctrs.empty()) << "No events were loaded from the file"; // Verify at least one counter was properly initialized @@ -89,7 +84,6 @@ TEST_F(LoadEventsTest, TestLoadEventsAlternateVersion) TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) { - // 1. Define expected events directly (hardcoded values from opCode-6-174.txt) std::vector expectedEvents = { // IB write events {0, 0x83, 0x1, 1, 0x7, 4, "IB write", "Part0", CounterType::iio}, @@ -144,17 +138,14 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) evt_ctx.cpu_family_model = PCM_CPU_FAMILY_MODEL(6, 174); - // 2. Load events using the existing function evt_ctx.ctrs.clear(); ASSERT_NO_THROW({ load_events("opCode-6-174.txt", opcodeFieldMap, iio_evt_parse_handler, &evt_ctx); }); - // 3. Verify that all loaded events match the expected events ASSERT_EQ(expectedEvents.size(), evt_ctx.ctrs.size()) << "Number of loaded events doesn't match expected count"; - // Create a copy of expected events that we'll mark as found std::vector foundEvents(expectedEvents.size(), false); // For each loaded event, find and verify the matching expected event @@ -165,7 +156,6 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) foundEvents[i] = true; found = true; - // Additional verification of specific fields EXPECT_EQ(expectedEvents[i].ctr, actualEvt.idx) << "Counter index mismatch for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name; @@ -178,7 +168,6 @@ TEST_F(LoadEventsTest, TestVerifyAllFieldsFromOpcodeFile) << "UMASK mismatch for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name; - // Checks for ch_mask and fc_mask EXPECT_EQ(expectedEvents[i].ch_mask, ((actualEvt.ccr >> 36) & 0xFFF)) << "CH_MASK mismatch for " << actualEvt.h_event_name << "/" << actualEvt.v_event_name; From a63adc8417f33fc08d02b170d8658667a25152f0 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Wed, 29 Oct 2025 13:04:17 +0000 Subject: [PATCH 43/54] Add _codeql_build_dir to .gitignore to exclude build artifacts Co-authored-by: rdementi <25432609+rdementi@users.noreply.github.com> --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 86e6584c..8aade9ba 100644 --- a/.gitignore +++ b/.gitignore @@ -34,3 +34,4 @@ latex/ build src/simdjson .vscode/ +_codeql_build_dir/ From f414c5ea99b1c894f0d281f3c9e77456ff3052eb Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Thu, 30 Oct 2025 10:31:52 +0000 Subject: [PATCH 44/54] Implement input validation for read_number function Co-authored-by: rdementi <25432609+rdementi@users.noreply.github.com> --- src/utils.cpp | 71 ++++++++++++++++++++++++++++-- tests/utests/CMakeLists.txt | 10 +++++ tests/utests/read-number-utest.cpp | 61 +++++++++++++++++++++++++ 3 files changed, 139 insertions(+), 3 deletions(-) create mode 100644 tests/utests/read-number-utest.cpp diff --git a/src/utils.cpp b/src/utils.cpp index 915bf5f0..2b5b537b 100644 --- a/src/utils.cpp +++ b/src/utils.cpp @@ -813,10 +813,75 @@ std::vector split(const std::string & str, const char delim) uint64 read_number(const char* str) { - std::istringstream stream(str); - if (strstr(str, "x")) stream >> std::hex; + if (str == nullptr || *str == '\0') + { + throw std::invalid_argument("Input string is null or empty"); + } + + std::string input(str); + // Trim leading and trailing whitespace + size_t start = input.find_first_not_of(" \t\n\r"); + size_t end = input.find_last_not_of(" \t\n\r"); + + if (start == std::string::npos) + { + throw std::invalid_argument("Input string contains only whitespace"); + } + + input = input.substr(start, end - start + 1); + + std::istringstream stream(input); uint64 result = 0; - stream >> result; + + // Check if the input is hexadecimal (starts with 0x or 0X) + if (input.length() >= 2 && input[0] == '0' && (input[1] == 'x' || input[1] == 'X')) + { + if (input.length() == 2) + { + throw std::invalid_argument("Invalid hexadecimal number: no digits after 0x"); + } + + // Validate that all characters after 0x are valid hex digits + for (size_t i = 2; i < input.length(); ++i) + { + char c = input[i]; + if (!((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F'))) + { + throw std::invalid_argument("Invalid hexadecimal number: contains non-hex characters"); + } + } + + stream >> std::hex >> result; + } + else + { + // Validate that all characters are valid decimal digits + for (size_t i = 0; i < input.length(); ++i) + { + char c = input[i]; + if (!(c >= '0' && c <= '9')) + { + throw std::invalid_argument("Invalid decimal number: contains non-digit characters"); + } + } + + stream >> result; + } + + // Check if the stream operation failed or if there are remaining characters + if (stream.fail()) + { + throw std::invalid_argument("Failed to parse number from input string"); + } + + // Check if there are any remaining characters in the stream + std::string remaining; + stream >> remaining; + if (!remaining.empty()) + { + throw std::invalid_argument("Input string contains extra characters after the number"); + } + return result; } diff --git a/tests/utests/CMakeLists.txt b/tests/utests/CMakeLists.txt index a0ba54a3..49fbc781 100644 --- a/tests/utests/CMakeLists.txt +++ b/tests/utests/CMakeLists.txt @@ -16,6 +16,7 @@ endif() file(GLOB LSPCI_TEST_FILES lspci-utest.cpp ${CMAKE_SOURCE_DIR}/src/lspci.cpp) file(GLOB PCM_IIO_TEST_FILES pcm-iio-utest.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-pmu.cpp ${CMAKE_SOURCE_DIR}/src/pcm-iio-topology.cpp) +file(GLOB READ_NUMBER_TEST_FILES read-number-utest.cpp) if(APPLE) set(LIBS PcmMsr Threads::Threads PCM_STATIC) @@ -25,6 +26,7 @@ endif() add_executable(lspci-utest ${LSPCI_TEST_FILES}) add_executable(pcm-iio-utest ${PCM_IIO_TEST_FILES}) +add_executable(read-number-utest ${READ_NUMBER_TEST_FILES}) configure_file( ${CMAKE_SOURCE_DIR}/src/opCode-6-174.txt @@ -46,6 +48,14 @@ target_link_libraries( ${LIBS} ) +target_link_libraries( + read-number-utest + GTest::gtest_main + GTest::gmock_main + ${LIBS} +) + include(GoogleTest) gtest_discover_tests(lspci-utest) gtest_discover_tests(pcm-iio-utest) +gtest_discover_tests(read-number-utest) diff --git a/tests/utests/read-number-utest.cpp b/tests/utests/read-number-utest.cpp new file mode 100644 index 00000000..3f559f9c --- /dev/null +++ b/tests/utests/read-number-utest.cpp @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2009-2025, Intel Corporation + +#include "utils.h" +#include +#include + +using namespace pcm; + +// Test valid decimal numbers +TEST(ReadNumberTest, ValidDecimalNumbers) +{ + EXPECT_EQ(read_number("0"), 0ULL); + EXPECT_EQ(read_number("123"), 123ULL); + EXPECT_EQ(read_number("456789"), 456789ULL); + EXPECT_EQ(read_number("18446744073709551615"), 18446744073709551615ULL); // max uint64 +} + +// Test valid hexadecimal numbers +TEST(ReadNumberTest, ValidHexadecimalNumbers) +{ + EXPECT_EQ(read_number("0x0"), 0ULL); + EXPECT_EQ(read_number("0x10"), 16ULL); + EXPECT_EQ(read_number("0xFF"), 255ULL); + EXPECT_EQ(read_number("0xABCD"), 43981ULL); + EXPECT_EQ(read_number("0xFFFFFFFFFFFFFFFF"), 18446744073709551615ULL); // max uint64 + EXPECT_EQ(read_number("0Xabcd"), 43981ULL); // capital X +} + +// Test invalid inputs - should throw exceptions +TEST(ReadNumberTest, InvalidInputsThrowException) +{ + EXPECT_THROW(read_number(""), std::invalid_argument); + EXPECT_THROW(read_number("abc"), std::invalid_argument); + EXPECT_THROW(read_number("12abc"), std::invalid_argument); + EXPECT_THROW(read_number("0xGHI"), std::invalid_argument); + EXPECT_THROW(read_number("not a number"), std::invalid_argument); + EXPECT_THROW(read_number("123.456"), std::invalid_argument); + EXPECT_THROW(read_number("-123"), std::invalid_argument); + EXPECT_THROW(read_number("0x"), std::invalid_argument); + EXPECT_THROW(read_number("x123"), std::invalid_argument); + EXPECT_THROW(read_number(" "), std::invalid_argument); +} + +// Test edge cases with whitespace +TEST(ReadNumberTest, WhitespaceHandling) +{ + // Leading/trailing whitespace should be acceptable + EXPECT_EQ(read_number(" 123"), 123ULL); + EXPECT_EQ(read_number("123 "), 123ULL); + EXPECT_EQ(read_number(" 123 "), 123ULL); + EXPECT_EQ(read_number(" 0x10 "), 16ULL); +} + +// Test numbers with extra characters should throw +TEST(ReadNumberTest, ExtraCharactersThrowException) +{ + EXPECT_THROW(read_number("123abc"), std::invalid_argument); + EXPECT_THROW(read_number("0x10ZZ"), std::invalid_argument); + EXPECT_THROW(read_number("12 34"), std::invalid_argument); +} From bf88f24f7a2f3c15b5829ace7c18a4de68cca3fc Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Thu, 23 Oct 2025 15:02:41 +0200 Subject: [PATCH 45/54] try to use ARL code for PTL cpu model 204 Change-Id: I0aa944142eed2731cd5e6834c3c218058809ece8 --- src/cpucounters.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpucounters.h b/src/cpucounters.h index 173a0ce2..b6c02251 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1967,7 +1967,7 @@ class PCM_API PCM MTL = PCM_CPU_FAMILY_MODEL(6, 0xAA), LNL = PCM_CPU_FAMILY_MODEL(6, 0xBD), ARL = PCM_CPU_FAMILY_MODEL(6, 197), - ARL_1 = PCM_CPU_FAMILY_MODEL(6, 198), + ARL_1 = PCM_CPU_FAMILY_MODEL(6, 204), BDX = PCM_CPU_FAMILY_MODEL(6, 79), KNL = PCM_CPU_FAMILY_MODEL(6, 87), SKL = PCM_CPU_FAMILY_MODEL(6, 94), From 56e11eb6c70e845f01b2c9f4021feb68f52ead87 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 29 Oct 2025 14:41:42 +0100 Subject: [PATCH 46/54] Revert "try to use ARL code for PTL cpu model 204" This reverts commit d8cd1bf5b06d218f019f5f2d91f5d2a6b1596a45. --- src/cpucounters.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpucounters.h b/src/cpucounters.h index b6c02251..173a0ce2 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1967,7 +1967,7 @@ class PCM_API PCM MTL = PCM_CPU_FAMILY_MODEL(6, 0xAA), LNL = PCM_CPU_FAMILY_MODEL(6, 0xBD), ARL = PCM_CPU_FAMILY_MODEL(6, 197), - ARL_1 = PCM_CPU_FAMILY_MODEL(6, 204), + ARL_1 = PCM_CPU_FAMILY_MODEL(6, 198), BDX = PCM_CPU_FAMILY_MODEL(6, 79), KNL = PCM_CPU_FAMILY_MODEL(6, 87), SKL = PCM_CPU_FAMILY_MODEL(6, 94), From 2f3378c5c2d35ae6e8e336c6f79fef216bf4bd52 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Wed, 29 Oct 2025 12:55:42 +0000 Subject: [PATCH 47/54] Add PTL (Panther Lake) CPU support with family model 6, 204 Implemented by duplicating all ARL patterns: - Added PTL enum definition (PCM_CPU_FAMILY_MODEL(6, 204)) - Added 8 case PTL statements across cpucounters.h and cpucounters.cpp - Added 7 conditional checks for PTL in both files - Added PTL to CPU name mapping ("Panther Lake") Co-authored-by: rdementi <25432609+rdementi@users.noreply.github.com> --- src/cpucounters.cpp | 9 +++++++++ src/cpucounters.h | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 5c62f4de..b45b5e78 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -717,6 +717,7 @@ void PCM::initCStateSupportTables() case MTL: case LNL: case ARL: + case PTL: case SNOWRIDGE: case ELKHART_LAKE: case JASPER_LAKE: @@ -798,6 +799,7 @@ void PCM::initCStateSupportTables() case MTL: case LNL: case ARL: + case PTL: case SNOWRIDGE: case ELKHART_LAKE: case JASPER_LAKE: @@ -1695,6 +1697,7 @@ bool PCM::detectNominalFrequency() || cpu_family_model == MTL || cpu_family_model == LNL || cpu_family_model == ARL + || cpu_family_model == PTL || cpu_family_model == SKX || cpu_family_model == ICX || cpu_family_model == SPR @@ -1974,6 +1977,7 @@ void PCM::initUncoreObjects() case MTL: // TGLClientBW works fine for MTL case LNL: // TGLClientBW works fine for LNL case ARL: // TGLClientBW works fine for ARL + case PTL: // TGLClientBW works fine for PTL clientBW = std::make_shared(); break; /* Disabled since ADLClientBW requires 2x multiplier for BW on top @@ -3417,6 +3421,7 @@ bool PCM::isCPUModelSupported(const int model_) || model_ == MTL || model_ == LNL || model_ == ARL + || model_ == PTL || model_ == SKX || model_ == ICX || model_ == SPR @@ -3599,6 +3604,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter || cpu_family_model == MTL || cpu_family_model == LNL || cpu_family_model == ARL + || cpu_family_model == PTL )) { canUsePerf = false; @@ -3688,6 +3694,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter case MTL: case LNL: case ARL: + case PTL: LLCArchEventInit(hybridAtomEventDesc); hybridAtomEventDesc[2].event_number = SKL_MEM_LOAD_RETIRED_L2_MISS_EVTNR; hybridAtomEventDesc[2].umask_value = SKL_MEM_LOAD_RETIRED_L2_MISS_UMASK; @@ -5063,6 +5070,8 @@ const char * PCM::cpuFamilyModelToUArchCodename(const int32 cpu_family_model_, c return "Lunar Lake"; case ARL: return "Arrow Lake"; + case PTL: + return "Panther Lake"; case SKX: if (cpu_stepping_ < 0) { diff --git a/src/cpucounters.h b/src/cpucounters.h index 173a0ce2..0ca20ddb 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1690,6 +1690,7 @@ class PCM_API PCM case MTL: case LNL: case ARL: + case PTL: if (topology[coreID].core_type == TopologyEntry::Atom) { return eCoreOCREvent; @@ -1709,6 +1710,7 @@ class PCM_API PCM case MTL: case LNL: case ARL: + case PTL: useGLCOCREvent = true; break; @@ -1968,6 +1970,7 @@ class PCM_API PCM LNL = PCM_CPU_FAMILY_MODEL(6, 0xBD), ARL = PCM_CPU_FAMILY_MODEL(6, 197), ARL_1 = PCM_CPU_FAMILY_MODEL(6, 198), + PTL = PCM_CPU_FAMILY_MODEL(6, 204), BDX = PCM_CPU_FAMILY_MODEL(6, 79), KNL = PCM_CPU_FAMILY_MODEL(6, 87), SKL = PCM_CPU_FAMILY_MODEL(6, 94), @@ -2209,6 +2212,7 @@ class PCM_API PCM return 6; case LNL: case ARL: + case PTL: return 12; case SNOWRIDGE: case ELKHART_LAKE: @@ -2565,6 +2569,7 @@ class PCM_API PCM || cpu_family_model == PCM::MTL || cpu_family_model == PCM::LNL || cpu_family_model == PCM::ARL + || cpu_family_model == PCM::PTL || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR @@ -2605,6 +2610,7 @@ class PCM_API PCM || cpu_family_model == PCM::MTL || cpu_family_model == PCM::LNL || cpu_family_model == PCM::ARL + || cpu_family_model == PCM::PTL || cpu_family_model == PCM::SPR || cpu_family_model == PCM::EMR || cpu_family_model == PCM::GNR @@ -2905,6 +2911,7 @@ class PCM_API PCM || cpu_family_model == MTL || cpu_family_model == LNL || cpu_family_model == ARL + || cpu_family_model == PTL || useSKLPath() ; } @@ -4470,6 +4477,7 @@ uint64 getL2CacheMisses(const CounterStateType & before, const CounterStateType || cpu_family_model == PCM::MTL || cpu_family_model == PCM::LNL || cpu_family_model == PCM::ARL + || cpu_family_model == PCM::PTL ) { return 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defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_C) +# define COMPILER_ID "SunPro" +# if __SUNPRO_C >= 0x5100 + /* __SUNPRO_C = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF) +# endif + +#elif defined(__HP_cc) +# define COMPILER_ID "HP" + /* __HP_cc = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_cc % 100) + +#elif defined(__DECC) +# define COMPILER_ID "Compaq" + /* __DECC_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECC_VER % 10000) + +#elif defined(__IBMC__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__open_xl__) && defined(__clang__) +# define COMPILER_ID "IBMClang" +# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__) +# define COMPILER_VERSION_MINOR DEC(__open_xl_release__) +# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__) + + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800 +# define COMPILER_ID "XL" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMC__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(__clang__) && defined(__cray__) +# define COMPILER_ID "CrayClang" +# define COMPILER_VERSION_MAJOR DEC(__cray_major__) +# define COMPILER_VERSION_MINOR DEC(__cray_minor__) +# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__TASKING__) +# define COMPILER_ID "Tasking" + # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000) + # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100) +# define COMPILER_VERSION_INTERNAL DEC(__VERSION__) + +#elif defined(__ORANGEC__) +# define COMPILER_ID "OrangeC" +# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__) + +#elif defined(__TINYC__) +# define COMPILER_ID "TinyCC" + +#elif defined(__BCC__) +# define COMPILER_ID "Bruce" + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100 % 100) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) && defined(__ti__) +# define COMPILER_ID "TIClang" + # define COMPILER_VERSION_MAJOR DEC(__ti_major__) + # define COMPILER_VERSION_MINOR DEC(__ti_minor__) + # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__) +# define COMPILER_VERSION_INTERNAL DEC(__ti_version__) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__)) +# define COMPILER_ID "LCC" +# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100) +# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100) +# if defined(__LCC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__) +# endif +# if defined(__GNUC__) && defined(__GNUC_MINOR__) +# define SIMULATE_ID "GNU" +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif +# endif + +#elif defined(__GNUC__) +# define COMPILER_ID "GNU" +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(_ADI_COMPILER) +# define COMPILER_ID "ADSP" +#if defined(__VERSIONNUM__) + /* __VERSIONNUM__ = 0xVVRRPPTT */ +# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF) +# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF) +# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF) +# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + +#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC) +# define COMPILER_ID "SDCC" +# if defined(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR) +# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR) +# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH) +# else + /* SDCC = VRP */ +# define COMPILER_VERSION_MAJOR DEC(SDCC/100) +# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10) +# define COMPILER_VERSION_PATCH DEC(SDCC % 10) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +# elif defined(_ADI_COMPILER) +# define PLATFORM_ID "ADSP" + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__clang__) && defined(__ti__) +# if defined(__ARM_ARCH) +# define ARCHITECTURE_ID "ARM" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +# elif defined(__ADSPSHARC__) +# define ARCHITECTURE_ID "SHARC" + +# elif defined(__ADSPBLACKFIN__) +# define ARCHITECTURE_ID "Blackfin" + +#elif defined(__TASKING__) + +# if defined(__CTC__) || defined(__CPTC__) +# define ARCHITECTURE_ID "TriCore" + +# elif defined(__CMCS__) +# define ARCHITECTURE_ID "MCS" + +# elif defined(__CARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__CARC__) +# define ARCHITECTURE_ID "ARC" + +# elif defined(__C51__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__CPCP__) +# define ARCHITECTURE_ID "PCP" + +# else +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#define C_STD_99 199901L +#define C_STD_11 201112L +#define C_STD_17 201710L +#define C_STD_23 202311L + +#ifdef __STDC_VERSION__ +# define C_STD __STDC_VERSION__ +#endif + +#if !defined(__STDC__) && !defined(__clang__) +# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__) +# define C_VERSION "90" +# else +# define C_VERSION +# endif +#elif C_STD > C_STD_17 +# define C_VERSION "23" +#elif C_STD > C_STD_11 +# define C_VERSION "17" +#elif C_STD > C_STD_99 +# define C_VERSION "11" +#elif C_STD >= C_STD_99 +# define C_VERSION "99" +#else +# define C_VERSION "90" +#endif +const char* info_language_standard_default = + "INFO" ":" "standard_default[" C_VERSION "]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +#ifdef ID_VOID_MAIN +void main() {} +#else +# if defined(__CLASSIC_C__) +int main(argc, argv) int argc; char *argv[]; +# else +int main(int argc, char* argv[]) +# endif +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; + require += info_arch[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; +} +#endif diff --git a/_codeql_build_dir/CMakeFiles/3.31.6/CompilerIdCXX/CMakeCXXCompilerId.cpp b/_codeql_build_dir/CMakeFiles/3.31.6/CompilerIdCXX/CMakeCXXCompilerId.cpp new file mode 100644 index 00000000..3b6e114c --- /dev/null +++ b/_codeql_build_dir/CMakeFiles/3.31.6/CompilerIdCXX/CMakeCXXCompilerId.cpp @@ -0,0 +1,919 @@ +/* This source file must have a .cpp extension so that all C++ compilers + recognize the extension without flags. Borland does not know .cxx for + example. */ +#ifndef __cplusplus +# error "A C compiler has been selected for C++." +#endif + +#if !defined(__has_include) +/* If the compiler does not have __has_include, pretend the answer is + always no. */ +# define __has_include(x) 0 +#endif + + +/* Version number components: V=Version, R=Revision, P=Patch + Version date components: YYYY=Year, MM=Month, DD=Day */ + +#if defined(__INTEL_COMPILER) || defined(__ICC) +# define COMPILER_ID "Intel" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# if defined(__GNUC__) +# define SIMULATE_ID "GNU" +# endif + /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later, + except that a few beta releases use the old format with V=2021. */ +# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111 +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10) +# if defined(__INTEL_COMPILER_UPDATE) +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE) +# else +# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10) +# endif +# else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER) +# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE) + /* The third version component from --version is an update index, + but no macro is provided for it. */ +# define COMPILER_VERSION_PATCH DEC(0) +# endif +# if defined(__INTEL_COMPILER_BUILD_DATE) + /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */ +# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE) +# endif +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER) +# define COMPILER_ID "IntelLLVM" +#if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +#endif +#if defined(__GNUC__) +# define SIMULATE_ID "GNU" +#endif +/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and + * later. Look for 6 digit vs. 8 digit version number to decide encoding. + * VVVV is no smaller than the current year when a version is released. + */ +#if __INTEL_LLVM_COMPILER < 1000000L +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10) +#else +# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000) +# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100) +#endif +#if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +#endif +#if defined(__GNUC__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +#elif defined(__GNUG__) +# define SIMULATE_VERSION_MAJOR DEC(__GNUG__) +#endif +#if defined(__GNUC_MINOR__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +#endif +#if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +#endif + +#elif defined(__PATHCC__) +# define COMPILER_ID "PathScale" +# define COMPILER_VERSION_MAJOR DEC(__PATHCC__) +# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__) +# if defined(__PATHCC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__) +# endif + +#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__) +# define COMPILER_ID "Embarcadero" +# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF) +# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF) +# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF) + +#elif defined(__BORLANDC__) +# define COMPILER_ID "Borland" + /* __BORLANDC__ = 0xVRR */ +# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8) +# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF) + +#elif defined(__WATCOMC__) && __WATCOMC__ < 1200 +# define COMPILER_ID "Watcom" + /* __WATCOMC__ = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__WATCOMC__) +# define COMPILER_ID "OpenWatcom" + /* __WATCOMC__ = VVRP + 1100 */ +# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100) +# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10) +# if (__WATCOMC__ % 10) > 0 +# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10) +# endif + +#elif defined(__SUNPRO_CC) +# define COMPILER_ID "SunPro" +# if __SUNPRO_CC >= 0x5100 + /* __SUNPRO_CC = 0xVRRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# else + /* __SUNPRO_CC = 0xVRP */ +# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8) +# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF) +# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF) +# endif + +#elif defined(__HP_aCC) +# define COMPILER_ID "HP" + /* __HP_aCC = VVRRPP */ +# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000) +# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100) +# define COMPILER_VERSION_PATCH DEC(__HP_aCC % 100) + +#elif defined(__DECCXX) +# define COMPILER_ID "Compaq" + /* __DECCXX_VER = VVRRTPPPP */ +# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000) +# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000 % 100) +# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER % 10000) + +#elif defined(__IBMCPP__) && defined(__COMPILER_VER__) +# define COMPILER_ID "zOS" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__open_xl__) && defined(__clang__) +# define COMPILER_ID "IBMClang" +# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__) +# define COMPILER_VERSION_MINOR DEC(__open_xl_release__) +# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__) + + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800 +# define COMPILER_ID "XL" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(__clang__) && defined(__cray__) +# define COMPILER_ID "CrayClang" +# define COMPILER_VERSION_MAJOR DEC(__cray_major__) +# define COMPILER_VERSION_MINOR DEC(__cray_minor__) +# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__TASKING__) +# define COMPILER_ID "Tasking" + # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000) + # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100) +# define COMPILER_VERSION_INTERNAL DEC(__VERSION__) + +#elif defined(__ORANGEC__) +# define COMPILER_ID "OrangeC" +# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__) + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100 % 100) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) && defined(__ti__) +# define COMPILER_ID "TIClang" + # define COMPILER_VERSION_MAJOR DEC(__ti_major__) + # define COMPILER_VERSION_MINOR DEC(__ti_minor__) + # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__) +# define COMPILER_VERSION_INTERNAL DEC(__ti_version__) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__)) +# define COMPILER_ID "LCC" +# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100) +# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100) +# if defined(__LCC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__) +# endif +# if defined(__GNUC__) && defined(__GNUC_MINOR__) +# define SIMULATE_ID "GNU" +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif +# endif + +#elif defined(__GNUC__) || defined(__GNUG__) +# define COMPILER_ID "GNU" +# if defined(__GNUC__) +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# else +# define COMPILER_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(_ADI_COMPILER) +# define COMPILER_ID "ADSP" +#if defined(__VERSIONNUM__) + /* __VERSIONNUM__ = 0xVVRRPPTT */ +# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF) +# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF) +# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF) +# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +# elif defined(_ADI_COMPILER) +# define PLATFORM_ID "ADSP" + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__clang__) && defined(__ti__) +# if defined(__ARM_ARCH) +# define ARCHITECTURE_ID "ARM" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +# elif defined(__ADSPSHARC__) +# define ARCHITECTURE_ID "SHARC" + +# elif defined(__ADSPBLACKFIN__) +# define ARCHITECTURE_ID "Blackfin" + +#elif defined(__TASKING__) + +# if defined(__CTC__) || defined(__CPTC__) +# define ARCHITECTURE_ID "TriCore" + +# elif defined(__CMCS__) +# define ARCHITECTURE_ID "MCS" + +# elif defined(__CARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__CARC__) +# define ARCHITECTURE_ID "ARC" + +# elif defined(__C51__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__CPCP__) +# define ARCHITECTURE_ID "PCP" + +# else +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#define CXX_STD_98 199711L +#define CXX_STD_11 201103L +#define CXX_STD_14 201402L +#define CXX_STD_17 201703L +#define CXX_STD_20 202002L +#define CXX_STD_23 202302L + +#if defined(__INTEL_COMPILER) && defined(_MSVC_LANG) +# if _MSVC_LANG > CXX_STD_17 +# define CXX_STD _MSVC_LANG +# elif _MSVC_LANG == CXX_STD_17 && defined(__cpp_aggregate_paren_init) +# define CXX_STD CXX_STD_20 +# elif _MSVC_LANG > CXX_STD_14 && __cplusplus > CXX_STD_17 +# define CXX_STD CXX_STD_20 +# elif _MSVC_LANG > CXX_STD_14 +# define CXX_STD CXX_STD_17 +# elif defined(__INTEL_CXX11_MODE__) && defined(__cpp_aggregate_nsdmi) +# define CXX_STD CXX_STD_14 +# elif defined(__INTEL_CXX11_MODE__) +# define CXX_STD CXX_STD_11 +# else +# define CXX_STD CXX_STD_98 +# endif +#elif defined(_MSC_VER) && defined(_MSVC_LANG) +# if _MSVC_LANG > __cplusplus +# define CXX_STD _MSVC_LANG +# else +# define CXX_STD __cplusplus +# endif +#elif defined(__NVCOMPILER) +# if __cplusplus == CXX_STD_17 && defined(__cpp_aggregate_paren_init) +# define CXX_STD CXX_STD_20 +# else +# define CXX_STD __cplusplus +# endif +#elif defined(__INTEL_COMPILER) || defined(__PGI) +# if __cplusplus == CXX_STD_11 && defined(__cpp_namespace_attributes) +# define CXX_STD CXX_STD_17 +# elif __cplusplus == CXX_STD_11 && defined(__cpp_aggregate_nsdmi) +# define CXX_STD CXX_STD_14 +# else +# define CXX_STD __cplusplus +# endif +#elif (defined(__IBMCPP__) || defined(__ibmxl__)) && defined(__linux__) +# if __cplusplus == CXX_STD_11 && defined(__cpp_aggregate_nsdmi) +# define CXX_STD CXX_STD_14 +# else +# define CXX_STD __cplusplus +# endif +#elif __cplusplus == 1 && defined(__GXX_EXPERIMENTAL_CXX0X__) +# define CXX_STD CXX_STD_11 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These variables +# should be set in the CMake list file of the project before CPack module is +# included. The list of available CPACK_xxx variables and their associated +# documentation may be obtained using +# cpack --help-variable-list +# +# Some variables are common to all generators (e.g. CPACK_PACKAGE_NAME) +# and some are specific to a generator +# (e.g. CPACK_NSIS_EXTRA_INSTALL_COMMANDS). The generator specific variables +# usually begin with CPACK__xxxx. + + +set(CPACK_BUILD_SOURCE_DIRS "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm;/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir") +set(CPACK_CMAKE_GENERATOR "Unix Makefiles") +set(CPACK_COMPONENT_UNSPECIFIED_HIDDEN "TRUE") +set(CPACK_COMPONENT_UNSPECIFIED_REQUIRED "TRUE") +set(CPACK_DEBIAN_PACKAGE_SHLIBDEPS "ON") +set(CPACK_DEB_COMPONENT_INSTALL "ON") +set(CPACK_DEFAULT_PACKAGE_DESCRIPTION_FILE "/usr/local/share/cmake-3.31/Templates/CPack.GenericDescription.txt") +set(CPACK_DEFAULT_PACKAGE_DESCRIPTION_SUMMARY "PCM built using CMake") +set(CPACK_DMG_SLA_USE_RESOURCE_FILE_LICENSE "ON") +set(CPACK_GENERATOR "DEB") +set(CPACK_INNOSETUP_ARCHITECTURE "x64") +set(CPACK_INSTALL_CMAKE_PROJECTS "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir;PCM;ALL;/") +set(CPACK_INSTALL_DEFAULT_DIRECTORY_PERMISSIONS "OWNER_READ;OWNER_WRITE;OWNER_EXECUTE;GROUP_READ;GROUP_EXECUTE;WORLD_READ;WORLD_EXECUTE") +set(CPACK_INSTALL_PREFIX "/usr/local") +set(CPACK_MODULE_PATH "") +set(CPACK_NSIS_DISPLAY_NAME "/usr/local") +set(CPACK_NSIS_INSTALLER_ICON_CODE "") +set(CPACK_NSIS_INSTALLER_MUI_ICON_CODE "") +set(CPACK_NSIS_INSTALL_ROOT "$PROGRAMFILES") +set(CPACK_NSIS_PACKAGE_NAME "/usr/local") +set(CPACK_NSIS_UNINSTALL_NAME "Uninstall") +set(CPACK_OBJCOPY_EXECUTABLE "/usr/bin/objcopy") +set(CPACK_OBJDUMP_EXECUTABLE "/usr/bin/objdump") +set(CPACK_OUTPUT_CONFIG_FILE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir/CPackConfig.cmake") +set(CPACK_PACKAGE_CONTACT "intel ") +set(CPACK_PACKAGE_DEFAULT_LOCATION "/") +set(CPACK_PACKAGE_DESCRIPTION " Intel(r) Performance Counter Monitor (Intel(r) PCM) is an application programming + interface (API) and a set of tools based on the API to monitor + performance and energy metrics of Intel(r) Core(tm), Xeon(r), Atom(tm) + and Xeon Phi(tm) processors. PCM works on Linux, Windows, Mac OS X, + FreeBSD and DragonFlyBSD operating systems.") +set(CPACK_PACKAGE_DESCRIPTION_FILE "/usr/local/share/cmake-3.31/Templates/CPack.GenericDescription.txt") +set(CPACK_PACKAGE_DESCRIPTION_SUMMARY "Intel(r) Performance Counter Monitor (Intel(r) PCM)") +set(CPACK_PACKAGE_FILE_NAME "pcm-0000-Linux") +set(CPACK_PACKAGE_INSTALL_DIRECTORY "/usr/local") +set(CPACK_PACKAGE_INSTALL_REGISTRY_KEY "/usr/local") +set(CPACK_PACKAGE_NAME "pcm") +set(CPACK_PACKAGE_RELOCATABLE "true") +set(CPACK_PACKAGE_VENDOR "Humanity") +set(CPACK_PACKAGE_VERSION "0000") +set(CPACK_PACKAGE_VERSION_MAJOR "0") +set(CPACK_PACKAGE_VERSION_MINOR "1") +set(CPACK_PACKAGE_VERSION_PATCH "1") +set(CPACK_READELF_EXECUTABLE "/usr/bin/readelf") +set(CPACK_RESOURCE_FILE_LICENSE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/LICENSE") +set(CPACK_RESOURCE_FILE_README "/usr/local/share/cmake-3.31/Templates/CPack.GenericDescription.txt") +set(CPACK_RESOURCE_FILE_WELCOME "/usr/local/share/cmake-3.31/Templates/CPack.GenericWelcome.txt") +set(CPACK_RPM_COMPONENT_INSTALL "ON") +set(CPACK_RPM_PACKAGE_DESCRIPTION " Intel(r) Performance Counter Monitor (Intel(r) PCM) is an application programming + interface (API) and a set of tools based on the API to monitor + performance and energy metrics of Intel(r) Core(tm), Xeon(r), Atom(tm) + and Xeon Phi(tm) processors. PCM works on Linux, Windows, Mac OS X, + FreeBSD and DragonFlyBSD operating systems.") +set(CPACK_RPM_PACKAGE_LICENSE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/LICENSE") +set(CPACK_RPM_PACKAGE_RELOCATABLE "TRUE") +set(CPACK_SET_DESTDIR "OFF") +set(CPACK_SOURCE_GENERATOR "TBZ2;TGZ;TXZ;TZ") +set(CPACK_SOURCE_OUTPUT_CONFIG_FILE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir/CPackSourceConfig.cmake") +set(CPACK_SOURCE_RPM "OFF") +set(CPACK_SOURCE_TBZ2 "ON") +set(CPACK_SOURCE_TGZ "ON") +set(CPACK_SOURCE_TXZ "ON") +set(CPACK_SOURCE_TZ "ON") +set(CPACK_SOURCE_ZIP "OFF") +set(CPACK_SYSTEM_NAME "Linux") +set(CPACK_THREADS "1") +set(CPACK_TOPLEVEL_TAG "Linux") +set(CPACK_WIX_SIZEOF_VOID_P "8") + +if(NOT CPACK_PROPERTIES_FILE) + set(CPACK_PROPERTIES_FILE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir/CPackProperties.cmake") +endif() + +if(EXISTS ${CPACK_PROPERTIES_FILE}) + include(${CPACK_PROPERTIES_FILE}) +endif() diff --git a/_codeql_build_dir/CPackSourceConfig.cmake b/_codeql_build_dir/CPackSourceConfig.cmake new file mode 100644 index 00000000..4bf9e058 --- /dev/null +++ b/_codeql_build_dir/CPackSourceConfig.cmake @@ -0,0 +1,96 @@ +# This file will be configured to contain variables for CPack. These variables +# should be set in the CMake list file of the project before CPack module is +# included. The list of available CPACK_xxx variables and their associated +# documentation may be obtained using +# cpack --help-variable-list +# +# Some variables are common to all generators (e.g. CPACK_PACKAGE_NAME) +# and some are specific to a generator +# (e.g. CPACK_NSIS_EXTRA_INSTALL_COMMANDS). The generator specific variables +# usually begin with CPACK__xxxx. + + +set(CPACK_BUILD_SOURCE_DIRS "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm;/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir") +set(CPACK_CMAKE_GENERATOR "Unix Makefiles") +set(CPACK_COMPONENT_UNSPECIFIED_HIDDEN "TRUE") +set(CPACK_COMPONENT_UNSPECIFIED_REQUIRED "TRUE") +set(CPACK_DEBIAN_PACKAGE_SHLIBDEPS "ON") +set(CPACK_DEB_COMPONENT_INSTALL "ON") +set(CPACK_DEFAULT_PACKAGE_DESCRIPTION_FILE "/usr/local/share/cmake-3.31/Templates/CPack.GenericDescription.txt") +set(CPACK_DEFAULT_PACKAGE_DESCRIPTION_SUMMARY "PCM built using CMake") +set(CPACK_DMG_SLA_USE_RESOURCE_FILE_LICENSE "ON") +set(CPACK_GENERATOR "TBZ2;TGZ;TXZ;TZ") +set(CPACK_IGNORE_FILES "/CVS/;/\\.svn/;/\\.bzr/;/\\.hg/;/\\.git/;\\.swp\$;\\.#;/#") +set(CPACK_INNOSETUP_ARCHITECTURE "x64") +set(CPACK_INSTALLED_DIRECTORIES "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm;/") +set(CPACK_INSTALL_CMAKE_PROJECTS "") +set(CPACK_INSTALL_DEFAULT_DIRECTORY_PERMISSIONS "OWNER_READ;OWNER_WRITE;OWNER_EXECUTE;GROUP_READ;GROUP_EXECUTE;WORLD_READ;WORLD_EXECUTE") +set(CPACK_INSTALL_PREFIX "/usr/local") +set(CPACK_MODULE_PATH "") +set(CPACK_NSIS_DISPLAY_NAME "/usr/local") +set(CPACK_NSIS_INSTALLER_ICON_CODE "") +set(CPACK_NSIS_INSTALLER_MUI_ICON_CODE "") +set(CPACK_NSIS_INSTALL_ROOT "$PROGRAMFILES") +set(CPACK_NSIS_PACKAGE_NAME "/usr/local") +set(CPACK_NSIS_UNINSTALL_NAME "Uninstall") +set(CPACK_OBJCOPY_EXECUTABLE "/usr/bin/objcopy") +set(CPACK_OBJDUMP_EXECUTABLE "/usr/bin/objdump") +set(CPACK_OUTPUT_CONFIG_FILE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir/CPackConfig.cmake") +set(CPACK_PACKAGE_CONTACT "intel ") +set(CPACK_PACKAGE_DEFAULT_LOCATION "/") +set(CPACK_PACKAGE_DESCRIPTION " Intel(r) Performance Counter Monitor (Intel(r) PCM) is an application programming + interface (API) and a set of tools based on the API to monitor + performance and energy metrics of Intel(r) Core(tm), Xeon(r), Atom(tm) + and Xeon Phi(tm) processors. PCM works on Linux, Windows, Mac OS X, + FreeBSD and DragonFlyBSD operating systems.") +set(CPACK_PACKAGE_DESCRIPTION_FILE "/usr/local/share/cmake-3.31/Templates/CPack.GenericDescription.txt") +set(CPACK_PACKAGE_DESCRIPTION_SUMMARY "Intel(r) Performance Counter Monitor (Intel(r) PCM)") +set(CPACK_PACKAGE_FILE_NAME "pcm-0000-Source") +set(CPACK_PACKAGE_INSTALL_DIRECTORY "/usr/local") +set(CPACK_PACKAGE_INSTALL_REGISTRY_KEY "/usr/local") +set(CPACK_PACKAGE_NAME "pcm") +set(CPACK_PACKAGE_RELOCATABLE "true") +set(CPACK_PACKAGE_VENDOR "Humanity") +set(CPACK_PACKAGE_VERSION "0000") +set(CPACK_PACKAGE_VERSION_MAJOR "0") +set(CPACK_PACKAGE_VERSION_MINOR "1") +set(CPACK_PACKAGE_VERSION_PATCH "1") +set(CPACK_READELF_EXECUTABLE "/usr/bin/readelf") +set(CPACK_RESOURCE_FILE_LICENSE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/LICENSE") +set(CPACK_RESOURCE_FILE_README "/usr/local/share/cmake-3.31/Templates/CPack.GenericDescription.txt") +set(CPACK_RESOURCE_FILE_WELCOME "/usr/local/share/cmake-3.31/Templates/CPack.GenericWelcome.txt") +set(CPACK_RPM_COMPONENT_INSTALL "ON") +set(CPACK_RPM_PACKAGE_DESCRIPTION " Intel(r) Performance Counter Monitor (Intel(r) PCM) is an application programming + interface (API) and a set of tools based on the API to monitor + performance and energy metrics of Intel(r) Core(tm), Xeon(r), Atom(tm) + and Xeon Phi(tm) processors. PCM works on Linux, Windows, Mac OS X, + FreeBSD and DragonFlyBSD operating systems.") +set(CPACK_RPM_PACKAGE_LICENSE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/LICENSE") +set(CPACK_RPM_PACKAGE_RELOCATABLE "TRUE") +set(CPACK_RPM_PACKAGE_SOURCES "ON") +set(CPACK_SET_DESTDIR "OFF") +set(CPACK_SOURCE_GENERATOR "TBZ2;TGZ;TXZ;TZ") +set(CPACK_SOURCE_IGNORE_FILES "/CVS/;/\\.svn/;/\\.bzr/;/\\.hg/;/\\.git/;\\.swp\$;\\.#;/#") +set(CPACK_SOURCE_INSTALLED_DIRECTORIES "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm;/") +set(CPACK_SOURCE_OUTPUT_CONFIG_FILE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir/CPackSourceConfig.cmake") +set(CPACK_SOURCE_PACKAGE_FILE_NAME "pcm-0000-Source") +set(CPACK_SOURCE_RPM "OFF") +set(CPACK_SOURCE_TBZ2 "ON") +set(CPACK_SOURCE_TGZ "ON") +set(CPACK_SOURCE_TOPLEVEL_TAG "Linux-Source") +set(CPACK_SOURCE_TXZ "ON") +set(CPACK_SOURCE_TZ "ON") +set(CPACK_SOURCE_ZIP "OFF") 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named pcm-tpmi + +# Build rule for target. +pcm-tpmi: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 pcm-tpmi +.PHONY : pcm-tpmi + +# fast build rule for target. +pcm-tpmi/fast: + $(MAKE) $(MAKESILENT) -f src/CMakeFiles/pcm-tpmi.dir/build.make src/CMakeFiles/pcm-tpmi.dir/build +.PHONY : pcm-tpmi/fast + +#============================================================================= +# Target rules for targets named pcm-raw + +# Build rule for target. +pcm-raw: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 pcm-raw +.PHONY : pcm-raw + +# fast build rule for target. +pcm-raw/fast: + $(MAKE) $(MAKESILENT) -f src/CMakeFiles/pcm-raw.dir/build.make src/CMakeFiles/pcm-raw.dir/build +.PHONY : pcm-raw/fast + +#============================================================================= +# Target rules for targets named pcm-accel + +# Build rule for target. +pcm-accel: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 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build rule for target. +pcm-sensor/fast: + $(MAKE) $(MAKESILENT) -f src/CMakeFiles/pcm-sensor.dir/build.make src/CMakeFiles/pcm-sensor.dir/build +.PHONY : pcm-sensor/fast + +#============================================================================= +# Target rules for targets named daemon + +# Build rule for target. +daemon: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 daemon +.PHONY : daemon + +# fast build rule for target. +daemon/fast: + $(MAKE) $(MAKESILENT) -f src/CMakeFiles/daemon.dir/build.make src/CMakeFiles/daemon.dir/build +.PHONY : daemon/fast + +#============================================================================= +# Target rules for targets named client + +# Build rule for target. +client: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 client +.PHONY : client + +# fast build rule for target. +client/fast: + $(MAKE) $(MAKESILENT) -f src/CMakeFiles/client.dir/build.make src/CMakeFiles/client.dir/build +.PHONY : client/fast + +#============================================================================= +# Target rules for targets named c_example + +# Build rule for target. +c_example: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 c_example +.PHONY : c_example + +# fast build rule for target. +c_example/fast: + $(MAKE) $(MAKESILENT) -f examples/CMakeFiles/c_example.dir/build.make examples/CMakeFiles/c_example.dir/build +.PHONY : c_example/fast + +#============================================================================= +# Target rules for targets named c_example_shlib + +# Build rule for target. +c_example_shlib: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 c_example_shlib +.PHONY : c_example_shlib + +# fast build rule for target. +c_example_shlib/fast: + $(MAKE) $(MAKESILENT) -f examples/CMakeFiles/c_example_shlib.dir/build.make examples/CMakeFiles/c_example_shlib.dir/build +.PHONY : c_example_shlib/fast + +#============================================================================= +# Target rules for targets named daemon_alignment_test + +# Build rule for target. +daemon_alignment_test: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 daemon_alignment_test +.PHONY : daemon_alignment_test + +# fast build rule for target. +daemon_alignment_test/fast: + $(MAKE) $(MAKESILENT) -f tests/CMakeFiles/daemon_alignment_test.dir/build.make tests/CMakeFiles/daemon_alignment_test.dir/build +.PHONY : daemon_alignment_test/fast + +#============================================================================= +# Target rules for targets named urltest + +# Build rule for target. +urltest: cmake_check_build_system + $(MAKE) $(MAKESILENT) -f CMakeFiles/Makefile2 urltest +.PHONY : urltest + +# fast build rule for target. +urltest/fast: + $(MAKE) $(MAKESILENT) -f tests/CMakeFiles/urltest.dir/build.make tests/CMakeFiles/urltest.dir/build +.PHONY : urltest/fast + +# Help Target +help: + @echo "The following are some of the valid targets for this Makefile:" + @echo "... all (the default if no target is provided)" + @echo "... clean" + @echo "... depend" + @echo "... edit_cache" + @echo "... install" + @echo "... install/local" + @echo "... install/strip" + @echo "... list_install_components" + @echo "... package" + @echo "... package_source" + @echo "... rebuild_cache" + @echo "... PCM_SHARED" + @echo "... PCM_STATIC" + @echo "... PCM_STATIC_SILENT" + @echo "... c_example" + @echo "... c_example_shlib" + @echo "... client" + @echo "... daemon" + @echo "... daemon_alignment_test" + @echo "... pcm" + @echo "... pcm-accel" + @echo "... pcm-core" + @echo "... pcm-iio" + @echo "... pcm-latency" + @echo "... pcm-memory" + @echo "... pcm-mmio" + @echo "... pcm-msr" + @echo "... pcm-numa" + @echo "... pcm-pcicfg" + @echo "... pcm-pcie" + @echo "... pcm-power" + @echo "... pcm-raw" + @echo "... pcm-sensor" + @echo "... pcm-sensor-server" + @echo "... pcm-tpmi" + @echo "... pcm-tsx" + @echo "... urltest" +.PHONY : help + + + +#============================================================================= +# Special targets to cleanup operation of make. + +# Special rule to run CMake to check the build system integrity. +# No rule that depends on this can have commands that come from listfiles +# because they might be regenerated. +cmake_check_build_system: + $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 +.PHONY : cmake_check_build_system + diff --git a/_codeql_build_dir/bin/CUSTOM-COMPILE-OPTIONS.md b/_codeql_build_dir/bin/CUSTOM-COMPILE-OPTIONS.md new file mode 100644 index 00000000..9b05f49f --- /dev/null +++ b/_codeql_build_dir/bin/CUSTOM-COMPILE-OPTIONS.md @@ -0,0 +1,15 @@ +cpucounters.h : `#define PCM_HA_REQUESTS_READS_ONLY` +For the metric "LOCAL: number of local memory access in %“ (getLocalMemoryRequestRatio API) count only read accesses (local and all). + +cpucounters.h : `#define PCM_DEBUG_TOPOLOGY` +print detailed CPU topology information + +cpucounters.h : `#define PCM_UNCORE_PMON_BOX_CHECK_STATUS` +verify uncore PMU register state after programming + +types.h : `#define PCM_DEBUG` +print some debug information + +pci.h : `#define PCM_USE_PCI_MM_LINUX` +use /dev/mem (direct memory mapped I/O) for PCICFG register access on Linux. This might be required for accessing registers in extended configuration space (beyond 4K) in *pcm-pcicfg* utility. Recent Linux kernels also require to be booted with iomem=relaxed option to make this work. + diff --git a/_codeql_build_dir/bin/CXL_README.md b/_codeql_build_dir/bin/CXL_README.md new file mode 100644 index 00000000..ad9265be --- /dev/null +++ b/_codeql_build_dir/bin/CXL_README.md @@ -0,0 +1,15 @@ +PCM can collect CLX bandwidth using the methods below. + +-------------------------------------------------------------------------------- +CXL.mem and CXL.cache traffic +-------------------------------------------------------------------------------- + +Please use pcm-memory utility for monitoring CXL.mem and CLX.cache traffic. pcm-memory will detect available CXL ports and will show traffic per CXL port and protocol (mem and cache) and per direction (read and write). + +-------------------------------------------------------------------------------- +CXL.io traffic +-------------------------------------------------------------------------------- + +pcm-iio utility should be used to monitor CXL.io traffic. pcm-iio will show traffic per CXL device and direction (inbound/outbound, read/write) + + diff --git a/_codeql_build_dir/bin/DOCKER_README.md b/_codeql_build_dir/bin/DOCKER_README.md new file mode 100644 index 00000000..ed38f7ed --- /dev/null +++ b/_codeql_build_dir/bin/DOCKER_README.md @@ -0,0 +1,14 @@ +-------------------------------------------------------------------------------- +How To Run Intel(r) Performance Counter Monitor Server Container from GitHub Container Repository or Docker Hub +-------------------------------------------------------------------------------- + +As root user: +1. ``modprobe msr`` +2. ``docker run -d --name pcm --privileged -p 9738:9738 ghcr.io/intel/pcm`` (GitHub Container repository) or ``docker run -d --name pcm --privileged -p 9738:9738 opcm/pcm`` (Dockerhub repository) + - the container can also be run with limited capabilities without the privileged mode: ``docker run -d --name pcm --cap-add=SYS_ADMIN --cap-add=SYS_RAWIO --device=/dev/cpu --device=/dev/mem -v /sys/firmware/acpi/tables/MCFG:/pcm/sys/firmware/acpi/tables/MCFG:ro -v /proc/bus/pci/:/pcm/proc/bus/pci/ -v /proc/sys/kernel/nmi_watchdog:/pcm/proc/sys/kernel/nmi_watchdog -v /sys:/sys:rw -p 9738:9738 ghcr.io/intel/pcm`` (there is also a docker-compose file containing these options: https://raw.githubusercontent.com/intel/pcm/master/docker-compose.yml) + +This will start pcm-sensor-server container exposing CPU metrics from the whole system at port 9738 + +The URLs of the docker container repositories: +- https://github.com/intel/pcm/pkgs/container/pcm +- https://hub.docker.com/r/opcm/pcm diff --git a/_codeql_build_dir/bin/ENVVAR_README.md b/_codeql_build_dir/bin/ENVVAR_README.md new file mode 100644 index 00000000..3a93ced0 --- /dev/null +++ b/_codeql_build_dir/bin/ENVVAR_README.md @@ -0,0 +1,17 @@ +`PCM_NO_PERF=1` : don't use Linux perf events API to program *core* PMUs (default is to use it) + +`PCM_USE_UNCORE_PERF=1` : use Linux perf events API to program *uncore* PMUs (default is *not* to use it) + +`PCM_NO_RDT=1` : don't use RDT metrics for a better interoperation with pqos utility (https://github.com/intel/intel-cmt-cat) + +`PCM_USE_RESCTRL=1` : use Linux resctrl driver for RDT metrics + +`PCM_PRINT_TOPOLOGY=1` : print detailed CPU topology + +`PCM_KEEP_NMI_WATCHDOG=1` : don't disable NMI watchdog (reducing the core metrics set) + +`PCM_NO_MAIN_EXCEPTION_HANDLER=1` : don't catch exceptions in the main function of pcm tools (a debugging option) + +`PCM_ENFORCE_MBM=1` : force-enable Memory Bandwidth Monitoring (MBM) metrics (LocalMemoryBW = LMB) and (RemoteMemoryBW = RMB) on processors with RDT/MBM errata + +`PCM_DEBUG_LEVEL=x` : x is an integer defining debug output level. level = 0 (default): minimal or no debug info, > 0 increases verbosity diff --git a/_codeql_build_dir/bin/FAQ.md b/_codeql_build_dir/bin/FAQ.md new file mode 100644 index 00000000..88a0266d --- /dev/null +++ b/_codeql_build_dir/bin/FAQ.md @@ -0,0 +1,95 @@ + +## Q1 + +pcm-iio Tool outputs "Server CPU is required for this tool! Program aborted". Is there a way I can monitor my PCIe link bandwidth using one of the PCM utilities on client CPU? + +Answer: The "IO" metric in *pcm* utility is the closest capability to monitor I/O PCIe traffic on client CPUs. + +## Q2 + +PCM reports "ERROR: QPI LL monitoring device (...) is missing". How to fix it? + +Answer: It is likely a BIOS issue. See details [here](https://software.intel.com/content/www/us/en/develop/articles/bios-preventing-access-to-qpi-performance-counters.html) + +## Q3 + +Does PCM work inside a virtual machine? + +Answer: PCM works inside virtual machines which support vPMU (with a limited set of metrics supported by vPMU). For example on AWS instances this is indicated by the presence of [arch_perfmon](https://instaguide.io/info.html?type=c5.18xlarge) flag: https://instaguide.io/ . Enabling vPMU in hypervisors is documented [in Hardware Event-Based Sampling section](https://software.intel.com/content/www/us/en/develop/documentation/vtune-help/top/set-up-analysis-target/on-virtual-machine.html). + +## Q4 + +Does PCM work inside a docker container? + +Answer: yes, it does. An example of how to run PCM inside a docker container is located [here](DOCKER_README.md). The recipe works also for other PCM utilities besides pcm-sensor-server. + +## Q5 + +pcm-power reports "Unsupported processor model". Can you add support for pcm-power for my CPU? + +Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. PCM-power can not work without them. + +## Q6 + +pcm-memory reports that the CPU is not supported. Can you add support for pcm-memory for my CPU? + +Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. PCM-memory can not work without them. + +## Q7 + +Can PCM be used for measuring energy, CPU cycles, etc for a particular process or does it measure for the system as a whole? + +Answer: PCM supports measurement for the whole system, per processor, per physical or per logical core. If you need monitoring per-process or user per-thread you can pin your process and/or thread to certain cores and read PCM data for these cores. But keep in mind that the OS can also schedule other processes or threads on this core and this may disturb your measurements. For a precise per-process or per-thread measurement the Intel VTune profiler or Linux perf profiler should be used. + +## Q8 + +PCM reports + +``` +opening /dev/mem failed: errno is 1 (Operation not permitted) +Can not read memory controller counter information from PCI configuration space. Access to memory bandwidth counters is not possible. +You must be root to access these SandyBridge/IvyBridge/Haswell counters in PCM. +Secure Boot detected. Using Linux perf for uncore PMU programming. +``` + +How to fix it? + +Answer: Linux disables access to /dev/mem because Secure Boot is enabled in the BIOS. Disable Secure Boot in the BIOS to enable memory controller statistics (e.g. memory read and write bandwidth). + +## Q9 + +PCM reports +``` +Linux Perf: Error on programming ... +``` +How to fix it? + +**Answer:** It is an issue with the Linux kernel perf driver. As a workaround upgrade your Linux kernel to the latest available/possible or run PCM with its own programming logic: + +``` +export PCM_NO_PERF=1 +pcm -r +``` + +## Q10 + +If you are getting the error `Starting MSR service failed with error 3 The system cannot find the path specified.` try to uninstall the driver by running `pcm --uninstallDriver` and optionally reboot the system. + +## Q11 + +Is PCM supported on AWS instances + +**Answer**: + +Not all AWS instances allow users to collect CPU telemetry by exposing PMU to the user. The following instances can be used: + +* Bare metal instances: allow collection of CPU metrics from both core (e.g. instructions per cycle, cache misses) and uncore (e.g. memory controller, UPI) +* Full-socket (single socket, two socket, etc) virtualized instances: e.g. m5d.12xlarge, m5.24xlarge, m5.12xlarge. Only core CPU metrics are exposed, and certain CPU performance events are forbidden (e.g. offcore response events, events collecting “any_thread” information). “arch_perfmon” flag in /proc/cpuinfo indicates if the core CPU metrics are exposed (example: https://instaguide.io/info.html?type=m5.12xlarge ). The mechanism of PMU virtualization is commonly known as vPMU. + +## Q12 + +pcm-pcie reports that the CPU is not supported: "Jaketown, Ivytown, Haswell, Broadwell-DE, Skylake, Icelake, Snowridge and Sapphirerapids Server CPU is required for this tool! Program aborted" +Can you add support for pcm-pcie for my CPU? + +Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. pcm-pcie can not work without them. + diff --git a/_codeql_build_dir/bin/FREEBSD_HOWTO.txt b/_codeql_build_dir/bin/FREEBSD_HOWTO.txt new file mode 100644 index 00000000..7711c85f --- /dev/null +++ b/_codeql_build_dir/bin/FREEBSD_HOWTO.txt @@ -0,0 +1,8 @@ +Building: +$ cmake -B build +$ cmake --build build + +Runtime requirements: +* the cpuctl(4) driver needs to be loaded + +PCM is also available as a port maintained by The FreeBSD Project (sysutils/intel-pcm). diff --git a/_codeql_build_dir/bin/LATENCY-OPTIMIZED-MODE.md b/_codeql_build_dir/bin/LATENCY-OPTIMIZED-MODE.md new file mode 100644 index 00000000..6cf74314 --- /dev/null +++ b/_codeql_build_dir/bin/LATENCY-OPTIMIZED-MODE.md @@ -0,0 +1,61 @@ +# Latency Optimized Mode in Intel® Xeon® 6 Processors + +Intel® Xeon® 6 Processors (previously codenamed Granite Rapids and Sierra Forest/Birch Stream platform) introduce a new power management mechanism called Efficiency Latency Control (ELC), designed to optimize performance per watt. This feature allows hardware power management algorithms to balance the trade-off between latency and power consumption. For latency-sensitive workloads, further tuning can be performed to achieve the desired performance. + +The hardware monitors the average CPU utilization across all cores at regular intervals to determine an appropriate uncore frequency. While this approach generally results in optimal performance per watt, some workloads may achieve higher performance at the expense of increased power consumption. For instance, an application that intermittently performs memory reads on an otherwise idle system may experience delays if the hardware lowers the uncore frequency, causing a lag in ramping up to the required performance levels. To verify this, the uncore frequencies can be monitored using the pcm utility: + +![Uncore Frequency Statistics DEFAULT](https://github.com/user-attachments/assets/108c7350-3fc2-4056-aeaf-ecc7c25da6bc) + +The screenshot above presents real-time data on uncore frequency statistics, measured in GHz, from a dual-socket platform (represented by two rows). Each socket includes five dies (organized into five columns). The first three dies contain CORes (COR), Last Level Cache (LLC), and Memory controllers (M), collectively referred to as CORLLCM. The final two dies are IO dies. + +The ELC control has parameters that can be adjusted either through BIOS or software tools. The default parameter configuration is optimized for performance per watt, ensuring power efficiency. The alternative configuration, known as Latency Optimized Mode, prioritizes maximum performance. +Below are the PCM statistics from a system operating in Latency Optimized Mode: + +![Uncore Frequency Statistics Latency Optimized Mode](https://github.com/user-attachments/assets/70310bbc-725b-4450-af7a-1db2c04291dd) + +## BIOS Options for Latency Optimized Mode + +The BIOS option for selecting the Default or Latency Optimized Mode can typically be located in the following menus, depending on the BIOS version and OEM vendor: +- **Socket Configuration** -> **Advanced Power Management** -> **CPU – Advanced PM Tuning** -> **Latency Optimized Mode** (Disabled or Enabled) +- **System Utilities** -> **System Configuration** -> **BIOS/Platform Configuration (RBSU)** -> **Power and Performance Options** -> **Advanced Power Options** -> **Efficiency Latency Control** (Default or Latency Optimized mode) + +Should this BIOS option be unavailable or if there is a preference to change the mode during runtime, the PCM repository provides scripts for changing this mode. + +|Platform |Script Type| URL | +|------------------|-----------|---------------------------------------------------------------------| +|Linux/FreeBSD/UNIX|bash | https://github.com/intel/pcm/blob/master/scripts/bhs-power-mode.sh | +|Windows |powershell | https://github.com/intel/pcm/blob/master/scripts/bhs-power-mode.ps1 | + +The scripts require the pcm-tpmi utility. There are several methods to obtain this utility: +- **Download or install precompiled PCM binaries:** Please refer to the following link: [Downloading Pre-Compiled PCM Tools](https://github.com/intel/pcm?tab=readme-ov-file#downloading-pre-compiled-pcm-tools) +- **Compile the utility:** Follow the instructions in the "Building PCM Tools" section available at: [Building PCM Tools](https://github.com/intel/pcm?tab=readme-ov-file#building-pcm-tools) + * For Linux/FreeBSD: Copy the pcm-tpmi utility from PCM’s source 'build/bin' directory to `/usr/local/bin/` or execute `make install` in the 'build' directory. + +For Windows: Copy the pcm-tpmi utility to the current directory. + +Once the pcm-tpmi binary is correctly placed, you can set the Latency Optimized Mode. + +### Setting Latency Optimized Mode + +Linux/FreeBSD/UNIX: +``` +bash bhs-power-mode.sh --latency-optimized-mode +``` +Windows: +``` +.\bhs-power-mode.ps1 --latency-optimized-mode +``` + +### Restoring the Default Mode + +Linux/FreeBSD/UNIX: +``` +bash bhs-power-mode.sh --default +``` + +Windows: +``` +.\bhs-power-mode.ps1 --default +``` + + diff --git a/_codeql_build_dir/bin/LINUX_HOWTO.txt b/_codeql_build_dir/bin/LINUX_HOWTO.txt new file mode 100644 index 00000000..19062902 --- /dev/null +++ b/_codeql_build_dir/bin/LINUX_HOWTO.txt @@ -0,0 +1,7 @@ +Refer to the main README ("Building PCM Tools" or "Downloading Pre-Compiled PCM Tools") sections + +Running tests: + +* build PCM +* as root run "sh test/test.sh" + - Automated CI test workflow: https://github.com/intel/pcm/blob/03ad6b0228c9e8a8eb022708b53a61875b9447bc/.github/workflows/ci-test.yml#L40 diff --git a/_codeql_build_dir/bin/MAC_HOWTO.txt b/_codeql_build_dir/bin/MAC_HOWTO.txt new file mode 100644 index 00000000..4cdd2dfb --- /dev/null +++ b/_codeql_build_dir/bin/MAC_HOWTO.txt @@ -0,0 +1,64 @@ +Building and Installing + +Note: xcode is required to build the driver and dynamic library. + +Requirements +____________ +Building and installing requires make, cmake, gcc, and xcode. +It has been tested on the following system configurations: + OS X 12.0.1, Xcode 13.1, Apple LLVM compiler 13.0.0 + +Build PCM and MacMSRDriver +----------------- + mkdir build && cd build + cmake .. && cmake --build . + +PCM utilities will be located in build/bin folder, libraries libpcm.dylib and libPcmMsr.dylib - in build/lib. + +Automatic Install +----------------- + cd build + sudo make install + +Install command loads the driver, installs the library into /usr/lib and installs the library headers into /usr/include. +Also PCM utilities are installing to /usr/local/sbin. + +Manual Install +-------------- +Build steps are the same. +To install do the following: + 1) load the driver by running src/MacMSRDriver/kextload.sh + 2) copy build/lib/libPcmMsr.dylib to a location on your path (auto-install uses /usr/lib) + 3) copy src/MacMSRDriver/MSRKernel.h to a location on your path (auto-install uses /usr/include) + 4) copy src/MacMSRDriver/MSRAccessorPublic.h as MSRAccessor.h to a location on your path (auto-install uses /usr/include) + +kext Signatures +--------------- +As of OS X El Capitan, kexts must be signed. So after building the kext, kextload.sh may fail with: + + /System/Library/Extensions/PcmMsrDriver.kext failed to load - (libkern/kext) not loadable (reason unspecified); check the system/kernel logs for errors or try kextutil(8). + +In this event, you will need to either disable System Integrity Protection or sign the kext. +You can disable SIP by rebooting into Recovery (reboot, command-option-R), opening a shell, csrutil disable and reboot again. +Signing a kext is more involved. You can't self-sign and will first need to obtain a Developer ID from Apple: + + https://developer.apple.com/contact/kext/ + +With this ID, you can then sign your kext with codesign. + +PCM Execution +---------------------- +Now you can run ./pcm utility. +See description of other built utilities in LINUX_HOWTO.txt + +Logging/Debugging +---------------------- + +Sometimes you will get errors while running utilities that may come from the kernel, and you can use something like this DTrace script to correlate it with user-land behavior: + +$ sudo dtrace -n 'fbt:mach_kernel:_ZN*IOUser*:return /execname == "pcm"/ { @hgram[probefunc, arg1, ustack(20)] = count(); }' -c ./pcm + +Various commands that can help diagnose errors: + +$ kmutil log stream +$ kmutil inspect -b com.intel.driver.PcmMsr diff --git a/_codeql_build_dir/bin/PCM-EXPORTER.md b/_codeql_build_dir/bin/PCM-EXPORTER.md new file mode 100644 index 00000000..63efc0b6 --- /dev/null +++ b/_codeql_build_dir/bin/PCM-EXPORTER.md @@ -0,0 +1,36 @@ +# Intel® Performance Counter Monitor (Intel® PCM) Prometheus exporter + + +pcm-sensor-server is a collector exposing Intel processor metrics over http in JSON or Prometheus (exporter text based) format. Also [available as a docker container](DOCKER_README.md). + +Installation on target system to be analyzed: +1. [Build](https://github.com/intel/pcm#building-pcm-tools) or [download](https://github.com/intel/pcm#downloading-pre-compiled-pcm-tools) pcm tools +2. As root, start pcm-sensor-server: `sudo ./pcm-sensor-server` or as non-root https://github.com/intel/pcm#executing-pcm-tools-under-non-root-user-on-linux + +Alternatively one can start [pcm-sensor-server as a container from docker hub](DOCKER_README.md). + +Additional options: + +``` +$ ./pcm-sensor-server --help +Usage: ./pcm-sensor-server [OPTION] + +Valid Options: + -d : Run in the background + -p portnumber : Run on port (default port is 9738) + -r|--reset : Reset programming of the performance counters. + -D|--debug level : level = 0: no debug info, > 0 increase verbosity. + -R|--real-time : If possible the daemon will run with real time + priority, could be useful under heavy load to + stabilize the async counter fetching. + -h|--help : This information +``` + +The default output of pcm-sensor-server endpoint in a browser: + +![image](https://user-images.githubusercontent.com/25432609/226344012-8783e154-998e-48a7-a2ca-f2c42af9c843.png) + + +The PCM exporter can be used together with Grafana to obtain these Intel processor metrics (see [how-to](../scripts/grafana/README.md)): + +![pcm grafana output](https://raw.githubusercontent.com/wiki/intel/pcm/pcm-dashboard-full.png) diff --git a/_codeql_build_dir/bin/PCM-SENSOR-SERVER-README.md b/_codeql_build_dir/bin/PCM-SENSOR-SERVER-README.md new file mode 100644 index 00000000..16cbf717 --- /dev/null +++ b/_codeql_build_dir/bin/PCM-SENSOR-SERVER-README.md @@ -0,0 +1,47 @@ +# Global PCM Events + +| Event Name | Description | +|-----------------------------|-----------------------------------------------------------------------------| +| Measurement_Interval_in_us | How many us elapsed to complete the last measurement | +| Number_of_sockets | Number of CPU sockets in the system | + + +# Core Counters per socket + +OS_ID is the OS assigned ID of the logical CPU core and denotes the socket id, core id and thread id. + +The events below are followed by the same {socket="socket id",core="core id",thread="thread id"} as +the OS_ID of their section with source="socket/core/thread" appended that denotes what the quantity +of the event accounts for. + +For example Instructions_Retired_Any{socket="0",core="1",thread="1",source="core"} refers to +Instructions_Retired_Any for socket 0, core 1, thread 1, and accounts for the total instructions +retired of the specified core. + +| Event | Description | +|------------------------------------------------|--------------------------------------------------------------| +| Instructions_Retired_Any | Total number of Retired instructions | +| Clock_Unhalted_Thread | | +| Clock_Unhalted_Ref | Counts the number of reference cycles that the thread is | +| | not in a halt state. The thread enters the halt state when | +| | it is running the HLT instruction. This event is not | +| | affected by thread frequency changes but counts as if the | +| | thread is running at the maximum frequency all the time. | +| L3_Cache_Misses | Total number of L3 Cache misses | +| L3_Cache_Hits | Total number of L3 Cache hits | +| L2_Cache_Misses | Total number of L2 Cache misses | +| L2_Cache_Hits | Total number of L3 Cache hits | +| L3_Cache_Occupancy | Computes L3 Cache Occupancy | +| SMI_Count | SMI (System Management Interrupt) count | +| Invariant_TSC | Calculates the invariant TSC clocks (the invariant TSC | +| | means that the TSC continues at a fixed rate regardless of | +| | the C-state or frequency of the processor as long as the | +| | processor remains in the ACPI S0 state. | +| Thermal_Headroom | Celsius degrees before reaching TjMax temperature | +| CStateResidency | This is the percentage of time that the core (or the whole | +| | package) spends in a particular level of C-state | | + +References: + +https://software.intel.com/content/www/us/en/develop/articles/intel-performance-counter-monitor.html +https://software.intel.com/content/dam/develop/external/us/en/documents-tps/325384-sdm-vol-3abcd.pdf - Chapter 18 Performance Monitoring \ No newline at end of file diff --git a/_codeql_build_dir/bin/PCM_ACCEL_README.md b/_codeql_build_dir/bin/PCM_ACCEL_README.md new file mode 100644 index 00000000..0acde59c --- /dev/null +++ b/_codeql_build_dir/bin/PCM_ACCEL_README.md @@ -0,0 +1,121 @@ +## Purpose: + +Intel® Xeon® Scalable Processors, starting from the 4th Generation (codenamed Sapphire Rapids), feature accelerators, which include the Intel® In-Memory Analytics Accelerator (Intel® IAA), Intel® Data Streaming Accelerator (Intel® DSA), and Intel® QuickAssist Technology (Intel® QAT), among others. These accelerators are essential components that can enhance the performance of Intel architecture platforms. + +Although these accelerators and their associated software stacks can significantly contribute to data center system performance, customers and users often find it challenging to access and understand performance data such as utilization and throughput. This difficulty arises from the complexity of low-level hardware event sets, which require a deep understanding of the accelerator's hardware and software architecture. + +The pcm-accel tool addresses this challenge by sampling performance data from the accelerator hardware and presenting it to end users in an easy-to-understand format. Its goal is to enable users to quickly and accurately gain a high-level overview of performance or identify issues related to the accelerator, regardless of their level of expertise in the underlying technology. + +## Command syntax: + +pcm-accel [target] [options] + +#### the target parameter + +Notes: only 1 target is allowed to monitor. + +| target | Default | Description | +| ------ | ------- | ----------------------------- | +| -iaa | yes | Monitor the IAA accelerator. | +| -dsa | no | Monitor the DSA accelerator. | +| -qat | no | Monitor the QAT accelerator. | + +#### the options parameter + +Notes: multiple options is allowed. + +| options | Default | Description | +| ---------------------- | -------------------- | -------------------------------------------------------------------------------------------------------------------------- | +| -numa | no | Print NUMA node mapping instead of CPU socket location. | +| -evt=[cfg.txt] | opCode-x-y-accel.txt | Specify the event config file name as cfg.txt.
- x/y is cpu family is model id, for example 6/143 for Sapphire Rapids. | +| -silent | no | Silence information output and print only measurements | +| -csv[=file.csv] | no | Output compact CSV format to screen or a file in case filename is provided | +| -csv-delimiter=[value] | no | Set custom csv delimiter | +| -human-readable | no | Use human readable format for output (for csv only) | +| -i=[value] | 0 | Allow to determine number of iterations, default is 0(infinite loop) if not specified. | +| [interval] | 3 | Time interval in seconds (floating point number is accepted) to sample performance counters, default is 3s if not specified| + +#### Examples: + +This example prints IAA counters every second 10 times and exits + +> pcm-accel -iaa 1.0 -i=10  + +This example saves IAA counters twice a second save IAA counter values to test.log in CSV format + +> pcm-accel -iaa 0.5 -csv=test.log            + +This example prints IAA counters every 3 second in human-readable CSV format + +> pcm-accel -iaa -csv -human-readable + +## Prerequisites: + +Linux* OS: + +FreeBSD* OS: + +Windows OS: + +- Install and load the required accelerator driver(iaa/dsa, qat driver, etc). + +Notes: + +- QAT monitoring and NUMA node display feature is supported only on Linux OS! + +## Tool UI introduction: + +Common indicator(Column field): + +- Accelerator = Accelerator device id. +- Socket = CPU socket id where accelerator device is located. +- NUMA Node = NUMA node that accelerator device belongs to. +- Inbound_BW = Data throughput input to the accelerator device, unit is Bps(Bytes per second). +- Outbound_BW = Data throughput output from the accelerator device, unit is Bps(Bytes per second). + +Specific indicators related to IAA/DSA:  + +- ShareWQ_ReqNb = The number of request submitted to share work queue of accelerator. +- DedicateWQ_ReqNb = The number of request submitted to dedicate work queue of accelerator. + +![image](https://user-images.githubusercontent.com/25432609/224027332-8846dff6-f71e-4daa-a189-730e68c7e1b2.png) +![image](https://user-images.githubusercontent.com/25432609/224027445-2b08e89c-4653-4f39-971b-a7dc76bd7349.png) + +Specific indicators related to QAT: + +- util_comp0 = The utilization of the compress engine 0, unit is %.(Sapphire Rapids platform has 1 compress and 3 decompress engine per QAT device) + +- util_decomp0 = same as above for decompress engine 0. + +- util_decomp1 = same as above for decompress engine 1. + +- util_decomp2 = same as above for decompress engine 2. + +- util_xlt0 = same as above for translation engine 0. + + + ![image](https://user-images.githubusercontent.com/25432609/224027570-e433aeef-c2ed-418d-aa42-18eef0f1b645.png) + + +## Event config file: + +pcm-accel tool allows the user to customized the monitored performance events with the config file as advance feature. + +Customize fields of cfg file: + +- ev_sel and ev_cat field for IAA/DSA monitor event. +- ev_sel field for QAT monitor event.  +- multiplier/divider is for event data display calculation. +- vname is the event name string(column) displayed in the UI. + +Please refer to the spec or code to learn more about the event mapping if you want to customize it. + +- IAA/DSA: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification + +- QAT: please refer to the [mapping table in source code](https://github.com/intel/pcm/blob/f20013f7563714cf592d7a59f169c1ddee3cf8ba/src/cpucounters.cpp#L915) + + +Here is the content of the event cfg file(opCode-6-143-accel.txt as example) + +![image](https://user-images.githubusercontent.com/25432609/224027717-1dcdae9e-6701-4b6f-90a0-8108c4ea4550.png) + diff --git a/_codeql_build_dir/bin/PCM_IIO_README.md b/_codeql_build_dir/bin/PCM_IIO_README.md new file mode 100644 index 00000000..cc2e0ab6 --- /dev/null +++ b/_codeql_build_dir/bin/PCM_IIO_README.md @@ -0,0 +1,35 @@ +## Purpose: + +PCM-IIO tool monitors PCIe transactions with a breakdown per PCIe bus (IIO stack) and/or PCIe devices. + +## Tool UI introduction: + +Inbound (PCIe device DMA into system) metrics: + +* IB write (inbound write): the number of bytes per second that the PCIe device requested to write to main memory through DMA +* IB read (inbound read): the number of bytes per second that the PCIe device requested to read from main memory through DMA + +Outbound (CPU MMIO to the PCIe device) metrics: + +* OB read (outbound read): the number of bytes per second that the CPU requested to read from the PCIe device through MMIO (memory-mapped I/O) +* OB write (outbound write): the number of bytes per second that the CPU requested to write to the PCIe device through MMIO (memory-mapped I/O) + +IOMMU metrics: + +* IOTLB Lookup: IOTLB lookups per second +* IOTLB Miss: IOTLB misses per second +* Ctxt Cache Hit: Context cache hits per second +* 256T Cache Hit: Second Level Page Walk Cache Hits to a 256T page per second +* 512G Cache Hit: Second Level Page Walk Cache Hits to a 512G page per second +* 1G Cache Hit: Second Level Page Walk Cache Hits to a 1G page per second +* 2M Cache Hit: Second Level Page Walk Cache Hits to a 2M page per second +* IOMMU Mem Access: IOMMU memory accesses per second + +Sample output: + +![image](https://github.com/user-attachments/assets/e8cce396-b210-49d5-ac95-dc43f9ae69d3) + +## Event config file: + +pcm-iio tool allows the user to customize the performance events with a config file as an advanced feature. The event config files are in opCode-x-y.txt files where x/y is cpu family is model id, for example 6/143 for Sapphire Rapids. + diff --git a/_codeql_build_dir/bin/PCM_RAW_README.md b/_codeql_build_dir/bin/PCM_RAW_README.md new file mode 100644 index 00000000..585e0b35 --- /dev/null +++ b/_codeql_build_dir/bin/PCM_RAW_README.md @@ -0,0 +1,251 @@ +-------------------------------------------------------------------------------- +PCM Raw Utility +-------------------------------------------------------------------------------- + +Disclaimer: in contrast to other PCM utilities this one is for expert usage only. + +*pcm-raw* allows to collect arbitrary core and uncore PMU events by providing raw PMU event ID encoding. It can become handy if other low-level PMU tools (e.g. emon, Linux perf) can not be used for some reason. For example: +- emon kernel driver is not compatible with the currently used Linux kernel or operating system +- loading emon Linux kernel driver is forbidden due to system administration policies +- Linux kernel is too old to support modern processor PMU and can not be upgraded + +Currently supported PMUs: core, m3upi, upi(ll)/qpi(ll), imc, m2m, pcu, cha/cbo, iio, ubox + +Recommended usage (as privileged/root user): +1. Install VTune which also contains emon (emon/sep driver installation is not needed): [free download](https://software.intel.com/content/www/us/en/develop/tools/vtune-profiler.html) +2. Run emon with `--dry-run -m` options to obtain raw PMU event encodings for event of interest. For example: +``` +# emon -C BR_MISP_RETIRED.ALL_BRANCHES,UNC_CHA_CLOCKTICKS,UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0,UNC_UPI_TxL_FLITS.NON_DATA --dry-run -m +Event Set 0 + BR_MISP_RETIRED.ALL_BRANCHES (PerfEvtSel0 (0x186) = 0x00000000004300c5) + CC=ALL PC=0x0 UMASK=0x0 E=0x1 INT=0x0 INV=0x0 CMASK=0x0 AMT=0x0 +cha Uncore Event Set 0 + UNC_CHA_CLOCKTICKS (CHA Counter 0 (0xe01) = 0x0000000000400000) + +qpill Uncore Event Set 0 + UNC_UPI_TxL_FLITS.NON_DATA (QPILL Counter 0 (0x350) = 0x0000000000409702) + +iio Uncore Event Set 0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 (IIO Counter 0 (0xa48) = 0x0000701000400183) +``` +3. Run *pcm-raw* by specifying the obtained raw event encodings to collect into csv file. Example: +``` +pcm-raw -e core/config=0x00000000004300c5,name=BR_MISP_RETIRED.ALL_BRANCHES -e cha/config=0x0000000000400000,name=UNC_CHA_CLOCKTICKS -e qpi/config=0x0000000000409702,name=UNC_UPI_TxL_FLITS.NON_DATA -e iio/config=0x0000701000400183,name=UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 -csv=out.csv +``` +4. View/process the csv file using your favorite method. For example just open it in Excel. + +-------------------------------------------------------------------------------- +Collecting Register Values +-------------------------------------------------------------------------------- + +pcm-raw supports collecting raw MSR and PCICFG (CSR) register values. The syntax is described below: + +Model Specific Registers (MSRs): + +``` +package_msr/config=,config1=[,name=] +``` + +static_or_freerun encoding: +* 0 : static (last value reported in csv) +* 1 : freerun (delta to last value reported in csv) + +Examples: +``` +package_msr/config=0x34,config1=0,name=SMI_COUNT +thread_msr/config=0x10,config1=1,name=TSC_DELTA +thread_msr/config=0x10,config1=0,name=TSC +``` + +If the name is not specified the first event will show up as package_msr:0x34:static, with the name it will show up as SMI_COUNT in csv. + +PCI Configuration Registers - PCICFG (CSR): + +``` +pcicfg/config=,config1=,config2=,width=[,name=] +``` + +* dev_id: Intel PCI device id where the register is located +* offset: offset of the register +* static_or_freerun: same syntax as for MSR registers +* width: register width in bits (16,32,64) + +Example: + +``` +pcicfg/config=0xe20,config1=0x180,config2=0x0,width=32,name=CHANERR_INT +``` +From: https://www.intel.la/content/dam/www/public/us/en/documents/datasheets/xeon-e7-v2-datasheet-vol-2.pdf + +MMIO Registers: + +``` +mmio/config=,config1=,config2=,config3=[,config4=],width=[,name=] +``` + +The MEMBAR is computed by logically ORing the result of membar_bits1 and membar_bits1 computation described below (PCICFG read + bit extraction and shift). The final MMIO register address = MEMBAR + offset. + +* width: register width in bits (16,32,64) +* dev_id: Intel PCI device id where the membar address registers are located +* membar_bits1: mmioBase register bits to compute membar (base address) + - bits 0-15 : PCICFG register offset to read membar1 bits + - bits 16-23: source position of membar bits in the PCICFG register + - bits 24-31: number of bits + - bits 32-39: destination bit position in the membar +* membar_bits2: mmioBase register bits to compute membar (base address), can be zero if only membar_bits1 is sufficient for locating the register. + - bits 0-15 : PCICFG register offset to read membar2 bits + - bits 16-23: source position of membar bits in the PCICFG register + - bits 24-31: number of bits + - bits 32-39: destination bit position in the membar +* offset: offset of the MMIO register relative to the membar +* static_or_freerun: same syntax as for MSR registers + +Example (Icelake server iMC PMON MMIO register read): + +``` +mmio/config=0x3451,config1=0x22808,config2=1,config3=0x171D0000D0,config4=0x0c0b0000d8,width=64 +``` + +TPMI Registers: + +TPMI ([Topology Aware Register and PM Capsule Interface](https://github.com/intel/tpmi_power_management)) can be read with pcm-raw as follows: + +``` +tpmi/config=,config1=,config2=[,name=] +``` + +* tpmi_id: TPMI id +* offset: offset of the register +* static_or_freerun: same syntax as for MSR registers + +Example: + +``` +tpmi/config=0x2,config1=0x18,name=BHS_UFS_CONTROL +``` + +From: https://github.com/intel/tpmi_power_management/blob/main/UFS_TPMI_public_disclosure_FINAL_rev4.pdf + +-------------------------------------------------------------------------------- +Collecting Events By Names From Event Lists (https://github.com/intel/perfmon/) +-------------------------------------------------------------------------------- + +pcm-raw can also automatically lookup the events from the json event lists (https://github.com/intel/perfmon/) and translate them to raw encodings itself. To make this work you need to checkout PCM with simdjson submodule: + +* use git clone --recursive flag when cloning pcm repository, or +* update submodule with command `git submodule update --init --recursive`, or +* download simdjson library in the PCM source directory and recompile PCM: + +1. change to PCM 'src/' directory +2. git clone https://github.com/simdjson/simdjson.git +3. re-compile pcm + +Example of usage (on Intel Xeon Scalable processor): + +``` +pcm-raw -tr -e INST_RETIRED.ANY -e CPU_CLK_UNHALTED.THREAD -e CPU_CLK_UNHALTED.REF_TSC -e LD_BLOCKS.STORE_FORWARD -e UNC_CHA_CLOCKTICKS -e UNC_M_CAS_COUNT.RD +``` + +or with event groups specified in event_file.txt (with event multiplexing): + +``` +pcm-raw -tr -el event_file.txt +``` + +where event_file.txt contains event groups separated by a semicolon: + +``` +# group 1 +INST_RETIRED.ANY +CPU_CLK_UNHALTED.REF_TSC +CPU_CLK_UNHALTED.THREAD +DTLB_LOAD_MISSES.STLB_HIT +L1D_PEND_MISS.PENDING_CYCLES_ANY +MEM_INST_RETIRED.LOCK_LOADS +UOPS_EXECUTED.X87 +UNC_CHA_DIR_LOOKUP.SNP +UNC_CHA_DIR_LOOKUP.NO_SNP +UNC_M_CAS_COUNT.RD +UNC_M_CAS_COUNT.WR +UNC_UPI_CLOCKTICKS +UNC_UPI_TxL_FLITS.ALL_DATA +UNC_UPI_TxL_FLITS.NON_DATA +UNC_UPI_L1_POWER_CYCLES +; +# group 2 +INST_RETIRED.ANY +CPU_CLK_UNHALTED.REF_TSC +CPU_CLK_UNHALTED.THREAD +OFFCORE_REQUESTS_BUFFER.SQ_FULL +MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT +MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM +MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS +UNC_CHA_DIR_UPDATE.HA +UNC_CHA_DIR_UPDATE.TOR +UNC_M2M_DIRECTORY_UPDATE.ANY +UNC_M_CAS_COUNT.RD +UNC_M_CAS_COUNT.WR +UNC_M_PRE_COUNT.PAGE_MISS +UNC_UPI_TxL0P_POWER_CYCLES +UNC_UPI_RxL0P_POWER_CYCLES +UNC_UPI_RxL_FLITS.ALL_DATA +UNC_UPI_RxL_FLITS.NON_DATA +; +``` + +Sample csv output (date,time,event_name,milliseconds_between_samples,TSC_cycles_between_samples,unit0_event_count,unit1_event_count,unit2_event_count,...): + +``` +2021-09-27,00:07:40.507,UNC_CHA_DIR_LOOKUP.SNP,1000,2102078418,76,70,56,91,88,75,76,158,74,60,77,81,75,74,71,95,99,95,125,87,68,136,54,91,65,84,69,46,75,100,92,68,67,70,68,80,72,88,80,76,130,71,102,98,79,73,71,109 +2021-09-27,00:07:40.507,UNC_CHA_DIR_LOOKUP.NO_SNP,1000,2102078418,1218,1280,1187,1310,1268,1287,1282,1331,1265,1267,1300,1270,1258,1307,1289,1300,1410,1378,1312,1316,1367,1337,1332,1317,1584,1519,1569,1557,1483,1537,1545,1520,1562,1527,1575,1540,1530,1581,1476,1525,1610,1680,1581,1657,1565,1613,1596,1600 +2021-09-27,00:07:40.507,INST_RETIRED.ANY,1000,2102078418,705400,44587,45923,238392,53910,69547,46644,46172,44740,44732,45692,44864,46105,45352,45057,217052,46511,46671,46893,46459,53739,47021,114133,46339,61649,59027,142096,48048,98178,48288,162122,474329,48046,49795,78239,425635,105512,69933,49827,48913,71549,48451,294858,312316,149586,540477,49115,55144,46788,61681,82964,81127,116227,85776,453369,145979,81007,82269,83580,73595,73355,73751,72599,47169,47767,48191,48131,48359,48621,67664,48227,532184,49686,48704,324264,48539,48795,48609,60275,518368,116077,163734,526815,50650,140337,666605,47935,1368049,47243,337542,47153,46882,46925,62373,70186,466927 +2021-09-27,00:07:40.507,CPU_CLK_UNHALTED.REF_TSC,1000,2102078418,3618636,384720,589092,2143512,766752,724164,803124,627312,541548,538188,534324,509964,535164,527436,529284,1366176,488124,491820,533148,543900,608580,577920,1145172,602196,919632,824544,1429344,692916,1092756,700644,1298640,2487156,736344,841344,1324008,1855476,1260084,1104768,658308,5805324,851424,766080,1909740,2170392,1313592,3986892,683844,986832,659064,642432,682668,772128,1076628,710220,2514876,1085112,715344,700812,676452,594468,577668,590856,574056,597996,525336,551460,548520,561624,569352,741468,623196,3124212,592032,596400,2265312,556584,593124,546756,766752,2547216,1047396,1280160,2704884,525336,1200444,3255000,497700,13643700,481572,1601040,515592,523740,503664,854280,603120,2305128 +2021-09-27,00:07:40.507,CPU_CLK_UNHALTED.THREAD,1000,2102078418,1723000,183219,280560,1020631,365140,344897,382467,298699,257868,256243,254471,242757,254794,251172,252091,650377,232442,234209,253807,259024,289817,275179,545244,286717,437888,392646,680513,329759,520244,333662,618356,1184347,350594,400648,630580,1517122,599939,525847,313441,2765951,405441,364827,909395,1033366,625655,1898427,325614,881026,312798,305884,325245,367890,512845,338440,1197524,516836,341497,334581,322975,283138,275031,281300,273347,284616,250171,262581,261182,267455,271097,353013,296757,1487751,282516,283651,1076725,265489,282845,260889,365411,1212743,498705,611118,1287439,360493,571158,1549944,236616,6499483,229820,762766,245338,248648,239640,406676,287582,1714659 +2021-09-27,00:07:40.507,DTLB_LOAD_MISSES.STLB_HIT,1000,2102078418,10093,1178,1186,2593,1184,1356,1182,1201,1187,1200,1191,1179,1189,1179,1177,1444,1218,1205,1158,1183,1216,1190,1789,1184,1388,1347,2207,1384,1566,1352,1541,3221,1374,1398,1580,11223,1690,1427,1398,1356,1531,1388,3429,3567,2136,2639,1354,1393,1181,1188,1457,1456,1801,1437,4698,1697,1426,1434,1418,1452,1396,1394,1434,1164,1349,1349,1356,1318,1354,1528,1349,18546,1168,1160,8935,1166,1172,1167,1194,4432,1801,2341,3152,1190,1777,4328,1178,4396,1170,1939,1199,1150,1158,1197,1187,12441 +2021-09-27,00:07:40.507,L1D_PEND_MISS.PENDING_CYCLES_ANY,1000,2102078418,682630,81530,114229,363299,169260,134931,441644,183870,89947,95379,98135,81156,75366,77990,78734,178321,52738,53883,57241,56306,65514,94824,152070,227164,87723,80980,300491,70675,148506,70130,173723,628031,142178,161405,503099,383743,255465,317627,67134,1509172,105102,242908,300344,336683,157280,555052,84017,615357,526290,88531,117674,387708,192129,157226,451213,201430,103646,106302,112452,86251,83203,82880,80239,189044,72389,73820,75135,70746,84963,106517,168907,249006,117006,109389,320326,98291,168531,100734,206075,647276,167155,154684,495947,359092,257614,322235,78189,1473756,148139,278653,308380,343576,166510,556816,90475,306546 +2021-09-27,00:07:40.507,MEM_INST_RETIRED.LOCK_LOADS,1000,2102078418,3462,231,235,1159,259,277,239,237,236,238,236,239,238,237,237,1114,237,237,238,237,265,237,555,237,277,278,542,237,431,240,389,906,239,238,385,3973,435,280,238,238,401,238,847,1238,604,1948,238,238,235,275,266,267,428,277,1287,399,271,277,272,239,240,239,239,237,237,237,237,237,238,347,237,4266,238,238,1174,238,238,238,270,1361,526,697,1101,238,615,2172,238,4276,236,642,236,237,236,275,299,2842 +2021-09-27,00:07:40.507,UOPS_EXECUTED.X87,1000,2102078418,1152,12,13,496,46,17,27,12,11,13,10,14,11,27,12,1591,11,10,11,13,23,11,257,12,64,52,216,31,231,31,1668,5944,31,30,85,710,101,54,34,41,100,33,1852,1561,423,2348,28,46,14,23,155,57,82,172,2776,281,19,52,107,18,36,18,19,14,11,10,10,10,26,57,10,108,31,33,151,31,32,30,63,3700,361,509,4610,31,396,1814,31,5607,33,4175,31,30,32,47,78,471 +2021-09-27,00:07:40.507,UNC_M_CAS_COUNT.RD,1000,2102078418,37565,33584,0,0,0,0,40306,0,37373,0,0,0 +2021-09-27,00:07:40.507,UNC_M_CAS_COUNT.WR,1000,2102078418,58994,53007,0,0,0,0,25088,0,21901,0,0,0 +2021-09-27,00:07:40.507,UNC_UPI_CLOCKTICKS,1000,2102078418,1300347171,1300351441,1200328715,1300297715,1300303139,1200283803 +2021-09-27,00:07:40.507,UNC_UPI_TxL_FLITS.ALL_DATA,1000,2102078418,132768,150840,0,285147,269190,0 +2021-09-27,00:07:40.507,UNC_UPI_TxL_FLITS.NON_DATA,1000,2102078418,298203,319302,0,293389,264875,0 +2021-09-27,00:07:40.507,UNC_UPI_L1_POWER_CYCLES,1000,2102078418,0,0,1200328715,0,0,1200283803 +``` +The unit can be logical core, memory channel, CHA, etc, depending on the event type. + + +Show events available for the processor on the system: +``` +pcm-raw -? +``` + +-------------------------------------------------------------------------------- +Low-level access to Intel PMT telemetry data +-------------------------------------------------------------------------------- + +pcm-raw can read raw telemetry data from Intel PMT (https://github.com/intel/Intel-PMT/). + +Syntax for a PMT raw telemetry counter: + +``` +pmt/config=,config1=,config2=,config3=[,name=] + +``` + +The fields are the values for the counter from the Intel PMT aggregator XML: + +* uniqueid : Intel PMT Telemetry unique identifier +* sampleID : sample ID of the counter +* sampleType counter encoding: + - 0 : Snapshot (last value reported in csv) + - non-zero : Counter (delta to last value reported in csv) +* lsb : lsb field +* msb : msb field + +Example for https://github.com/intel/Intel-PMT/blob/868049006ad2770a75e5fc7526fd0c4b22438e27/xml/SPR/OOBMSM/CORE/spr_aggregator.xml#L15428: +``` +pmt/config=0x87b6fef1,config1=770,config2=0,config3=32,config4=63,name="Temperature_histogram_range_5_(50.5-57.5C)_counter_for_core_0" +``` + +Current limitations: this feature (PMT access) is currently only available on Linux (with Intel PMT Linux driver). diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-4F-1.json new file mode 100644 index 00000000..3f1fcc2b --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-4F-1.json @@ -0,0 +1,122 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "AnyThread": {"Config": 0, "Position": 21, "Width": 1}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 2, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 6, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 10, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "TIDEnable": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "Filter0": {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0}, + "TID": {"Config": 1, "Position": 0, "Width": 6, "DefaultValue": 0}, + "State": {"Config": 1, "Position": 17, "Width": 7, "DefaultValue": 0}, + "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59}, + "OPC": {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0}, + "NC": {"Config": 2, "Position": 30, "Width": 1, "DefaultValue": 0}, + "ISOC": {"Config": 2, "Position": 31, "Width": 1, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "ha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "ubox" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-55-4.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-55-4.json new file mode 100644 index 00000000..9b08c471 --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-55-4.json @@ -0,0 +1,136 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "AnyThread": {"Config": 0, "Position": 21, "Width": 1}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 2, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 6, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 10, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "TIDEnable": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "Filter0": {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0}, + "TID": {"Config": 1, "Position": 0, "Width": 9, "DefaultValue": 0}, + "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "ubox" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 8}, + "FCMask": {"Config": 0, "Position": 44, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-6A-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-6A-0.json new file mode 100644 index 00000000..ee0d516d --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-6A-0.json @@ -0,0 +1,144 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed3" : { + "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "TIDEnable": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 9, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "ubox" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-86-5.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-86-5.json new file mode 100644 index 00000000..f564e4fa --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-86-5.json @@ -0,0 +1,103 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8E-C.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8E-C.json new file mode 100644 index 00000000..9955c1dc --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8E-C.json @@ -0,0 +1,57 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "AnyThread": {"Config": 0, "Position": 21, "Width": 1}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 2, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 6, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "AnyThread": {"Config": 0, "Position": 10, "Width": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8F-6.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8F-6.json new file mode 100644 index 00000000..0cc35641 --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8F-6.json @@ -0,0 +1,152 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed3" : { + "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "ubox" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AD-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AD-0.json new file mode 100644 index 00000000..d68375b7 --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AD-0.json @@ -0,0 +1,158 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed3" : { + "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex8" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex16" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AE-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AE-0.json new file mode 100644 index 00000000..d68375b7 --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AE-0.json @@ -0,0 +1,158 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed3" : { + "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex8" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex16" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AF-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AF-0.json new file mode 100644 index 00000000..e3b4a8ed --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AF-0.json @@ -0,0 +1,145 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex8" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex16" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-B6-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-B6-0.json new file mode 100644 index 00000000..e3b4a8ed --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-B6-0.json @@ -0,0 +1,145 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex8" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "pciex16" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-CF-1.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-CF-1.json new file mode 100644 index 00000000..0cc35641 --- /dev/null +++ b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-CF-1.json @@ -0,0 +1,152 @@ +{ + "core" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, + "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, + "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, + "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, + "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, + "Invert": {"Config": 0, "Position": 23, "Width": 1}, + "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, + "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, + "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, + "MSRIndex": { + "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, + "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, + "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, + "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} + } + }, + "fixed0" : { + "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed1" : { + "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed2" : { + "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} + }, + "fixed3" : { + "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, + "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, + "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, + "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, + "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} + } + }, + "cha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, + "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} + } + }, + "imc" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "xpi" : { + "__comment" : "this is for UPI LL and QPI LL uncore PMUs", + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} + } + }, + "m2m" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, + "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} + } + }, + "m3upi" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "mdf" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "irp" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "ubox" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, + "iio" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, + "PortMask": {"Config": 0, "Position": 36, "Width": 12}, + "FCMask": {"Config": 0, "Position": 48, "Width": 3} + } + } +} diff --git a/_codeql_build_dir/bin/STARS.md b/_codeql_build_dir/bin/STARS.md new file mode 100644 index 00000000..3755531f --- /dev/null +++ b/_codeql_build_dir/bin/STARS.md @@ -0,0 +1,3 @@ +## Git Hub Star History for PCM Project + +[![Star History Chart](https://api.star-history.com/svg?repos=intel/pcm&type=Date)](https://star-history.com/#intel/pcm&Date) diff --git a/_codeql_build_dir/bin/WINDOWS_HOWTO.md b/_codeql_build_dir/bin/WINDOWS_HOWTO.md new file mode 100644 index 00000000..97a880d5 --- /dev/null +++ b/_codeql_build_dir/bin/WINDOWS_HOWTO.md @@ -0,0 +1,103 @@ +**COMPILATION AND INSTALLATION OF UTILITIES** + +_For support of systems with more than _**_64_**_ logical cores you need to compile all binaries below in “_**_x64_**_” platform mode (not the default “_**_Win32_**_” mode)._ + +## Command-line utility + +1. Follow [Compile the Windows MSR driver](#compile-the-windows-msr-driver) to compile the Windows MSR driver (msr.sys). For Windows 7 and later versions you have to [sign the msr.sys driver additionally](#sign-the-windows-msr-driver). To enable loading test-signed drivers on the system: in administrator cmd console run `bcdedit /set testsigning on` and reboot. + +2. Build the *pcm.exe* utility: + ``` + cmake -B build + cmake --build build --config Release --parallel + ``` + alternatively you can perform `cmake -B build`, open *PCM.sln* form *build* folder in and build required project in Visual Studio. + .exe and .dll files will be located in *build\bin\Release* folder +3. As Administrator create PCM directory in Windows "Program Files" directory (e.g. `C:\Program Files (x86)\PCM\`) +4. As Administrator copy the msr.sys driver and pcm.exe into the PCM directory +5. Run pcm.exe utility from the PCM directory as Administrator + +For Windows 7+ and Windows Server 2008+ R2 the PCM utilities need to be run as Administrator: + +Alternatively you can achieve the same using the “Properties” Windows menu of the executable (“Privilege level” setting in the “Compatibility” tab): Right mouse click -> Properties -> Compatibility -> Privilege level -> Set “Run this program as an administrator”. + +![Screenshot](run-as-administrator.png) + +If you are getting the error `Starting MSR service failed with error 3 The system cannot find the path specified.` try to uninstall the driver by running `pcm --uninstallDriver` and optionally reboot the system. + +## Graphical Perfmon front end + +1. Follow [Compile the windows MSR driver](#compile-the-windows-msr-driver) to compile the windows MSR driver (msr.sys). For Windows 7 and later versions you have to sign the msr.sys driver additionally ([http://msdn.microsoft.com/en-us/library/ms537361(VS.85).aspx](http://msdn.microsoft.com/en-us/library/ms537361(VS.85).aspx)). + +2. Copy msr.sys into the c:\windows\system32 directory + +3. Build pcm-lib.dll using Microsoft Visual Studio or cmake + +4. Build 'PCM-Service.exe' using Microsoft Visual Studio or cmake + +5. Copy PCM-Service.exe, PCM-Service.exe.config, and pcm-lib.dll files into the PCM sub-directory in Windows "Program Files" directory (see above) + +The config file enables support for legacy security policy. Without this configuration switch, you will get an exception like this: + +Unhandled Exception: System.NotSupportedException: This method implicitly uses CAS policy, which has been obsoleted by the .NET Framework. + +6. With administrator rights execute '"PCM-Service.exe" -Install' from this directory + +7. With administrator rights execute 'net start pcmservice' + +8. Start perfmon and find new PCM\* counters + +If you do not want or cannot compile the msr.sys driver you might use a third-party open source WinRing0 driver instead (experimental only, for testing environments only). +Instructions: + +1. Download the free RealTemp utility package from [http://www.techpowerup.com/realtemp/](http://www.techpowerup.com/realtemp/) or any other free utility that uses the open-source WinRing0 driver (like OpenHardwareMonitor [http://code.google.com/p/open-hardware-monitor/downloads/list](http://code.google.com/p/open-hardware-monitor/downloads/list)). +2. Copy WinRing0.dll, WinRing0.sys, WinRing0x64.dll, WinRing0x64.sys files from there into the PCM.exe binary location, into the PCM-Service.exe location and into c:\windows\system32 +3. Run the PCM.exe tool and/or go to step 6 (perfmon utility). + +## Compile the Windows MSR driver + +1. Download Visual Studio ([Visual Studio download](https://visualstudio.microsoft.com/downloads/)). +When you install Visual Studio, also install related packages: + - under `Workloads`, select `Desktop development with C++` +(select `C++ CMake tools for Windows` in this workload) and `.NET desktop development`. + - under `Individual components`, search `Libs for Spectre` and select `MSVC v143 - VS +2022 C++ x64/x86 Spectre-mitigated libs(Latest)`. + +2. Download and install SDK ([windows-sdk](https://developer.microsoft.com/en-us/windows/downloads/windows-sdk/)) + +3. Download and install WDK ([windows-wdk](https://learn.microsoft.com/en-us/windows-hardware/drivers/download-the-wdk)). Please select `Install Windows Driver Kit Visual Studio extension` when you install WDK. + +4. Open **a terminal in Visual Studio**, then go to `src\WinMSRDriver`, and run the following command to compile the driver. Then you will see `MSR.sys` in `src\WinMSRDriver\x64\Release`. + ``` + MSBuild.exe MSR.vcxproj -property:Configuration=Release -property:Platform=x64 + ``` + +## Sign the Windows MSR driver + +Run the following in PowerShell, in the directory where `MSR.sys` is located: + +``` +$cert = New-SelfSignedCertificate -Type CodeSigning -Subject "CN=TestCert" -CertStoreLocation "Cert:\CurrentUser\My" -KeyExportPolicy Exportable +$pwd = Read-Host -Prompt "Enter the password for the PFX file" -AsSecureString +Export-PfxCertificate -Cert $cert -FilePath TestCert.pfx -Password $pwd +signtool sign /fd SHA256 /f TestCert.pfx /p ([Runtime.InteropServices.Marshal]::PtrToStringAuto([Runtime.InteropServices.Marshal]::SecureStringToBSTR($pwd))) /t http://timestamp.digicert.com MSR.sys +``` + +Afterwards, double-click `TestCert.pfx`. Install to "Current User" and when able to pick "Place all ...", browse for "Trusted Root Certification Authorities". + +## Known limitations + +Running PCM.exe under Cygwin shell is possible, but due to incompatibilities of signals/events handling between Windows and Cygwin, the PCM may not cleanup PMU configuration after Ctrl+C or Ctrl+Break pressed. The subsequent run of PCM will require to do PMU configuration reset, so adding -r command line option to PCM will be required. + +PCM-Service FAQ: +Q: Help my service won't start, what can I do to diagnose the problem? +A: Please check in the Windows Application "Event Viewer" under "Windows Logs" and then under "Application". PCM-Service writes its messages here, just look for errors. If you can't figure it out how to fix it, create a bug report and make sure to paste the text from the Event Viewer in the bug report so we can diagnose the issue. + +Q: I see a message in the Events Viewer that PCM-Service does not start because the "custom counter file view is out of memory", how do I fix this? +A: Despite that PCM-Service is reserving more memory than the standard 512kB this error can still occur if there is another application that uses performance counters is initialized before PCM. There are two options: +1. identify the application or service that starts before PCM-Service and stop or disable it and consequently reboot and try again +2. [find your machine.config file](https://stackoverflow.com/questions/2325473/where-is-machine-config) and add +` + +` +to that file diff --git a/_codeql_build_dir/bin/generate_summary_readme.md b/_codeql_build_dir/bin/generate_summary_readme.md new file mode 100644 index 00000000..f202a926 --- /dev/null +++ b/_codeql_build_dir/bin/generate_summary_readme.md @@ -0,0 +1,25 @@ +Step 1 + +```pip3 install pipreqs``` + +Step 2 + +```cd /path/to/pcm/scripts``` + +Step 3 + +```python3 -m pipreqs.pipreqs --encoding utf-8 .``` + +Step 4 + +```pip3 install -r requirements.txt``` + +Step 5 + +```python3 generate_summary.py --help``` + +Step 6 + +```python3 generate_summary.py -{argument1} -{argument2} ....-{argumentN}``` + + diff --git a/_codeql_build_dir/bin/license.txt b/_codeql_build_dir/bin/license.txt new file mode 100644 index 00000000..976fed2c --- /dev/null +++ b/_codeql_build_dir/bin/license.txt @@ -0,0 +1,28 @@ +This notice belongs to the code originating from "Intel Performance Counter Monitor". + +Copyright (c) 2009-2016, Intel Corporation +All rights reserved. +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + diff --git a/_codeql_build_dir/bin/opCode-6-106.txt b/_codeql_build_dir/bin/opCode-6-106.txt new file mode 100644 index 00000000..2bd1077e --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-106.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-108.txt b/_codeql_build_dir/bin/opCode-6-108.txt new file mode 100644 index 00000000..2bd1077e --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-108.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-134.txt b/_codeql_build_dir/bin/opCode-6-134.txt new file mode 100644 index 00000000..4c8e744f --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-134.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total \ No newline at end of file diff --git a/_codeql_build_dir/bin/opCode-6-143-accel.txt b/_codeql_build_dir/bin/opCode-6-143-accel.txt new file mode 100644 index 00000000..8c6429a7 --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-143-accel.txt @@ -0,0 +1,20 @@ +# IAA events +ctr=0,ev_sel=0x1,ev_cat=0x1,en=1,multiplier=32,divider=1,hname=IAA,vname=Inbound_BW(Bps) +ctr=1,ev_sel=0x2,ev_cat=0x1,en=1,multiplier=512,divider=1,hname=IAA,vname=Outbound_BW(Bps) +ctr=2,ev_sel=0x5,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=IAA,vname=ShareWQ_ReqNb +ctr=3,ev_sel=0x10,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=IAA,vname=DedicateWQ_ReqNb + +# DSA events +ctr=0,ev_sel=0x1,ev_cat=0x1,en=1,multiplier=32,divider=1,hname=DSA,vname=Inbound_BW(Bps) +ctr=1,ev_sel=0x2,ev_cat=0x1,en=1,multiplier=32,divider=1,hname=DSA,vname=Outbound_BW(Bps) +ctr=2,ev_sel=0x5,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=DSA,vname=ShareWQ_ReqNb +ctr=3,ev_sel=0x10,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=DSA,vname=DedicateWQ_ReqNb + +# QAT events +ctr=0,ev_sel=0x6,ev_cat=0x1,en=1,multiplier=1048576,divider=1,hname=QAT,vname=Inbound_BW(Bps) +ctr=1,ev_sel=0x7,ev_cat=0x1,en=1,multiplier=1048576,divider=1,hname=QAT,vname=Outbound_BW(Bps) +ctr=2,ev_sel=0xB,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_comp0(%) +ctr=3,ev_sel=0xC,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_decomp0(%) +ctr=4,ev_sel=0xD,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_decomp1(%) +ctr=5,ev_sel=0xE,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_decomp2(%) +ctr=6,ev_sel=0xF,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_xlt0(%) diff --git a/_codeql_build_dir/bin/opCode-6-143.txt b/_codeql_build_dir/bin/opCode-6-143.txt new file mode 100644 index 00000000..7a4dfc3d --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-143.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-173.txt b/_codeql_build_dir/bin/opCode-6-173.txt new file mode 100644 index 00000000..821de1c2 --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-173.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-174.txt b/_codeql_build_dir/bin/opCode-6-174.txt new file mode 100644 index 00000000..821de1c2 --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-174.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-175.txt b/_codeql_build_dir/bin/opCode-6-175.txt new file mode 100644 index 00000000..821de1c2 --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-175.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-182.txt b/_codeql_build_dir/bin/opCode-6-182.txt new file mode 100644 index 00000000..821de1c2 --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-182.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-207.txt b/_codeql_build_dir/bin/opCode-6-207.txt new file mode 100644 index 00000000..7a4dfc3d --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-207.txt @@ -0,0 +1,45 @@ +#Clockticks +#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 +ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 +ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 +# IOMMU events +ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total +ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-85.txt b/_codeql_build_dir/bin/opCode-6-85.txt new file mode 100644 index 00000000..73d93176 --- /dev/null +++ b/_codeql_build_dir/bin/opCode-6-85.txt @@ -0,0 +1,26 @@ +# Inbound (PCIe device DMA into system) payload events +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part3 (4th x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part1 (2nd x4) +ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part3 (4th x4) +# Outbound (CPU MMIO to the PCIe device) payload events +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part3 (4th x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part1 (2nd x4) +ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4) +ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part3 (4th x4) +# VTd events +ctr=0,unit=iio,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Hit,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d CTXT Miss,vname=Total +ctr=3,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d L1 Miss,vname=Total +ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=4,fc_mask=0x7,multiplier=1,hname=VT-d L2 Miss,vname=Total +ctr=1,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=VT-d L3 Miss,vname=Total +ctr=2,unit=iio,ev_sel=0x84,umask=0x04,en=1,ch_mask=0x10,fc_mask=0x7,multiplier=1,hname=VT-d Mem Read,vname=Total diff --git a/_codeql_build_dir/bin/pcm-client b/_codeql_build_dir/bin/pcm-client new file mode 100755 index 0000000000000000000000000000000000000000..e7621d6aabd89f781bdd2d1a3335916e24cecc97 GIT binary patch literal 39224 zcmeHw33OCN_V-IVFNC#&isHENL_kmp3Hu_N5CYv0FoqzwK-1}T7RhG1!{Vp}LzK2@ zjE)QHsEi}X%($R}B7zeI6WkHSL7h=XTwV(!K@@OM`}^H`Ro(So(g=S4^FQDD4lk!u zb#GPOx?A0`ZojijiQyHmr#s6N)xk@tNB!)A} zGmQkL#<45WoThNR4JozjNtt%ivkkN&Qo$jm)Gpr9pEnSxl4{hXb}D5x`iDbf|D$PW zssW2sZpZqo=JhS<+AaoOq;fmbP5SLdxixKN%qWUOD1`G#>Y{dzWkx$|n#%PlQqi1v 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a source file +pcm-iio-pmu.cpp.i: + cd /home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir && $(MAKE) $(MAKESILENT) -f src/CMakeFiles/PCM_STATIC.dir/build.make src/CMakeFiles/PCM_STATIC.dir/pcm-iio-pmu.cpp.i + cd /home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir && $(MAKE) $(MAKESILENT) -f src/CMakeFiles/PCM_STATIC_SILENT.dir/build.make src/CMakeFiles/PCM_STATIC_SILENT.dir/pcm-iio-pmu.cpp.i +.PHONY : pcm-iio-pmu.cpp.i + +pcm-iio-pmu.s: pcm-iio-pmu.cpp.s +.PHONY : pcm-iio-pmu.s + +# target to generate assembly for a file +pcm-iio-pmu.cpp.s: + cd /home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir && $(MAKE) $(MAKESILENT) -f src/CMakeFiles/PCM_STATIC.dir/build.make src/CMakeFiles/PCM_STATIC.dir/pcm-iio-pmu.cpp.s + cd /home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir && $(MAKE) $(MAKESILENT) -f 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- -/* Construct a string literal encoding the version number components. */ -#elif defined(COMPILER_VERSION_MAJOR) -char const info_version[] = { - 'I', 'N', 'F', 'O', ':', - 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', - COMPILER_VERSION_MAJOR, -# ifdef COMPILER_VERSION_MINOR - '.', COMPILER_VERSION_MINOR, -# ifdef COMPILER_VERSION_PATCH - '.', COMPILER_VERSION_PATCH, -# ifdef COMPILER_VERSION_TWEAK - '.', COMPILER_VERSION_TWEAK, -# endif -# endif -# endif - ']','\0'}; -#endif - -/* Construct a string literal encoding the internal version number. */ -#ifdef COMPILER_VERSION_INTERNAL -char const info_version_internal[] = { - 'I', 'N', 'F', 'O', ':', - 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', - 'i','n','t','e','r','n','a','l','[', - COMPILER_VERSION_INTERNAL,']','\0'}; -#elif defined(COMPILER_VERSION_INTERNAL_STR) -char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; -#endif - -/* Construct a string literal encoding the version number components. */ -#ifdef SIMULATE_VERSION_MAJOR -char const info_simulate_version[] = { - 'I', 'N', 'F', 'O', ':', - 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', - SIMULATE_VERSION_MAJOR, -# ifdef SIMULATE_VERSION_MINOR - '.', SIMULATE_VERSION_MINOR, -# ifdef SIMULATE_VERSION_PATCH - '.', SIMULATE_VERSION_PATCH, -# ifdef SIMULATE_VERSION_TWEAK - '.', SIMULATE_VERSION_TWEAK, -# endif -# endif -# endif - ']','\0'}; -#endif - -/* Construct the string literal in pieces to prevent the source from - getting matched. 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(((__VER__) / 100)*100)) -# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) -# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) -# endif - - -/* These compilers are either not known or too old to define an - identification macro. Try to identify the platform and guess that - it is the native compiler. */ -#elif defined(__hpux) || defined(__hpua) -# define COMPILER_ID "HP" - -#else /* unknown compiler */ -# define COMPILER_ID "" -#endif - -/* Construct the string literal in pieces to prevent the source from - getting matched. Store it in a pointer rather than an array - because some compilers will just produce instructions to fill the - array rather than assigning a pointer to a static array. */ -char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; -#ifdef SIMULATE_ID -char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; -#endif - -#ifdef __QNXNTO__ -char const* qnxnto = "INFO" ":" "qnxnto[]"; -#endif - -#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) -char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; -#endif - -#define STRINGIFY_HELPER(X) #X -#define STRINGIFY(X) STRINGIFY_HELPER(X) - -/* Identify known platforms by name. */ -#if defined(__linux) || defined(__linux__) || defined(linux) -# define PLATFORM_ID "Linux" - -#elif defined(__MSYS__) -# define PLATFORM_ID "MSYS" - -#elif defined(__CYGWIN__) -# define PLATFORM_ID "Cygwin" - -#elif defined(__MINGW32__) -# define PLATFORM_ID "MinGW" - -#elif defined(__APPLE__) -# define PLATFORM_ID "Darwin" - -#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) -# define PLATFORM_ID "Windows" - -#elif defined(__FreeBSD__) || defined(__FreeBSD) -# define PLATFORM_ID "FreeBSD" - -#elif defined(__NetBSD__) || defined(__NetBSD) -# define PLATFORM_ID "NetBSD" - -#elif defined(__OpenBSD__) || defined(__OPENBSD) -# define PLATFORM_ID "OpenBSD" - -#elif defined(__sun) || defined(sun) -# define PLATFORM_ID "SunOS" - -#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) -# define PLATFORM_ID "AIX" - -#elif defined(__hpux) || defined(__hpux__) -# define PLATFORM_ID "HP-UX" - -#elif defined(__HAIKU__) -# define PLATFORM_ID "Haiku" - -#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) -# define PLATFORM_ID "BeOS" - -#elif defined(__QNX__) || defined(__QNXNTO__) -# define PLATFORM_ID "QNX" - -#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) -# define PLATFORM_ID "Tru64" - -#elif defined(__riscos) || defined(__riscos__) -# define PLATFORM_ID "RISCos" - -#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) -# define PLATFORM_ID "SINIX" - -#elif defined(__UNIX_SV__) -# define PLATFORM_ID "UNIX_SV" - -#elif defined(__bsdos__) -# define PLATFORM_ID "BSDOS" - -#elif defined(_MPRAS) || defined(MPRAS) -# define PLATFORM_ID "MP-RAS" - -#elif defined(__osf) || defined(__osf__) -# define PLATFORM_ID "OSF1" - -#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) -# define PLATFORM_ID "SCO_SV" - -#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) -# define PLATFORM_ID "ULTRIX" - -#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) -# define PLATFORM_ID "Xenix" - -#elif defined(__WATCOMC__) -# if defined(__LINUX__) -# define PLATFORM_ID "Linux" - -# elif defined(__DOS__) -# define PLATFORM_ID "DOS" - -# elif defined(__OS2__) -# define PLATFORM_ID "OS2" - -# elif defined(__WINDOWS__) -# define PLATFORM_ID "Windows3x" - -# elif defined(__VXWORKS__) -# define PLATFORM_ID "VxWorks" - -# else /* unknown platform */ -# define PLATFORM_ID -# endif - -#elif defined(__INTEGRITY) -# if defined(INT_178B) -# define PLATFORM_ID "Integrity178" - -# else /* regular Integrity */ -# define PLATFORM_ID "Integrity" -# endif - -# elif defined(_ADI_COMPILER) -# define PLATFORM_ID "ADSP" - -#else /* unknown platform */ -# define PLATFORM_ID - -#endif - -/* For windows compilers MSVC and Intel we can determine - the architecture of the compiler being used. This is because - the compilers do not have flags that can change the architecture, - but rather depend on which compiler is being used -*/ -#if defined(_WIN32) && defined(_MSC_VER) -# if defined(_M_IA64) -# define ARCHITECTURE_ID "IA64" - -# elif defined(_M_ARM64EC) -# define ARCHITECTURE_ID "ARM64EC" - -# elif defined(_M_X64) || defined(_M_AMD64) -# define ARCHITECTURE_ID "x64" - -# elif defined(_M_IX86) -# define ARCHITECTURE_ID "X86" - -# elif defined(_M_ARM64) -# define ARCHITECTURE_ID "ARM64" - -# elif defined(_M_ARM) -# if _M_ARM == 4 -# define ARCHITECTURE_ID "ARMV4I" -# elif _M_ARM == 5 -# define ARCHITECTURE_ID "ARMV5I" -# else -# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) -# endif - -# elif defined(_M_MIPS) -# define ARCHITECTURE_ID "MIPS" - -# elif defined(_M_SH) -# define ARCHITECTURE_ID "SHx" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__WATCOMC__) -# if defined(_M_I86) -# define ARCHITECTURE_ID "I86" - -# elif defined(_M_IX86) -# define ARCHITECTURE_ID "X86" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) -# if defined(__ICCARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__ICCRX__) -# define ARCHITECTURE_ID "RX" - -# elif defined(__ICCRH850__) -# define ARCHITECTURE_ID "RH850" - -# elif defined(__ICCRL78__) -# define ARCHITECTURE_ID "RL78" - -# elif defined(__ICCRISCV__) -# define ARCHITECTURE_ID "RISCV" - -# elif defined(__ICCAVR__) -# define ARCHITECTURE_ID "AVR" - -# elif defined(__ICC430__) -# define ARCHITECTURE_ID "MSP430" - -# elif defined(__ICCV850__) -# define ARCHITECTURE_ID "V850" - -# elif defined(__ICC8051__) -# define ARCHITECTURE_ID "8051" - -# elif defined(__ICCSTM8__) -# define ARCHITECTURE_ID "STM8" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__ghs__) -# if defined(__PPC64__) -# define ARCHITECTURE_ID "PPC64" - -# elif defined(__ppc__) -# define ARCHITECTURE_ID "PPC" - -# elif defined(__ARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__x86_64__) -# define ARCHITECTURE_ID "x64" - -# elif defined(__i386__) -# define ARCHITECTURE_ID "X86" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__clang__) && defined(__ti__) -# if defined(__ARM_ARCH) -# define ARCHITECTURE_ID "ARM" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__TI_COMPILER_VERSION__) -# if defined(__TI_ARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__MSP430__) -# define ARCHITECTURE_ID "MSP430" - -# elif defined(__TMS320C28XX__) -# define ARCHITECTURE_ID "TMS320C28x" - -# elif defined(__TMS320C6X__) || defined(_TMS320C6X) -# define ARCHITECTURE_ID "TMS320C6x" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -# elif defined(__ADSPSHARC__) -# define ARCHITECTURE_ID "SHARC" - -# elif defined(__ADSPBLACKFIN__) -# define ARCHITECTURE_ID "Blackfin" - -#elif defined(__TASKING__) - -# if defined(__CTC__) || defined(__CPTC__) -# define ARCHITECTURE_ID "TriCore" - -# elif defined(__CMCS__) -# define ARCHITECTURE_ID "MCS" - -# elif defined(__CARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__CARC__) -# define ARCHITECTURE_ID "ARC" - -# elif defined(__C51__) -# define ARCHITECTURE_ID "8051" - -# elif defined(__CPCP__) -# define ARCHITECTURE_ID "PCP" - -# else -# define ARCHITECTURE_ID "" -# endif - -#else -# define ARCHITECTURE_ID -#endif - -/* Convert integer to decimal digit literals. */ -#define DEC(n) \ - ('0' + (((n) / 10000000)%10)), \ - ('0' + (((n) / 1000000)%10)), \ - ('0' + (((n) / 100000)%10)), \ - ('0' + (((n) / 10000)%10)), \ - ('0' + (((n) / 1000)%10)), \ - ('0' + (((n) / 100)%10)), \ - ('0' + (((n) / 10)%10)), \ - ('0' + ((n) % 10)) - -/* Convert integer to hex digit literals. */ -#define HEX(n) \ - ('0' + ((n)>>28 & 0xF)), \ - ('0' + ((n)>>24 & 0xF)), \ - ('0' + ((n)>>20 & 0xF)), \ - ('0' + ((n)>>16 & 0xF)), \ - ('0' + ((n)>>12 & 0xF)), \ - ('0' + ((n)>>8 & 0xF)), \ - ('0' + ((n)>>4 & 0xF)), \ - ('0' + ((n) & 0xF)) - -/* Construct a string literal encoding the version number. */ -#ifdef COMPILER_VERSION -char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; 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@echo "... depend" - @echo "... edit_cache" - @echo "... install" - @echo "... install/local" - @echo "... install/strip" - @echo "... list_install_components" - @echo "... package" - @echo "... package_source" - @echo "... rebuild_cache" - @echo "... PCM_SHARED" - @echo "... PCM_STATIC" - @echo "... PCM_STATIC_SILENT" - @echo "... c_example" - @echo "... c_example_shlib" - @echo "... client" - @echo "... daemon" - @echo "... daemon_alignment_test" - @echo "... pcm" - @echo "... pcm-accel" - @echo "... pcm-core" - @echo "... pcm-iio" - @echo "... pcm-latency" - @echo "... pcm-memory" - @echo "... pcm-mmio" - @echo "... pcm-msr" - @echo "... pcm-numa" - @echo "... pcm-pcicfg" - @echo "... pcm-pcie" - @echo "... pcm-power" - @echo "... pcm-raw" - @echo "... pcm-sensor" - @echo "... pcm-sensor-server" - @echo "... pcm-tpmi" - @echo "... pcm-tsx" - @echo "... urltest" -.PHONY : help - - - -#============================================================================= -# Special targets to cleanup operation of make. - -# Special rule to run CMake to check the build system integrity. -# No rule that depends on this can have commands that come from listfiles -# because they might be regenerated. -cmake_check_build_system: - $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 -.PHONY : cmake_check_build_system - diff --git a/_codeql_build_dir/bin/CUSTOM-COMPILE-OPTIONS.md b/_codeql_build_dir/bin/CUSTOM-COMPILE-OPTIONS.md deleted file mode 100644 index 9b05f49f..00000000 --- a/_codeql_build_dir/bin/CUSTOM-COMPILE-OPTIONS.md +++ /dev/null @@ -1,15 +0,0 @@ -cpucounters.h : `#define PCM_HA_REQUESTS_READS_ONLY` -For the metric "LOCAL: number of local memory access in %“ (getLocalMemoryRequestRatio API) count only read accesses (local and all). - -cpucounters.h : `#define PCM_DEBUG_TOPOLOGY` -print detailed CPU topology information - -cpucounters.h : `#define PCM_UNCORE_PMON_BOX_CHECK_STATUS` -verify uncore PMU register state after programming - -types.h : `#define PCM_DEBUG` -print some debug information - -pci.h : `#define PCM_USE_PCI_MM_LINUX` -use /dev/mem (direct memory mapped I/O) for PCICFG register access on Linux. This might be required for accessing registers in extended configuration space (beyond 4K) in *pcm-pcicfg* utility. Recent Linux kernels also require to be booted with iomem=relaxed option to make this work. - diff --git a/_codeql_build_dir/bin/CXL_README.md b/_codeql_build_dir/bin/CXL_README.md deleted file mode 100644 index ad9265be..00000000 --- a/_codeql_build_dir/bin/CXL_README.md +++ /dev/null @@ -1,15 +0,0 @@ -PCM can collect CLX bandwidth using the methods below. - --------------------------------------------------------------------------------- -CXL.mem and CXL.cache traffic --------------------------------------------------------------------------------- - -Please use pcm-memory utility for monitoring CXL.mem and CLX.cache traffic. pcm-memory will detect available CXL ports and will show traffic per CXL port and protocol (mem and cache) and per direction (read and write). - --------------------------------------------------------------------------------- -CXL.io traffic --------------------------------------------------------------------------------- - -pcm-iio utility should be used to monitor CXL.io traffic. pcm-iio will show traffic per CXL device and direction (inbound/outbound, read/write) - - diff --git a/_codeql_build_dir/bin/DOCKER_README.md b/_codeql_build_dir/bin/DOCKER_README.md deleted file mode 100644 index ed38f7ed..00000000 --- a/_codeql_build_dir/bin/DOCKER_README.md +++ /dev/null @@ -1,14 +0,0 @@ --------------------------------------------------------------------------------- -How To Run Intel(r) Performance Counter Monitor Server Container from GitHub Container Repository or Docker Hub --------------------------------------------------------------------------------- - -As root user: -1. ``modprobe msr`` -2. ``docker run -d --name pcm --privileged -p 9738:9738 ghcr.io/intel/pcm`` (GitHub Container repository) or ``docker run -d --name pcm --privileged -p 9738:9738 opcm/pcm`` (Dockerhub repository) - - the container can also be run with limited capabilities without the privileged mode: ``docker run -d --name pcm --cap-add=SYS_ADMIN --cap-add=SYS_RAWIO --device=/dev/cpu --device=/dev/mem -v /sys/firmware/acpi/tables/MCFG:/pcm/sys/firmware/acpi/tables/MCFG:ro -v /proc/bus/pci/:/pcm/proc/bus/pci/ -v /proc/sys/kernel/nmi_watchdog:/pcm/proc/sys/kernel/nmi_watchdog -v /sys:/sys:rw -p 9738:9738 ghcr.io/intel/pcm`` (there is also a docker-compose file containing these options: https://raw.githubusercontent.com/intel/pcm/master/docker-compose.yml) - -This will start pcm-sensor-server container exposing CPU metrics from the whole system at port 9738 - -The URLs of the docker container repositories: -- https://github.com/intel/pcm/pkgs/container/pcm -- https://hub.docker.com/r/opcm/pcm diff --git a/_codeql_build_dir/bin/ENVVAR_README.md b/_codeql_build_dir/bin/ENVVAR_README.md deleted file mode 100644 index 3a93ced0..00000000 --- a/_codeql_build_dir/bin/ENVVAR_README.md +++ /dev/null @@ -1,17 +0,0 @@ -`PCM_NO_PERF=1` : don't use Linux perf events API to program *core* PMUs (default is to use it) - -`PCM_USE_UNCORE_PERF=1` : use Linux perf events API to program *uncore* PMUs (default is *not* to use it) - -`PCM_NO_RDT=1` : don't use RDT metrics for a better interoperation with pqos utility (https://github.com/intel/intel-cmt-cat) - -`PCM_USE_RESCTRL=1` : use Linux resctrl driver for RDT metrics - -`PCM_PRINT_TOPOLOGY=1` : print detailed CPU topology - -`PCM_KEEP_NMI_WATCHDOG=1` : don't disable NMI watchdog (reducing the core metrics set) - -`PCM_NO_MAIN_EXCEPTION_HANDLER=1` : don't catch exceptions in the main function of pcm tools (a debugging option) - -`PCM_ENFORCE_MBM=1` : force-enable Memory Bandwidth Monitoring (MBM) metrics (LocalMemoryBW = LMB) and (RemoteMemoryBW = RMB) on processors with RDT/MBM errata - -`PCM_DEBUG_LEVEL=x` : x is an integer defining debug output level. level = 0 (default): minimal or no debug info, > 0 increases verbosity diff --git a/_codeql_build_dir/bin/FAQ.md b/_codeql_build_dir/bin/FAQ.md deleted file mode 100644 index 88a0266d..00000000 --- a/_codeql_build_dir/bin/FAQ.md +++ /dev/null @@ -1,95 +0,0 @@ - -## Q1 - -pcm-iio Tool outputs "Server CPU is required for this tool! Program aborted". Is there a way I can monitor my PCIe link bandwidth using one of the PCM utilities on client CPU? - -Answer: The "IO" metric in *pcm* utility is the closest capability to monitor I/O PCIe traffic on client CPUs. - -## Q2 - -PCM reports "ERROR: QPI LL monitoring device (...) is missing". How to fix it? - -Answer: It is likely a BIOS issue. See details [here](https://software.intel.com/content/www/us/en/develop/articles/bios-preventing-access-to-qpi-performance-counters.html) - -## Q3 - -Does PCM work inside a virtual machine? - -Answer: PCM works inside virtual machines which support vPMU (with a limited set of metrics supported by vPMU). For example on AWS instances this is indicated by the presence of [arch_perfmon](https://instaguide.io/info.html?type=c5.18xlarge) flag: https://instaguide.io/ . Enabling vPMU in hypervisors is documented [in Hardware Event-Based Sampling section](https://software.intel.com/content/www/us/en/develop/documentation/vtune-help/top/set-up-analysis-target/on-virtual-machine.html). - -## Q4 - -Does PCM work inside a docker container? - -Answer: yes, it does. An example of how to run PCM inside a docker container is located [here](DOCKER_README.md). The recipe works also for other PCM utilities besides pcm-sensor-server. - -## Q5 - -pcm-power reports "Unsupported processor model". Can you add support for pcm-power for my CPU? - -Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. PCM-power can not work without them. - -## Q6 - -pcm-memory reports that the CPU is not supported. Can you add support for pcm-memory for my CPU? - -Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. PCM-memory can not work without them. - -## Q7 - -Can PCM be used for measuring energy, CPU cycles, etc for a particular process or does it measure for the system as a whole? - -Answer: PCM supports measurement for the whole system, per processor, per physical or per logical core. If you need monitoring per-process or user per-thread you can pin your process and/or thread to certain cores and read PCM data for these cores. But keep in mind that the OS can also schedule other processes or threads on this core and this may disturb your measurements. For a precise per-process or per-thread measurement the Intel VTune profiler or Linux perf profiler should be used. - -## Q8 - -PCM reports - -``` -opening /dev/mem failed: errno is 1 (Operation not permitted) -Can not read memory controller counter information from PCI configuration space. Access to memory bandwidth counters is not possible. -You must be root to access these SandyBridge/IvyBridge/Haswell counters in PCM. -Secure Boot detected. Using Linux perf for uncore PMU programming. -``` - -How to fix it? - -Answer: Linux disables access to /dev/mem because Secure Boot is enabled in the BIOS. Disable Secure Boot in the BIOS to enable memory controller statistics (e.g. memory read and write bandwidth). - -## Q9 - -PCM reports -``` -Linux Perf: Error on programming ... -``` -How to fix it? - -**Answer:** It is an issue with the Linux kernel perf driver. As a workaround upgrade your Linux kernel to the latest available/possible or run PCM with its own programming logic: - -``` -export PCM_NO_PERF=1 -pcm -r -``` - -## Q10 - -If you are getting the error `Starting MSR service failed with error 3 The system cannot find the path specified.` try to uninstall the driver by running `pcm --uninstallDriver` and optionally reboot the system. - -## Q11 - -Is PCM supported on AWS instances - -**Answer**: - -Not all AWS instances allow users to collect CPU telemetry by exposing PMU to the user. The following instances can be used: - -* Bare metal instances: allow collection of CPU metrics from both core (e.g. instructions per cycle, cache misses) and uncore (e.g. memory controller, UPI) -* Full-socket (single socket, two socket, etc) virtualized instances: e.g. m5d.12xlarge, m5.24xlarge, m5.12xlarge. Only core CPU metrics are exposed, and certain CPU performance events are forbidden (e.g. offcore response events, events collecting “any_thread” information). “arch_perfmon” flag in /proc/cpuinfo indicates if the core CPU metrics are exposed (example: https://instaguide.io/info.html?type=m5.12xlarge ). The mechanism of PMU virtualization is commonly known as vPMU. - -## Q12 - -pcm-pcie reports that the CPU is not supported: "Jaketown, Ivytown, Haswell, Broadwell-DE, Skylake, Icelake, Snowridge and Sapphirerapids Server CPU is required for this tool! Program aborted" -Can you add support for pcm-pcie for my CPU? - -Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. pcm-pcie can not work without them. - diff --git a/_codeql_build_dir/bin/FREEBSD_HOWTO.txt b/_codeql_build_dir/bin/FREEBSD_HOWTO.txt deleted file mode 100644 index 7711c85f..00000000 --- a/_codeql_build_dir/bin/FREEBSD_HOWTO.txt +++ /dev/null @@ -1,8 +0,0 @@ -Building: -$ cmake -B build -$ cmake --build build - -Runtime requirements: -* the cpuctl(4) driver needs to be loaded - -PCM is also available as a port maintained by The FreeBSD Project (sysutils/intel-pcm). diff --git a/_codeql_build_dir/bin/LATENCY-OPTIMIZED-MODE.md b/_codeql_build_dir/bin/LATENCY-OPTIMIZED-MODE.md deleted file mode 100644 index 6cf74314..00000000 --- a/_codeql_build_dir/bin/LATENCY-OPTIMIZED-MODE.md +++ /dev/null @@ -1,61 +0,0 @@ -# Latency Optimized Mode in Intel® Xeon® 6 Processors - -Intel® Xeon® 6 Processors (previously codenamed Granite Rapids and Sierra Forest/Birch Stream platform) introduce a new power management mechanism called Efficiency Latency Control (ELC), designed to optimize performance per watt. This feature allows hardware power management algorithms to balance the trade-off between latency and power consumption. For latency-sensitive workloads, further tuning can be performed to achieve the desired performance. - -The hardware monitors the average CPU utilization across all cores at regular intervals to determine an appropriate uncore frequency. While this approach generally results in optimal performance per watt, some workloads may achieve higher performance at the expense of increased power consumption. For instance, an application that intermittently performs memory reads on an otherwise idle system may experience delays if the hardware lowers the uncore frequency, causing a lag in ramping up to the required performance levels. To verify this, the uncore frequencies can be monitored using the pcm utility: - -![Uncore Frequency Statistics DEFAULT](https://github.com/user-attachments/assets/108c7350-3fc2-4056-aeaf-ecc7c25da6bc) - -The screenshot above presents real-time data on uncore frequency statistics, measured in GHz, from a dual-socket platform (represented by two rows). Each socket includes five dies (organized into five columns). The first three dies contain CORes (COR), Last Level Cache (LLC), and Memory controllers (M), collectively referred to as CORLLCM. The final two dies are IO dies. - -The ELC control has parameters that can be adjusted either through BIOS or software tools. The default parameter configuration is optimized for performance per watt, ensuring power efficiency. The alternative configuration, known as Latency Optimized Mode, prioritizes maximum performance. -Below are the PCM statistics from a system operating in Latency Optimized Mode: - -![Uncore Frequency Statistics Latency Optimized Mode](https://github.com/user-attachments/assets/70310bbc-725b-4450-af7a-1db2c04291dd) - -## BIOS Options for Latency Optimized Mode - -The BIOS option for selecting the Default or Latency Optimized Mode can typically be located in the following menus, depending on the BIOS version and OEM vendor: -- **Socket Configuration** -> **Advanced Power Management** -> **CPU – Advanced PM Tuning** -> **Latency Optimized Mode** (Disabled or Enabled) -- **System Utilities** -> **System Configuration** -> **BIOS/Platform Configuration (RBSU)** -> **Power and Performance Options** -> **Advanced Power Options** -> **Efficiency Latency Control** (Default or Latency Optimized mode) - -Should this BIOS option be unavailable or if there is a preference to change the mode during runtime, the PCM repository provides scripts for changing this mode. - -|Platform |Script Type| URL | -|------------------|-----------|---------------------------------------------------------------------| -|Linux/FreeBSD/UNIX|bash | https://github.com/intel/pcm/blob/master/scripts/bhs-power-mode.sh | -|Windows |powershell | https://github.com/intel/pcm/blob/master/scripts/bhs-power-mode.ps1 | - -The scripts require the pcm-tpmi utility. There are several methods to obtain this utility: -- **Download or install precompiled PCM binaries:** Please refer to the following link: [Downloading Pre-Compiled PCM Tools](https://github.com/intel/pcm?tab=readme-ov-file#downloading-pre-compiled-pcm-tools) -- **Compile the utility:** Follow the instructions in the "Building PCM Tools" section available at: [Building PCM Tools](https://github.com/intel/pcm?tab=readme-ov-file#building-pcm-tools) - * For Linux/FreeBSD: Copy the pcm-tpmi utility from PCM’s source 'build/bin' directory to `/usr/local/bin/` or execute `make install` in the 'build' directory. - -For Windows: Copy the pcm-tpmi utility to the current directory. - -Once the pcm-tpmi binary is correctly placed, you can set the Latency Optimized Mode. - -### Setting Latency Optimized Mode - -Linux/FreeBSD/UNIX: -``` -bash bhs-power-mode.sh --latency-optimized-mode -``` -Windows: -``` -.\bhs-power-mode.ps1 --latency-optimized-mode -``` - -### Restoring the Default Mode - -Linux/FreeBSD/UNIX: -``` -bash bhs-power-mode.sh --default -``` - -Windows: -``` -.\bhs-power-mode.ps1 --default -``` - - diff --git a/_codeql_build_dir/bin/LINUX_HOWTO.txt b/_codeql_build_dir/bin/LINUX_HOWTO.txt deleted file mode 100644 index 19062902..00000000 --- a/_codeql_build_dir/bin/LINUX_HOWTO.txt +++ /dev/null @@ -1,7 +0,0 @@ -Refer to the main README ("Building PCM Tools" or "Downloading Pre-Compiled PCM Tools") sections - -Running tests: - -* build PCM -* as root run "sh test/test.sh" - - Automated CI test workflow: https://github.com/intel/pcm/blob/03ad6b0228c9e8a8eb022708b53a61875b9447bc/.github/workflows/ci-test.yml#L40 diff --git a/_codeql_build_dir/bin/MAC_HOWTO.txt b/_codeql_build_dir/bin/MAC_HOWTO.txt deleted file mode 100644 index 4cdd2dfb..00000000 --- a/_codeql_build_dir/bin/MAC_HOWTO.txt +++ /dev/null @@ -1,64 +0,0 @@ -Building and Installing - -Note: xcode is required to build the driver and dynamic library. - -Requirements -____________ -Building and installing requires make, cmake, gcc, and xcode. -It has been tested on the following system configurations: - OS X 12.0.1, Xcode 13.1, Apple LLVM compiler 13.0.0 - -Build PCM and MacMSRDriver ------------------ - mkdir build && cd build - cmake .. && cmake --build . - -PCM utilities will be located in build/bin folder, libraries libpcm.dylib and libPcmMsr.dylib - in build/lib. - -Automatic Install ------------------ - cd build - sudo make install - -Install command loads the driver, installs the library into /usr/lib and installs the library headers into /usr/include. -Also PCM utilities are installing to /usr/local/sbin. - -Manual Install --------------- -Build steps are the same. -To install do the following: - 1) load the driver by running src/MacMSRDriver/kextload.sh - 2) copy build/lib/libPcmMsr.dylib to a location on your path (auto-install uses /usr/lib) - 3) copy src/MacMSRDriver/MSRKernel.h to a location on your path (auto-install uses /usr/include) - 4) copy src/MacMSRDriver/MSRAccessorPublic.h as MSRAccessor.h to a location on your path (auto-install uses /usr/include) - -kext Signatures ---------------- -As of OS X El Capitan, kexts must be signed. So after building the kext, kextload.sh may fail with: - - /System/Library/Extensions/PcmMsrDriver.kext failed to load - (libkern/kext) not loadable (reason unspecified); check the system/kernel logs for errors or try kextutil(8). - -In this event, you will need to either disable System Integrity Protection or sign the kext. -You can disable SIP by rebooting into Recovery (reboot, command-option-R), opening a shell, csrutil disable and reboot again. -Signing a kext is more involved. You can't self-sign and will first need to obtain a Developer ID from Apple: - - https://developer.apple.com/contact/kext/ - -With this ID, you can then sign your kext with codesign. - -PCM Execution ----------------------- -Now you can run ./pcm utility. -See description of other built utilities in LINUX_HOWTO.txt - -Logging/Debugging ----------------------- - -Sometimes you will get errors while running utilities that may come from the kernel, and you can use something like this DTrace script to correlate it with user-land behavior: - -$ sudo dtrace -n 'fbt:mach_kernel:_ZN*IOUser*:return /execname == "pcm"/ { @hgram[probefunc, arg1, ustack(20)] = count(); }' -c ./pcm - -Various commands that can help diagnose errors: - -$ kmutil log stream -$ kmutil inspect -b com.intel.driver.PcmMsr diff --git a/_codeql_build_dir/bin/PCM-EXPORTER.md b/_codeql_build_dir/bin/PCM-EXPORTER.md deleted file mode 100644 index 63efc0b6..00000000 --- a/_codeql_build_dir/bin/PCM-EXPORTER.md +++ /dev/null @@ -1,36 +0,0 @@ -# Intel® Performance Counter Monitor (Intel® PCM) Prometheus exporter - - -pcm-sensor-server is a collector exposing Intel processor metrics over http in JSON or Prometheus (exporter text based) format. Also [available as a docker container](DOCKER_README.md). - -Installation on target system to be analyzed: -1. [Build](https://github.com/intel/pcm#building-pcm-tools) or [download](https://github.com/intel/pcm#downloading-pre-compiled-pcm-tools) pcm tools -2. As root, start pcm-sensor-server: `sudo ./pcm-sensor-server` or as non-root https://github.com/intel/pcm#executing-pcm-tools-under-non-root-user-on-linux - -Alternatively one can start [pcm-sensor-server as a container from docker hub](DOCKER_README.md). - -Additional options: - -``` -$ ./pcm-sensor-server --help -Usage: ./pcm-sensor-server [OPTION] - -Valid Options: - -d : Run in the background - -p portnumber : Run on port (default port is 9738) - -r|--reset : Reset programming of the performance counters. - -D|--debug level : level = 0: no debug info, > 0 increase verbosity. - -R|--real-time : If possible the daemon will run with real time - priority, could be useful under heavy load to - stabilize the async counter fetching. - -h|--help : This information -``` - -The default output of pcm-sensor-server endpoint in a browser: - -![image](https://user-images.githubusercontent.com/25432609/226344012-8783e154-998e-48a7-a2ca-f2c42af9c843.png) - - -The PCM exporter can be used together with Grafana to obtain these Intel processor metrics (see [how-to](../scripts/grafana/README.md)): - -![pcm grafana output](https://raw.githubusercontent.com/wiki/intel/pcm/pcm-dashboard-full.png) diff --git a/_codeql_build_dir/bin/PCM-SENSOR-SERVER-README.md b/_codeql_build_dir/bin/PCM-SENSOR-SERVER-README.md deleted file mode 100644 index 16cbf717..00000000 --- a/_codeql_build_dir/bin/PCM-SENSOR-SERVER-README.md +++ /dev/null @@ -1,47 +0,0 @@ -# Global PCM Events - -| Event Name | Description | -|-----------------------------|-----------------------------------------------------------------------------| -| Measurement_Interval_in_us | How many us elapsed to complete the last measurement | -| Number_of_sockets | Number of CPU sockets in the system | - - -# Core Counters per socket - -OS_ID is the OS assigned ID of the logical CPU core and denotes the socket id, core id and thread id. - -The events below are followed by the same {socket="socket id",core="core id",thread="thread id"} as -the OS_ID of their section with source="socket/core/thread" appended that denotes what the quantity -of the event accounts for. - -For example Instructions_Retired_Any{socket="0",core="1",thread="1",source="core"} refers to -Instructions_Retired_Any for socket 0, core 1, thread 1, and accounts for the total instructions -retired of the specified core. - -| Event | Description | -|------------------------------------------------|--------------------------------------------------------------| -| Instructions_Retired_Any | Total number of Retired instructions | -| Clock_Unhalted_Thread | | -| Clock_Unhalted_Ref | Counts the number of reference cycles that the thread is | -| | not in a halt state. The thread enters the halt state when | -| | it is running the HLT instruction. This event is not | -| | affected by thread frequency changes but counts as if the | -| | thread is running at the maximum frequency all the time. | -| L3_Cache_Misses | Total number of L3 Cache misses | -| L3_Cache_Hits | Total number of L3 Cache hits | -| L2_Cache_Misses | Total number of L2 Cache misses | -| L2_Cache_Hits | Total number of L3 Cache hits | -| L3_Cache_Occupancy | Computes L3 Cache Occupancy | -| SMI_Count | SMI (System Management Interrupt) count | -| Invariant_TSC | Calculates the invariant TSC clocks (the invariant TSC | -| | means that the TSC continues at a fixed rate regardless of | -| | the C-state or frequency of the processor as long as the | -| | processor remains in the ACPI S0 state. | -| Thermal_Headroom | Celsius degrees before reaching TjMax temperature | -| CStateResidency | This is the percentage of time that the core (or the whole | -| | package) spends in a particular level of C-state | | - -References: - -https://software.intel.com/content/www/us/en/develop/articles/intel-performance-counter-monitor.html -https://software.intel.com/content/dam/develop/external/us/en/documents-tps/325384-sdm-vol-3abcd.pdf - Chapter 18 Performance Monitoring \ No newline at end of file diff --git a/_codeql_build_dir/bin/PCM_ACCEL_README.md b/_codeql_build_dir/bin/PCM_ACCEL_README.md deleted file mode 100644 index 0acde59c..00000000 --- a/_codeql_build_dir/bin/PCM_ACCEL_README.md +++ /dev/null @@ -1,121 +0,0 @@ -## Purpose: - -Intel® Xeon® Scalable Processors, starting from the 4th Generation (codenamed Sapphire Rapids), feature accelerators, which include the Intel® In-Memory Analytics Accelerator (Intel® IAA), Intel® Data Streaming Accelerator (Intel® DSA), and Intel® QuickAssist Technology (Intel® QAT), among others. These accelerators are essential components that can enhance the performance of Intel architecture platforms. - -Although these accelerators and their associated software stacks can significantly contribute to data center system performance, customers and users often find it challenging to access and understand performance data such as utilization and throughput. This difficulty arises from the complexity of low-level hardware event sets, which require a deep understanding of the accelerator's hardware and software architecture. - -The pcm-accel tool addresses this challenge by sampling performance data from the accelerator hardware and presenting it to end users in an easy-to-understand format. Its goal is to enable users to quickly and accurately gain a high-level overview of performance or identify issues related to the accelerator, regardless of their level of expertise in the underlying technology. - -## Command syntax: - -pcm-accel [target] [options] - -#### the target parameter - -Notes: only 1 target is allowed to monitor. - -| target | Default | Description | -| ------ | ------- | ----------------------------- | -| -iaa | yes | Monitor the IAA accelerator. | -| -dsa | no | Monitor the DSA accelerator. | -| -qat | no | Monitor the QAT accelerator. | - -#### the options parameter - -Notes: multiple options is allowed. - -| options | Default | Description | -| ---------------------- | -------------------- | -------------------------------------------------------------------------------------------------------------------------- | -| -numa | no | Print NUMA node mapping instead of CPU socket location. | -| -evt=[cfg.txt] | opCode-x-y-accel.txt | Specify the event config file name as cfg.txt.
- x/y is cpu family is model id, for example 6/143 for Sapphire Rapids. | -| -silent | no | Silence information output and print only measurements | -| -csv[=file.csv] | no | Output compact CSV format to screen or a file in case filename is provided | -| -csv-delimiter=[value] | no | Set custom csv delimiter | -| -human-readable | no | Use human readable format for output (for csv only) | -| -i=[value] | 0 | Allow to determine number of iterations, default is 0(infinite loop) if not specified. | -| [interval] | 3 | Time interval in seconds (floating point number is accepted) to sample performance counters, default is 3s if not specified| - -#### Examples: - -This example prints IAA counters every second 10 times and exits - -> pcm-accel -iaa 1.0 -i=10  - -This example saves IAA counters twice a second save IAA counter values to test.log in CSV format - -> pcm-accel -iaa 0.5 -csv=test.log            - -This example prints IAA counters every 3 second in human-readable CSV format - -> pcm-accel -iaa -csv -human-readable - -## Prerequisites: - -Linux* OS: - -FreeBSD* OS: - -Windows OS: - -- Install and load the required accelerator driver(iaa/dsa, qat driver, etc). - -Notes: - -- QAT monitoring and NUMA node display feature is supported only on Linux OS! - -## Tool UI introduction: - -Common indicator(Column field): - -- Accelerator = Accelerator device id. -- Socket = CPU socket id where accelerator device is located. -- NUMA Node = NUMA node that accelerator device belongs to. -- Inbound_BW = Data throughput input to the accelerator device, unit is Bps(Bytes per second). -- Outbound_BW = Data throughput output from the accelerator device, unit is Bps(Bytes per second). - -Specific indicators related to IAA/DSA:  - -- ShareWQ_ReqNb = The number of request submitted to share work queue of accelerator. -- DedicateWQ_ReqNb = The number of request submitted to dedicate work queue of accelerator. - -![image](https://user-images.githubusercontent.com/25432609/224027332-8846dff6-f71e-4daa-a189-730e68c7e1b2.png) -![image](https://user-images.githubusercontent.com/25432609/224027445-2b08e89c-4653-4f39-971b-a7dc76bd7349.png) - -Specific indicators related to QAT: - -- util_comp0 = The utilization of the compress engine 0, unit is %.(Sapphire Rapids platform has 1 compress and 3 decompress engine per QAT device) - -- util_decomp0 = same as above for decompress engine 0. - -- util_decomp1 = same as above for decompress engine 1. - -- util_decomp2 = same as above for decompress engine 2. - -- util_xlt0 = same as above for translation engine 0. - - - ![image](https://user-images.githubusercontent.com/25432609/224027570-e433aeef-c2ed-418d-aa42-18eef0f1b645.png) - - -## Event config file: - -pcm-accel tool allows the user to customized the monitored performance events with the config file as advance feature. - -Customize fields of cfg file: - -- ev_sel and ev_cat field for IAA/DSA monitor event. -- ev_sel field for QAT monitor event.  -- multiplier/divider is for event data display calculation. -- vname is the event name string(column) displayed in the UI. - -Please refer to the spec or code to learn more about the event mapping if you want to customize it. - -- IAA/DSA: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification - -- QAT: please refer to the [mapping table in source code](https://github.com/intel/pcm/blob/f20013f7563714cf592d7a59f169c1ddee3cf8ba/src/cpucounters.cpp#L915) - - -Here is the content of the event cfg file(opCode-6-143-accel.txt as example) - -![image](https://user-images.githubusercontent.com/25432609/224027717-1dcdae9e-6701-4b6f-90a0-8108c4ea4550.png) - diff --git a/_codeql_build_dir/bin/PCM_IIO_README.md b/_codeql_build_dir/bin/PCM_IIO_README.md deleted file mode 100644 index cc2e0ab6..00000000 --- a/_codeql_build_dir/bin/PCM_IIO_README.md +++ /dev/null @@ -1,35 +0,0 @@ -## Purpose: - -PCM-IIO tool monitors PCIe transactions with a breakdown per PCIe bus (IIO stack) and/or PCIe devices. - -## Tool UI introduction: - -Inbound (PCIe device DMA into system) metrics: - -* IB write (inbound write): the number of bytes per second that the PCIe device requested to write to main memory through DMA -* IB read (inbound read): the number of bytes per second that the PCIe device requested to read from main memory through DMA - -Outbound (CPU MMIO to the PCIe device) metrics: - -* OB read (outbound read): the number of bytes per second that the CPU requested to read from the PCIe device through MMIO (memory-mapped I/O) -* OB write (outbound write): the number of bytes per second that the CPU requested to write to the PCIe device through MMIO (memory-mapped I/O) - -IOMMU metrics: - -* IOTLB Lookup: IOTLB lookups per second -* IOTLB Miss: IOTLB misses per second -* Ctxt Cache Hit: Context cache hits per second -* 256T Cache Hit: Second Level Page Walk Cache Hits to a 256T page per second -* 512G Cache Hit: Second Level Page Walk Cache Hits to a 512G page per second -* 1G Cache Hit: Second Level Page Walk Cache Hits to a 1G page per second -* 2M Cache Hit: Second Level Page Walk Cache Hits to a 2M page per second -* IOMMU Mem Access: IOMMU memory accesses per second - -Sample output: - -![image](https://github.com/user-attachments/assets/e8cce396-b210-49d5-ac95-dc43f9ae69d3) - -## Event config file: - -pcm-iio tool allows the user to customize the performance events with a config file as an advanced feature. The event config files are in opCode-x-y.txt files where x/y is cpu family is model id, for example 6/143 for Sapphire Rapids. - diff --git a/_codeql_build_dir/bin/PCM_RAW_README.md b/_codeql_build_dir/bin/PCM_RAW_README.md deleted file mode 100644 index 585e0b35..00000000 --- a/_codeql_build_dir/bin/PCM_RAW_README.md +++ /dev/null @@ -1,251 +0,0 @@ --------------------------------------------------------------------------------- -PCM Raw Utility --------------------------------------------------------------------------------- - -Disclaimer: in contrast to other PCM utilities this one is for expert usage only. - -*pcm-raw* allows to collect arbitrary core and uncore PMU events by providing raw PMU event ID encoding. It can become handy if other low-level PMU tools (e.g. emon, Linux perf) can not be used for some reason. For example: -- emon kernel driver is not compatible with the currently used Linux kernel or operating system -- loading emon Linux kernel driver is forbidden due to system administration policies -- Linux kernel is too old to support modern processor PMU and can not be upgraded - -Currently supported PMUs: core, m3upi, upi(ll)/qpi(ll), imc, m2m, pcu, cha/cbo, iio, ubox - -Recommended usage (as privileged/root user): -1. Install VTune which also contains emon (emon/sep driver installation is not needed): [free download](https://software.intel.com/content/www/us/en/develop/tools/vtune-profiler.html) -2. Run emon with `--dry-run -m` options to obtain raw PMU event encodings for event of interest. For example: -``` -# emon -C BR_MISP_RETIRED.ALL_BRANCHES,UNC_CHA_CLOCKTICKS,UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0,UNC_UPI_TxL_FLITS.NON_DATA --dry-run -m -Event Set 0 - BR_MISP_RETIRED.ALL_BRANCHES (PerfEvtSel0 (0x186) = 0x00000000004300c5) - CC=ALL PC=0x0 UMASK=0x0 E=0x1 INT=0x0 INV=0x0 CMASK=0x0 AMT=0x0 -cha Uncore Event Set 0 - UNC_CHA_CLOCKTICKS (CHA Counter 0 (0xe01) = 0x0000000000400000) - -qpill Uncore Event Set 0 - UNC_UPI_TxL_FLITS.NON_DATA (QPILL Counter 0 (0x350) = 0x0000000000409702) - -iio Uncore Event Set 0 - UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 (IIO Counter 0 (0xa48) = 0x0000701000400183) -``` -3. Run *pcm-raw* by specifying the obtained raw event encodings to collect into csv file. Example: -``` -pcm-raw -e core/config=0x00000000004300c5,name=BR_MISP_RETIRED.ALL_BRANCHES -e cha/config=0x0000000000400000,name=UNC_CHA_CLOCKTICKS -e qpi/config=0x0000000000409702,name=UNC_UPI_TxL_FLITS.NON_DATA -e iio/config=0x0000701000400183,name=UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 -csv=out.csv -``` -4. View/process the csv file using your favorite method. For example just open it in Excel. - --------------------------------------------------------------------------------- -Collecting Register Values --------------------------------------------------------------------------------- - -pcm-raw supports collecting raw MSR and PCICFG (CSR) register values. The syntax is described below: - -Model Specific Registers (MSRs): - -``` -package_msr/config=,config1=[,name=] -``` - -static_or_freerun encoding: -* 0 : static (last value reported in csv) -* 1 : freerun (delta to last value reported in csv) - -Examples: -``` -package_msr/config=0x34,config1=0,name=SMI_COUNT -thread_msr/config=0x10,config1=1,name=TSC_DELTA -thread_msr/config=0x10,config1=0,name=TSC -``` - -If the name is not specified the first event will show up as package_msr:0x34:static, with the name it will show up as SMI_COUNT in csv. - -PCI Configuration Registers - PCICFG (CSR): - -``` -pcicfg/config=,config1=,config2=,width=[,name=] -``` - -* dev_id: Intel PCI device id where the register is located -* offset: offset of the register -* static_or_freerun: same syntax as for MSR registers -* width: register width in bits (16,32,64) - -Example: - -``` -pcicfg/config=0xe20,config1=0x180,config2=0x0,width=32,name=CHANERR_INT -``` -From: https://www.intel.la/content/dam/www/public/us/en/documents/datasheets/xeon-e7-v2-datasheet-vol-2.pdf - -MMIO Registers: - -``` -mmio/config=,config1=,config2=,config3=[,config4=],width=[,name=] -``` - -The MEMBAR is computed by logically ORing the result of membar_bits1 and membar_bits1 computation described below (PCICFG read + bit extraction and shift). The final MMIO register address = MEMBAR + offset. - -* width: register width in bits (16,32,64) -* dev_id: Intel PCI device id where the membar address registers are located -* membar_bits1: mmioBase register bits to compute membar (base address) - - bits 0-15 : PCICFG register offset to read membar1 bits - - bits 16-23: source position of membar bits in the PCICFG register - - bits 24-31: number of bits - - bits 32-39: destination bit position in the membar -* membar_bits2: mmioBase register bits to compute membar (base address), can be zero if only membar_bits1 is sufficient for locating the register. - - bits 0-15 : PCICFG register offset to read membar2 bits - - bits 16-23: source position of membar bits in the PCICFG register - - bits 24-31: number of bits - - bits 32-39: destination bit position in the membar -* offset: offset of the MMIO register relative to the membar -* static_or_freerun: same syntax as for MSR registers - -Example (Icelake server iMC PMON MMIO register read): - -``` -mmio/config=0x3451,config1=0x22808,config2=1,config3=0x171D0000D0,config4=0x0c0b0000d8,width=64 -``` - -TPMI Registers: - -TPMI ([Topology Aware Register and PM Capsule Interface](https://github.com/intel/tpmi_power_management)) can be read with pcm-raw as follows: - -``` -tpmi/config=,config1=,config2=[,name=] -``` - -* tpmi_id: TPMI id -* offset: offset of the register -* static_or_freerun: same syntax as for MSR registers - -Example: - -``` -tpmi/config=0x2,config1=0x18,name=BHS_UFS_CONTROL -``` - -From: https://github.com/intel/tpmi_power_management/blob/main/UFS_TPMI_public_disclosure_FINAL_rev4.pdf - --------------------------------------------------------------------------------- -Collecting Events By Names From Event Lists (https://github.com/intel/perfmon/) --------------------------------------------------------------------------------- - -pcm-raw can also automatically lookup the events from the json event lists (https://github.com/intel/perfmon/) and translate them to raw encodings itself. To make this work you need to checkout PCM with simdjson submodule: - -* use git clone --recursive flag when cloning pcm repository, or -* update submodule with command `git submodule update --init --recursive`, or -* download simdjson library in the PCM source directory and recompile PCM: - -1. change to PCM 'src/' directory -2. git clone https://github.com/simdjson/simdjson.git -3. re-compile pcm - -Example of usage (on Intel Xeon Scalable processor): - -``` -pcm-raw -tr -e INST_RETIRED.ANY -e CPU_CLK_UNHALTED.THREAD -e CPU_CLK_UNHALTED.REF_TSC -e LD_BLOCKS.STORE_FORWARD -e UNC_CHA_CLOCKTICKS -e UNC_M_CAS_COUNT.RD -``` - -or with event groups specified in event_file.txt (with event multiplexing): - -``` -pcm-raw -tr -el event_file.txt -``` - -where event_file.txt contains event groups separated by a semicolon: - -``` -# group 1 -INST_RETIRED.ANY -CPU_CLK_UNHALTED.REF_TSC -CPU_CLK_UNHALTED.THREAD -DTLB_LOAD_MISSES.STLB_HIT -L1D_PEND_MISS.PENDING_CYCLES_ANY -MEM_INST_RETIRED.LOCK_LOADS -UOPS_EXECUTED.X87 -UNC_CHA_DIR_LOOKUP.SNP -UNC_CHA_DIR_LOOKUP.NO_SNP -UNC_M_CAS_COUNT.RD -UNC_M_CAS_COUNT.WR -UNC_UPI_CLOCKTICKS -UNC_UPI_TxL_FLITS.ALL_DATA -UNC_UPI_TxL_FLITS.NON_DATA -UNC_UPI_L1_POWER_CYCLES -; -# group 2 -INST_RETIRED.ANY -CPU_CLK_UNHALTED.REF_TSC -CPU_CLK_UNHALTED.THREAD -OFFCORE_REQUESTS_BUFFER.SQ_FULL -MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT -MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM -MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS -UNC_CHA_DIR_UPDATE.HA -UNC_CHA_DIR_UPDATE.TOR -UNC_M2M_DIRECTORY_UPDATE.ANY -UNC_M_CAS_COUNT.RD -UNC_M_CAS_COUNT.WR -UNC_M_PRE_COUNT.PAGE_MISS -UNC_UPI_TxL0P_POWER_CYCLES -UNC_UPI_RxL0P_POWER_CYCLES -UNC_UPI_RxL_FLITS.ALL_DATA -UNC_UPI_RxL_FLITS.NON_DATA -; -``` - -Sample csv output (date,time,event_name,milliseconds_between_samples,TSC_cycles_between_samples,unit0_event_count,unit1_event_count,unit2_event_count,...): - -``` -2021-09-27,00:07:40.507,UNC_CHA_DIR_LOOKUP.SNP,1000,2102078418,76,70,56,91,88,75,76,158,74,60,77,81,75,74,71,95,99,95,125,87,68,136,54,91,65,84,69,46,75,100,92,68,67,70,68,80,72,88,80,76,130,71,102,98,79,73,71,109 -2021-09-27,00:07:40.507,UNC_CHA_DIR_LOOKUP.NO_SNP,1000,2102078418,1218,1280,1187,1310,1268,1287,1282,1331,1265,1267,1300,1270,1258,1307,1289,1300,1410,1378,1312,1316,1367,1337,1332,1317,1584,1519,1569,1557,1483,1537,1545,1520,1562,1527,1575,1540,1530,1581,1476,1525,1610,1680,1581,1657,1565,1613,1596,1600 -2021-09-27,00:07:40.507,INST_RETIRED.ANY,1000,2102078418,705400,44587,45923,238392,53910,69547,46644,46172,44740,44732,45692,44864,46105,45352,45057,217052,46511,46671,46893,46459,53739,47021,114133,46339,61649,59027,142096,48048,98178,48288,162122,474329,48046,49795,78239,425635,105512,69933,49827,48913,71549,48451,294858,312316,149586,540477,49115,55144,46788,61681,82964,81127,116227,85776,453369,145979,81007,82269,83580,73595,73355,73751,72599,47169,47767,48191,48131,48359,48621,67664,48227,532184,49686,48704,324264,48539,48795,48609,60275,518368,116077,163734,526815,50650,140337,666605,47935,1368049,47243,337542,47153,46882,46925,62373,70186,466927 -2021-09-27,00:07:40.507,CPU_CLK_UNHALTED.REF_TSC,1000,2102078418,3618636,384720,589092,2143512,766752,724164,803124,627312,541548,538188,534324,509964,535164,527436,529284,1366176,488124,491820,533148,543900,608580,577920,1145172,602196,919632,824544,1429344,692916,1092756,700644,1298640,2487156,736344,841344,1324008,1855476,1260084,1104768,658308,5805324,851424,766080,1909740,2170392,1313592,3986892,683844,986832,659064,642432,682668,772128,1076628,710220,2514876,1085112,715344,700812,676452,594468,577668,590856,574056,597996,525336,551460,548520,561624,569352,741468,623196,3124212,592032,596400,2265312,556584,593124,546756,766752,2547216,1047396,1280160,2704884,525336,1200444,3255000,497700,13643700,481572,1601040,515592,523740,503664,854280,603120,2305128 -2021-09-27,00:07:40.507,CPU_CLK_UNHALTED.THREAD,1000,2102078418,1723000,183219,280560,1020631,365140,344897,382467,298699,257868,256243,254471,242757,254794,251172,252091,650377,232442,234209,253807,259024,289817,275179,545244,286717,437888,392646,680513,329759,520244,333662,618356,1184347,350594,400648,630580,1517122,599939,525847,313441,2765951,405441,364827,909395,1033366,625655,1898427,325614,881026,312798,305884,325245,367890,512845,338440,1197524,516836,341497,334581,322975,283138,275031,281300,273347,284616,250171,262581,261182,267455,271097,353013,296757,1487751,282516,283651,1076725,265489,282845,260889,365411,1212743,498705,611118,1287439,360493,571158,1549944,236616,6499483,229820,762766,245338,248648,239640,406676,287582,1714659 -2021-09-27,00:07:40.507,DTLB_LOAD_MISSES.STLB_HIT,1000,2102078418,10093,1178,1186,2593,1184,1356,1182,1201,1187,1200,1191,1179,1189,1179,1177,1444,1218,1205,1158,1183,1216,1190,1789,1184,1388,1347,2207,1384,1566,1352,1541,3221,1374,1398,1580,11223,1690,1427,1398,1356,1531,1388,3429,3567,2136,2639,1354,1393,1181,1188,1457,1456,1801,1437,4698,1697,1426,1434,1418,1452,1396,1394,1434,1164,1349,1349,1356,1318,1354,1528,1349,18546,1168,1160,8935,1166,1172,1167,1194,4432,1801,2341,3152,1190,1777,4328,1178,4396,1170,1939,1199,1150,1158,1197,1187,12441 -2021-09-27,00:07:40.507,L1D_PEND_MISS.PENDING_CYCLES_ANY,1000,2102078418,682630,81530,114229,363299,169260,134931,441644,183870,89947,95379,98135,81156,75366,77990,78734,178321,52738,53883,57241,56306,65514,94824,152070,227164,87723,80980,300491,70675,148506,70130,173723,628031,142178,161405,503099,383743,255465,317627,67134,1509172,105102,242908,300344,336683,157280,555052,84017,615357,526290,88531,117674,387708,192129,157226,451213,201430,103646,106302,112452,86251,83203,82880,80239,189044,72389,73820,75135,70746,84963,106517,168907,249006,117006,109389,320326,98291,168531,100734,206075,647276,167155,154684,495947,359092,257614,322235,78189,1473756,148139,278653,308380,343576,166510,556816,90475,306546 -2021-09-27,00:07:40.507,MEM_INST_RETIRED.LOCK_LOADS,1000,2102078418,3462,231,235,1159,259,277,239,237,236,238,236,239,238,237,237,1114,237,237,238,237,265,237,555,237,277,278,542,237,431,240,389,906,239,238,385,3973,435,280,238,238,401,238,847,1238,604,1948,238,238,235,275,266,267,428,277,1287,399,271,277,272,239,240,239,239,237,237,237,237,237,238,347,237,4266,238,238,1174,238,238,238,270,1361,526,697,1101,238,615,2172,238,4276,236,642,236,237,236,275,299,2842 -2021-09-27,00:07:40.507,UOPS_EXECUTED.X87,1000,2102078418,1152,12,13,496,46,17,27,12,11,13,10,14,11,27,12,1591,11,10,11,13,23,11,257,12,64,52,216,31,231,31,1668,5944,31,30,85,710,101,54,34,41,100,33,1852,1561,423,2348,28,46,14,23,155,57,82,172,2776,281,19,52,107,18,36,18,19,14,11,10,10,10,26,57,10,108,31,33,151,31,32,30,63,3700,361,509,4610,31,396,1814,31,5607,33,4175,31,30,32,47,78,471 -2021-09-27,00:07:40.507,UNC_M_CAS_COUNT.RD,1000,2102078418,37565,33584,0,0,0,0,40306,0,37373,0,0,0 -2021-09-27,00:07:40.507,UNC_M_CAS_COUNT.WR,1000,2102078418,58994,53007,0,0,0,0,25088,0,21901,0,0,0 -2021-09-27,00:07:40.507,UNC_UPI_CLOCKTICKS,1000,2102078418,1300347171,1300351441,1200328715,1300297715,1300303139,1200283803 -2021-09-27,00:07:40.507,UNC_UPI_TxL_FLITS.ALL_DATA,1000,2102078418,132768,150840,0,285147,269190,0 -2021-09-27,00:07:40.507,UNC_UPI_TxL_FLITS.NON_DATA,1000,2102078418,298203,319302,0,293389,264875,0 -2021-09-27,00:07:40.507,UNC_UPI_L1_POWER_CYCLES,1000,2102078418,0,0,1200328715,0,0,1200283803 -``` -The unit can be logical core, memory channel, CHA, etc, depending on the event type. - - -Show events available for the processor on the system: -``` -pcm-raw -? -``` - --------------------------------------------------------------------------------- -Low-level access to Intel PMT telemetry data --------------------------------------------------------------------------------- - -pcm-raw can read raw telemetry data from Intel PMT (https://github.com/intel/Intel-PMT/). - -Syntax for a PMT raw telemetry counter: - -``` -pmt/config=,config1=,config2=,config3=[,name=] - -``` - -The fields are the values for the counter from the Intel PMT aggregator XML: - -* uniqueid : Intel PMT Telemetry unique identifier -* sampleID : sample ID of the counter -* sampleType counter encoding: - - 0 : Snapshot (last value reported in csv) - - non-zero : Counter (delta to last value reported in csv) -* lsb : lsb field -* msb : msb field - -Example for https://github.com/intel/Intel-PMT/blob/868049006ad2770a75e5fc7526fd0c4b22438e27/xml/SPR/OOBMSM/CORE/spr_aggregator.xml#L15428: -``` -pmt/config=0x87b6fef1,config1=770,config2=0,config3=32,config4=63,name="Temperature_histogram_range_5_(50.5-57.5C)_counter_for_core_0" -``` - -Current limitations: this feature (PMT access) is currently only available on Linux (with Intel PMT Linux driver). diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-4F-1.json deleted file mode 100644 index 3f1fcc2b..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-4F-1.json +++ /dev/null @@ -1,122 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "AnyThread": {"Config": 0, "Position": 21, "Width": 1}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 2, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 6, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 10, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "TIDEnable": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "Filter0": {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0}, - "TID": {"Config": 1, "Position": 0, "Width": 6, "DefaultValue": 0}, - "State": {"Config": 1, "Position": 17, "Width": 7, "DefaultValue": 0}, - "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59}, - "OPC": {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0}, - "NC": {"Config": 2, "Position": 30, "Width": 1, "DefaultValue": 0}, - "ISOC": {"Config": 2, "Position": 31, "Width": 1, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "ha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "ubox" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-55-4.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-55-4.json deleted file mode 100644 index 9b08c471..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-55-4.json +++ /dev/null @@ -1,136 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "AnyThread": {"Config": 0, "Position": 21, "Width": 1}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 2, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 6, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 10, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "TIDEnable": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "Filter0": {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0}, - "TID": {"Config": 1, "Position": 0, "Width": 9, "DefaultValue": 0}, - "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "ubox" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 8}, - "FCMask": {"Config": 0, "Position": 44, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-6A-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-6A-0.json deleted file mode 100644 index ee0d516d..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-6A-0.json +++ /dev/null @@ -1,144 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed3" : { - "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "TIDEnable": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 9, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "ubox" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-86-5.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-86-5.json deleted file mode 100644 index f564e4fa..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-86-5.json +++ /dev/null @@ -1,103 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8E-C.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8E-C.json deleted file mode 100644 index 9955c1dc..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8E-C.json +++ /dev/null @@ -1,57 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "AnyThread": {"Config": 0, "Position": 21, "Width": 1}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 2, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 6, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "AnyThread": {"Config": 0, "Position": 10, "Width": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8F-6.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8F-6.json deleted file mode 100644 index 0cc35641..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-8F-6.json +++ /dev/null @@ -1,152 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed3" : { - "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "mdf" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "ubox" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AD-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AD-0.json deleted file mode 100644 index d68375b7..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AD-0.json +++ /dev/null @@ -1,158 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed3" : { - "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "mdf" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex8" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex16" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AE-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AE-0.json deleted file mode 100644 index d68375b7..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AE-0.json +++ /dev/null @@ -1,158 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed3" : { - "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "mdf" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex8" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex16" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AF-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AF-0.json deleted file mode 100644 index e3b4a8ed..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-AF-0.json +++ /dev/null @@ -1,145 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "mdf" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex8" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex16" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-B6-0.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-B6-0.json deleted file mode 100644 index e3b4a8ed..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-B6-0.json +++ /dev/null @@ -1,145 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "mdf" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex8" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "pciex16" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-CF-1.json b/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-CF-1.json deleted file mode 100644 index 0cc35641..00000000 --- a/_codeql_build_dir/bin/PMURegisterDeclarations/GenuineIntel-6-CF-1.json +++ /dev/null @@ -1,152 +0,0 @@ -{ - "core" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "User": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 1}, - "OS": {"Config": 0, "Position": 17, "Width": 1, "DefaultValue": 1}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1}, - "PinControl": {"Config": 0, "Position": 19, "Width": 1, "DefaultValue": 0}, - "APICInt": {"Config": 0, "Position": 20, "Width": 1, "DefaultValue": 0}, - "Enable": {"Config": 0, "Position": 22, "Width": 1, "DefaultValue": 1}, - "Invert": {"Config": 0, "Position": 23, "Width": 1}, - "CounterMask": {"Config": 0, "Position": 24, "Width": 8}, - "InTX": {"Config": 0, "Position": 32, "Width": 1, "DefaultValue": 0}, - "InTXCheckpointed": {"Config": 0, "Position": 33, "Width": 1, "DefaultValue": 0}, - "MSRIndex": { - "0x1a6" : {"Config": 1, "Position": 0, "Width": 64}, - "0x1a7" : {"Config": 2, "Position": 0, "Width": 64}, - "0x3f6" : {"Config": 3, "Position": 0, "Width": 64}, - "0x3f7" : {"Config": 4, "Position": 0, "Width": 64} - } - }, - "fixed0" : { - "OS": {"Config": 0, "Position": 0, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 1, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 3, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed1" : { - "OS": {"Config": 0, "Position": 4, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 5, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 7, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed2" : { - "OS": {"Config": 0, "Position": 8, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 9, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 11, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"} - }, - "fixed3" : { - "OS": {"Config": 0, "Position": 12, "Width": 1, "DefaultValue": 1}, - "User": {"Config": 0, "Position": 13, "Width": 1, "DefaultValue": 1}, - "EnablePMI": {"Config": 0, "Position": 15, "Width": 1, "DefaultValue": 0}, - "EventCode": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "UMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "EdgeDetect": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "Invert": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "CounterMask": {"Config": 0, "Position": -1, "__comment": "position=-1 means field ignored"}, - "PerfMetrics": {"Config": 2, "Position": 0, "Width": 1, "DefaultValue": 0, "__comment": "fake field to tell the collector to also print the L1 top-down metrics, not just raw slots count"} - } - }, - "cha" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "TIDEnable": {"Config": 0, "Position": 16, "Width": 1, "DefaultValue": 0}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 26}, - "TID": {"Config": 1, "Position": 0, "Width": 10, "DefaultValue": 0} - } - }, - "imc" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "xpi" : { - "__comment" : "this is for UPI LL and QPI LL uncore PMUs", - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 24} - } - }, - "m2m" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, - "UMaskExt": {"Config": 0, "Position": 32, "Width": 8} - } - }, - "m3upi" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "mdf" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "irp" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "ubox" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} - } - }, - "pcu" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} - } - }, - "iio" : { - "programmable" : { - "EventCode": {"Config": 0, "Position": 0, "Width": 8}, - "UMask": {"Config": 0, "Position": 8, "Width": 8}, - "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, - "Threshold": {"Config": 0, "Position": 24, "Width": 12, "DefaultValue": 0}, - "PortMask": {"Config": 0, "Position": 36, "Width": 12}, - "FCMask": {"Config": 0, "Position": 48, "Width": 3} - } - } -} diff --git a/_codeql_build_dir/bin/STARS.md b/_codeql_build_dir/bin/STARS.md deleted file mode 100644 index 3755531f..00000000 --- a/_codeql_build_dir/bin/STARS.md +++ /dev/null @@ -1,3 +0,0 @@ -## Git Hub Star History for PCM Project - -[![Star History Chart](https://api.star-history.com/svg?repos=intel/pcm&type=Date)](https://star-history.com/#intel/pcm&Date) diff --git a/_codeql_build_dir/bin/WINDOWS_HOWTO.md b/_codeql_build_dir/bin/WINDOWS_HOWTO.md deleted file mode 100644 index 97a880d5..00000000 --- a/_codeql_build_dir/bin/WINDOWS_HOWTO.md +++ /dev/null @@ -1,103 +0,0 @@ -**COMPILATION AND INSTALLATION OF UTILITIES** - -_For support of systems with more than _**_64_**_ logical cores you need to compile all binaries below in “_**_x64_**_” platform mode (not the default “_**_Win32_**_” mode)._ - -## Command-line utility - -1. Follow [Compile the Windows MSR driver](#compile-the-windows-msr-driver) to compile the Windows MSR driver (msr.sys). For Windows 7 and later versions you have to [sign the msr.sys driver additionally](#sign-the-windows-msr-driver). To enable loading test-signed drivers on the system: in administrator cmd console run `bcdedit /set testsigning on` and reboot. - -2. Build the *pcm.exe* utility: - ``` - cmake -B build - cmake --build build --config Release --parallel - ``` - alternatively you can perform `cmake -B build`, open *PCM.sln* form *build* folder in and build required project in Visual Studio. - .exe and .dll files will be located in *build\bin\Release* folder -3. As Administrator create PCM directory in Windows "Program Files" directory (e.g. `C:\Program Files (x86)\PCM\`) -4. As Administrator copy the msr.sys driver and pcm.exe into the PCM directory -5. Run pcm.exe utility from the PCM directory as Administrator - -For Windows 7+ and Windows Server 2008+ R2 the PCM utilities need to be run as Administrator: - -Alternatively you can achieve the same using the “Properties” Windows menu of the executable (“Privilege level” setting in the “Compatibility” tab): Right mouse click -> Properties -> Compatibility -> Privilege level -> Set “Run this program as an administrator”. - -![Screenshot](run-as-administrator.png) - -If you are getting the error `Starting MSR service failed with error 3 The system cannot find the path specified.` try to uninstall the driver by running `pcm --uninstallDriver` and optionally reboot the system. - -## Graphical Perfmon front end - -1. Follow [Compile the windows MSR driver](#compile-the-windows-msr-driver) to compile the windows MSR driver (msr.sys). For Windows 7 and later versions you have to sign the msr.sys driver additionally ([http://msdn.microsoft.com/en-us/library/ms537361(VS.85).aspx](http://msdn.microsoft.com/en-us/library/ms537361(VS.85).aspx)). - -2. Copy msr.sys into the c:\windows\system32 directory - -3. Build pcm-lib.dll using Microsoft Visual Studio or cmake - -4. Build 'PCM-Service.exe' using Microsoft Visual Studio or cmake - -5. Copy PCM-Service.exe, PCM-Service.exe.config, and pcm-lib.dll files into the PCM sub-directory in Windows "Program Files" directory (see above) - -The config file enables support for legacy security policy. Without this configuration switch, you will get an exception like this: - -Unhandled Exception: System.NotSupportedException: This method implicitly uses CAS policy, which has been obsoleted by the .NET Framework. - -6. With administrator rights execute '"PCM-Service.exe" -Install' from this directory - -7. With administrator rights execute 'net start pcmservice' - -8. Start perfmon and find new PCM\* counters - -If you do not want or cannot compile the msr.sys driver you might use a third-party open source WinRing0 driver instead (experimental only, for testing environments only). -Instructions: - -1. Download the free RealTemp utility package from [http://www.techpowerup.com/realtemp/](http://www.techpowerup.com/realtemp/) or any other free utility that uses the open-source WinRing0 driver (like OpenHardwareMonitor [http://code.google.com/p/open-hardware-monitor/downloads/list](http://code.google.com/p/open-hardware-monitor/downloads/list)). -2. Copy WinRing0.dll, WinRing0.sys, WinRing0x64.dll, WinRing0x64.sys files from there into the PCM.exe binary location, into the PCM-Service.exe location and into c:\windows\system32 -3. Run the PCM.exe tool and/or go to step 6 (perfmon utility). - -## Compile the Windows MSR driver - -1. Download Visual Studio ([Visual Studio download](https://visualstudio.microsoft.com/downloads/)). -When you install Visual Studio, also install related packages: - - under `Workloads`, select `Desktop development with C++` -(select `C++ CMake tools for Windows` in this workload) and `.NET desktop development`. - - under `Individual components`, search `Libs for Spectre` and select `MSVC v143 - VS -2022 C++ x64/x86 Spectre-mitigated libs(Latest)`. - -2. Download and install SDK ([windows-sdk](https://developer.microsoft.com/en-us/windows/downloads/windows-sdk/)) - -3. Download and install WDK ([windows-wdk](https://learn.microsoft.com/en-us/windows-hardware/drivers/download-the-wdk)). Please select `Install Windows Driver Kit Visual Studio extension` when you install WDK. - -4. Open **a terminal in Visual Studio**, then go to `src\WinMSRDriver`, and run the following command to compile the driver. Then you will see `MSR.sys` in `src\WinMSRDriver\x64\Release`. - ``` - MSBuild.exe MSR.vcxproj -property:Configuration=Release -property:Platform=x64 - ``` - -## Sign the Windows MSR driver - -Run the following in PowerShell, in the directory where `MSR.sys` is located: - -``` -$cert = New-SelfSignedCertificate -Type CodeSigning -Subject "CN=TestCert" -CertStoreLocation "Cert:\CurrentUser\My" -KeyExportPolicy Exportable -$pwd = Read-Host -Prompt "Enter the password for the PFX file" -AsSecureString -Export-PfxCertificate -Cert $cert -FilePath TestCert.pfx -Password $pwd -signtool sign /fd SHA256 /f TestCert.pfx /p ([Runtime.InteropServices.Marshal]::PtrToStringAuto([Runtime.InteropServices.Marshal]::SecureStringToBSTR($pwd))) /t http://timestamp.digicert.com MSR.sys -``` - -Afterwards, double-click `TestCert.pfx`. Install to "Current User" and when able to pick "Place all ...", browse for "Trusted Root Certification Authorities". - -## Known limitations - -Running PCM.exe under Cygwin shell is possible, but due to incompatibilities of signals/events handling between Windows and Cygwin, the PCM may not cleanup PMU configuration after Ctrl+C or Ctrl+Break pressed. The subsequent run of PCM will require to do PMU configuration reset, so adding -r command line option to PCM will be required. - -PCM-Service FAQ: -Q: Help my service won't start, what can I do to diagnose the problem? -A: Please check in the Windows Application "Event Viewer" under "Windows Logs" and then under "Application". PCM-Service writes its messages here, just look for errors. If you can't figure it out how to fix it, create a bug report and make sure to paste the text from the Event Viewer in the bug report so we can diagnose the issue. - -Q: I see a message in the Events Viewer that PCM-Service does not start because the "custom counter file view is out of memory", how do I fix this? -A: Despite that PCM-Service is reserving more memory than the standard 512kB this error can still occur if there is another application that uses performance counters is initialized before PCM. There are two options: -1. identify the application or service that starts before PCM-Service and stop or disable it and consequently reboot and try again -2. [find your machine.config file](https://stackoverflow.com/questions/2325473/where-is-machine-config) and add -` - -` -to that file diff --git a/_codeql_build_dir/bin/generate_summary_readme.md b/_codeql_build_dir/bin/generate_summary_readme.md deleted file mode 100644 index f202a926..00000000 --- a/_codeql_build_dir/bin/generate_summary_readme.md +++ /dev/null @@ -1,25 +0,0 @@ -Step 1 - -```pip3 install pipreqs``` - -Step 2 - -```cd /path/to/pcm/scripts``` - -Step 3 - -```python3 -m pipreqs.pipreqs --encoding utf-8 .``` - -Step 4 - -```pip3 install -r requirements.txt``` - -Step 5 - -```python3 generate_summary.py --help``` - -Step 6 - -```python3 generate_summary.py -{argument1} -{argument2} ....-{argumentN}``` - - diff --git a/_codeql_build_dir/bin/license.txt b/_codeql_build_dir/bin/license.txt deleted file mode 100644 index 976fed2c..00000000 --- a/_codeql_build_dir/bin/license.txt +++ /dev/null @@ -1,28 +0,0 @@ -This notice belongs to the code originating from "Intel Performance Counter Monitor". - -Copyright (c) 2009-2016, Intel Corporation -All rights reserved. -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -* Neither the name of Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - diff --git a/_codeql_build_dir/bin/opCode-6-106.txt b/_codeql_build_dir/bin/opCode-6-106.txt deleted file mode 100644 index 2bd1077e..00000000 --- a/_codeql_build_dir/bin/opCode-6-106.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-108.txt b/_codeql_build_dir/bin/opCode-6-108.txt deleted file mode 100644 index 2bd1077e..00000000 --- a/_codeql_build_dir/bin/opCode-6-108.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-134.txt b/_codeql_build_dir/bin/opCode-6-134.txt deleted file mode 100644 index 4c8e744f..00000000 --- a/_codeql_build_dir/bin/opCode-6-134.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 (4th x4) -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 (4th x4) -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=4K Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x40,en=1,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total \ No newline at end of file diff --git a/_codeql_build_dir/bin/opCode-6-143-accel.txt b/_codeql_build_dir/bin/opCode-6-143-accel.txt deleted file mode 100644 index 8c6429a7..00000000 --- a/_codeql_build_dir/bin/opCode-6-143-accel.txt +++ /dev/null @@ -1,20 +0,0 @@ -# IAA events -ctr=0,ev_sel=0x1,ev_cat=0x1,en=1,multiplier=32,divider=1,hname=IAA,vname=Inbound_BW(Bps) -ctr=1,ev_sel=0x2,ev_cat=0x1,en=1,multiplier=512,divider=1,hname=IAA,vname=Outbound_BW(Bps) -ctr=2,ev_sel=0x5,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=IAA,vname=ShareWQ_ReqNb -ctr=3,ev_sel=0x10,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=IAA,vname=DedicateWQ_ReqNb - -# DSA events -ctr=0,ev_sel=0x1,ev_cat=0x1,en=1,multiplier=32,divider=1,hname=DSA,vname=Inbound_BW(Bps) -ctr=1,ev_sel=0x2,ev_cat=0x1,en=1,multiplier=32,divider=1,hname=DSA,vname=Outbound_BW(Bps) -ctr=2,ev_sel=0x5,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=DSA,vname=ShareWQ_ReqNb -ctr=3,ev_sel=0x10,ev_cat=0x0,en=1,multiplier=1,divider=1,hname=DSA,vname=DedicateWQ_ReqNb - -# QAT events -ctr=0,ev_sel=0x6,ev_cat=0x1,en=1,multiplier=1048576,divider=1,hname=QAT,vname=Inbound_BW(Bps) -ctr=1,ev_sel=0x7,ev_cat=0x1,en=1,multiplier=1048576,divider=1,hname=QAT,vname=Outbound_BW(Bps) -ctr=2,ev_sel=0xB,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_comp0(%) -ctr=3,ev_sel=0xC,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_decomp0(%) -ctr=4,ev_sel=0xD,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_decomp1(%) -ctr=5,ev_sel=0xE,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_decomp2(%) -ctr=6,ev_sel=0xF,ev_cat=0x1,en=1,multiplier=1,divider=1,hname=QAT,vname=util_xlt0(%) diff --git a/_codeql_build_dir/bin/opCode-6-143.txt b/_codeql_build_dir/bin/opCode-6-143.txt deleted file mode 100644 index 7a4dfc3d..00000000 --- a/_codeql_build_dir/bin/opCode-6-143.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-173.txt b/_codeql_build_dir/bin/opCode-6-173.txt deleted file mode 100644 index 821de1c2..00000000 --- a/_codeql_build_dir/bin/opCode-6-173.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-174.txt b/_codeql_build_dir/bin/opCode-6-174.txt deleted file mode 100644 index 821de1c2..00000000 --- a/_codeql_build_dir/bin/opCode-6-174.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-175.txt b/_codeql_build_dir/bin/opCode-6-175.txt deleted file mode 100644 index 821de1c2..00000000 --- a/_codeql_build_dir/bin/opCode-6-175.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-182.txt b/_codeql_build_dir/bin/opCode-6-182.txt deleted file mode 100644 index 821de1c2..00000000 --- a/_codeql_build_dir/bin/opCode-6-182.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-207.txt b/_codeql_build_dir/bin/opCode-6-207.txt deleted file mode 100644 index 7a4dfc3d..00000000 --- a/_codeql_build_dir/bin/opCode-6-207.txt +++ /dev/null @@ -1,45 +0,0 @@ -#Clockticks -#ctr=0,unit=iio,ev_sel=0x1,umask=0x0,en=1,ch_mask=0,fc_mask=0x0,multiplier=1,hname=Clockticks,vname=Total -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB write,vname=Part7 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part0 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part1 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part2 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part3 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=16,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part4 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=32,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part5 -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=64,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part6 -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,ch_mask=128,fc_mask=0x7,multiplier=4,hname=IB read,vname=Part7 -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part0 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part1 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part2 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part3 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part4 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part5 -ctr=2,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part6 -ctr=3,unit=iio,ev_sel=0x83,umask=0x80,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB read,vname=Part7 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part0 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part1 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part2 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part3 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=16,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part4 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=32,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part5 -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=64,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part6 -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,ch_mask=128,fc_mask=0x7,multiplier=4,hname=OB write,vname=Part7 -# IOMMU events -ctr=0,unit=iio,ev_sel=0x40,umask=0x01,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Lookup,vname=Total -ctr=1,unit=iio,ev_sel=0x40,umask=0x20,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOTLB Miss,vname=Total -ctr=2,unit=iio,ev_sel=0x40,umask=0x80,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=Ctxt Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0x10,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=256T Cache Hit,vname=Total -ctr=0,unit=iio,ev_sel=0x41,umask=0x08,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=512G Cache Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x04,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=1G Cache Hit,vname=Total -ctr=2,unit=iio,ev_sel=0x41,umask=0x02,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=2M Cache Hit,vname=Total -ctr=3,unit=iio,ev_sel=0x41,umask=0xc0,ch_mask=0x0,fc_mask=0x0,multiplier=1,hname=IOMMU Mem Access,vname=Total diff --git a/_codeql_build_dir/bin/opCode-6-85.txt b/_codeql_build_dir/bin/opCode-6-85.txt deleted file mode 100644 index 73d93176..00000000 --- a/_codeql_build_dir/bin/opCode-6-85.txt +++ /dev/null @@ -1,26 +0,0 @@ -# Inbound (PCIe device DMA into system) payload events -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB write (bytes),vname=Part3 (4th x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part0 (1st x16/x8/x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part1 (2nd x4) -ctr=0,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=1,unit=iio,ev_sel=0x83,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=IB read (bytes),vname=Part3 (4th x4) -# Outbound (CPU MMIO to the PCIe device) payload events -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x4,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB read (bytes),vname=Part3 (4th x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part0 (1st x16/x8/x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=2,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part1 (2nd x4) -ctr=2,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=4,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part2 (2nd x8/3rd x4) -ctr=3,unit=iio,ev_sel=0xc0,umask=0x1,en=1,ch_mask=8,fc_mask=0x7,multiplier=4,hname=OB write (bytes),vname=Part3 (4th x4) -# VTd events -ctr=0,unit=iio,ev_sel=0x41,umask=0x1,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Hit,vname=Total -ctr=1,unit=iio,ev_sel=0x41,umask=0x20,en=1,ch_mask=1,fc_mask=0x7,multiplier=1,hname=IOTLB Miss,vname=Total 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- - -#============================================================================= -# Special targets to cleanup operation of make. - -# Special rule to run CMake to check the build system integrity. -# No rule that depends on this can have commands that come from listfiles -# because they might be regenerated. -cmake_check_build_system: - cd /home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir && $(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0 -.PHONY : cmake_check_build_system - diff --git a/_codeql_build_dir/tests/cmake_install.cmake b/_codeql_build_dir/tests/cmake_install.cmake deleted file mode 100644 index 15773584..00000000 --- a/_codeql_build_dir/tests/cmake_install.cmake +++ /dev/null @@ -1,50 +0,0 @@ -# Install script for directory: /home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/tests - -# Set the install prefix -if(NOT DEFINED CMAKE_INSTALL_PREFIX) - set(CMAKE_INSTALL_PREFIX "/usr/local") -endif() -string(REGEX REPLACE "/$" "" CMAKE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}") - -# Set the install configuration name. -if(NOT DEFINED CMAKE_INSTALL_CONFIG_NAME) - if(BUILD_TYPE) - string(REGEX REPLACE "^[^A-Za-z0-9_]+" "" - CMAKE_INSTALL_CONFIG_NAME "${BUILD_TYPE}") - else() - set(CMAKE_INSTALL_CONFIG_NAME "Release") - endif() - message(STATUS "Install configuration: \"${CMAKE_INSTALL_CONFIG_NAME}\"") -endif() - -# Set the component getting installed. -if(NOT CMAKE_INSTALL_COMPONENT) - if(COMPONENT) - message(STATUS "Install component: \"${COMPONENT}\"") - set(CMAKE_INSTALL_COMPONENT "${COMPONENT}") - else() - set(CMAKE_INSTALL_COMPONENT) - endif() -endif() - -# Install shared libraries without execute permission? -if(NOT DEFINED CMAKE_INSTALL_SO_NO_EXE) - set(CMAKE_INSTALL_SO_NO_EXE "1") -endif() - -# Is this installation the result of a crosscompile? -if(NOT DEFINED CMAKE_CROSSCOMPILING) - set(CMAKE_CROSSCOMPILING "FALSE") -endif() - -# Set path to fallback-tool for dependency-resolution. -if(NOT DEFINED CMAKE_OBJDUMP) - set(CMAKE_OBJDUMP "/usr/bin/objdump") -endif() - -string(REPLACE ";" "\n" CMAKE_INSTALL_MANIFEST_CONTENT - "${CMAKE_INSTALL_MANIFEST_FILES}") -if(CMAKE_INSTALL_LOCAL_ONLY) - file(WRITE "/home/runner/work/applications.analyzers.pcm/applications.analyzers.pcm/_codeql_build_dir/tests/install_local_manifest.txt" - "${CMAKE_INSTALL_MANIFEST_CONTENT}") -endif() From 575626bb1c62c34b90d8de4b5210312459efb17a Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 31 Oct 2025 13:27:07 +0100 Subject: [PATCH 50/54] bump up FreeBSD version in the runner Change-Id: I784a9795d919f64661ee2a4b5238d254aef8ba48 --- .github/workflows/freebsd_build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/freebsd_build.yml b/.github/workflows/freebsd_build.yml index ed07c46b..c6b76a9b 100644 --- a/.github/workflows/freebsd_build.yml +++ b/.github/workflows/freebsd_build.yml @@ -30,7 +30,7 @@ jobs: memory: 2048 shell: sh operating_system: freebsd - version: '14.2' + version: '14.3' run: | sudo mkdir -p /usr/local/etc/pkg/repos sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf' From b4b1809f90671dacb406b3de51a4e3784d8ed5fe Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 31 Oct 2025 13:38:44 +0100 Subject: [PATCH 51/54] IGNORE_OSVERSION workaround Change-Id: I6885e0a19d532db44734c862b5f952b56946b590 --- .github/workflows/freebsd_build.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/freebsd_build.yml b/.github/workflows/freebsd_build.yml index c6b76a9b..1ffafe54 100644 --- a/.github/workflows/freebsd_build.yml +++ b/.github/workflows/freebsd_build.yml @@ -26,11 +26,13 @@ jobs: - name: build in FreeBSD VM id: build uses: cross-platform-actions/action@2d97d42e1972a17b045fd709a422f7e55a86230d + env: + IGNORE_OSVERSION: "yes" with: memory: 2048 shell: sh operating_system: freebsd - version: '14.3' + version: '14.2' run: | sudo mkdir -p /usr/local/etc/pkg/repos sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf' From 93c0e6a3bd6ec03f538c1077348d95aaacb20f53 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 31 Oct 2025 13:44:44 +0100 Subject: [PATCH 52/54] progagate variables Change-Id: I0141b6e3efae8796e598a9187e2ac63982380dd5 --- .github/workflows/freebsd_build.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/freebsd_build.yml b/.github/workflows/freebsd_build.yml index 1ffafe54..8a71b837 100644 --- a/.github/workflows/freebsd_build.yml +++ b/.github/workflows/freebsd_build.yml @@ -36,9 +36,9 @@ jobs: run: | sudo mkdir -p /usr/local/etc/pkg/repos sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf' - sudo pkg update -f - sudo pkg upgrade -y - sudo pkg install -y curl gmake cmake + sudo -E pkg update -f + sudo -E pkg upgrade -y + sudo -E pkg install -y curl gmake cmake pwd ls -lah whoami From a477160529818f09b4873181496f2060f2bd7da3 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 31 Oct 2025 13:48:59 +0100 Subject: [PATCH 53/54] other way to set IGNORE_OSVERSION Change-Id: Ic55c850906d195d43a677d341ed05198cad40152 --- .github/workflows/freebsd_build.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/freebsd_build.yml b/.github/workflows/freebsd_build.yml index 8a71b837..145e012f 100644 --- a/.github/workflows/freebsd_build.yml +++ b/.github/workflows/freebsd_build.yml @@ -26,14 +26,13 @@ jobs: - name: build in FreeBSD VM id: build uses: cross-platform-actions/action@2d97d42e1972a17b045fd709a422f7e55a86230d - env: - IGNORE_OSVERSION: "yes" with: memory: 2048 shell: sh operating_system: freebsd version: '14.2' run: | + export IGNORE_OSVERSION=yes sudo mkdir -p /usr/local/etc/pkg/repos sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf' sudo -E pkg update -f From c66d3907b8405cbaeb402454def86550607bf5b7 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 31 Oct 2025 13:58:11 +0100 Subject: [PATCH 54/54] fix freebsd_scan_build.yml Change-Id: Id2f57310e094759f41487cb9defaa0e19ac9f400 --- .github/workflows/freebsd_scan_build.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/.github/workflows/freebsd_scan_build.yml b/.github/workflows/freebsd_scan_build.yml index 1446eb42..b9a4375e 100644 --- a/.github/workflows/freebsd_scan_build.yml +++ b/.github/workflows/freebsd_scan_build.yml @@ -32,11 +32,12 @@ jobs: operating_system: freebsd version: '14.2' run: | + export IGNORE_OSVERSION=yes sudo mkdir -p /usr/local/etc/pkg/repos sudo sh -c 'echo "FreeBSD: { url: \"https://pkg.FreeBSD.org/\${ABI}/quarterly\", mirror_type: \"srv\", enabled: yes }" > /usr/local/etc/pkg/repos/FreeBSD.conf' - sudo pkg update -f - sudo pkg upgrade -y - sudo pkg install -y curl gmake cmake devel/llvm llvm + sudo -E pkg update -f + sudo -E pkg upgrade -y + sudo -E pkg install -y curl gmake cmake devel/llvm llvm pwd ls -lah whoami