diff --git a/.gitignore b/.gitignore index 4d60bcb..7552bee 100644 --- a/.gitignore +++ b/.gitignore @@ -1,8 +1,10 @@ work/ *.txt dumpfile -risc_test_program/merge_sort -risc_test_program/risc_test +sram_dumpfile +merge_sort +risc_test +blinky # ignore ModelSim generated files and directories (temp files and so on) [_@]* @@ -26,4 +28,53 @@ wlf* cov*/ transcript* sc_dpiheader.h -vsim.dbg \ No newline at end of file +vsim. + +# ignore Quartus II generated files +*_generation_script* +*_inst.vhd +*.bak +*.cmp +*.cdf +*.done +*.eqn +*.hex +*.html +*.jdi +*.jpg +*.mif +*.pin +*.pof +*.ptf.* +*.qar +*.qarlog +*.qws +*.rpt +*.smsg +*.sof +*.sopc_builder +*.summary +*.tcl +*.txt # Explicitly add any text files used +*~ +*example* +*sopc_* +# *.sdc # I want those timing files + +# ignore Quartus II generated folders +*/db/ +*/incremental_db/ +*/simulation/ +*/timing/ +*/testbench/ +*/*_sim/ +incremental_db/ +db/ +_output_files/ +PLLJ_PLLSPE_INFO.txt + +/xpacks +/.vscode +/build +*.o +/.pytest_cache \ No newline at end of file diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..e76657a --- /dev/null +++ b/Makefile @@ -0,0 +1,35 @@ +DIR := ./xpacks/.bin +SRC_DIR := ./tests/src +HEX_DIR := ./tests/hex +OBJ_DIR := ./tests/obj + +CC := $(DIR)/riscv-none-elf-gcc +PYTHON := python3 +OBJDUMP := $(DIR)/riscv-none-elf-objdump +OBJCOPY := $(DIR)/riscv-none-elf-objcopy +MEM_WORD_LENGTH := 4 + +CFLAGS := -O0 -ffunction-sections -Xlinker -g -T./tests/risc.ld -mbig-endian -nostdlib -ffreestanding -fno-pie -fno-stack-protector -Wall -mno-fdiv -march=rv32i -mabi=ilp32 + +SRCS = $(wildcard $(SRC_DIR)/*.c) + +PROGS = $(patsubst ${SRC_DIR}/%.c,%,$(SRCS)) +.PHONY: $(PROGS) + +all: $(PROGS) + +$(PROGS): + $(CC) $(CFLAGS) -o $(OBJ_DIR)/$@.o $(SRC_DIR)/$@.c + $(OBJCOPY) --remove-section=.comment --reverse-bytes=$(MEM_WORD_LENGTH) \ + --verilog-data-width $(MEM_WORD_LENGTH) \ + $(OBJ_DIR)/$@.o -O verilog $(HEX_DIR)/$@.hex + +test: + python3 -m pytest ./tests + +dump: + $(OBJDUMP) -D --disassembler-options=no-aliases $(OBJ_DIR)/$(FILE) + +clean: + rm -r tests/obj/* tests/hex/* build + diff --git a/README.md b/README.md index 86a4adb..7c0a48f 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,9 @@ # riscv-processor -RISCV processor in verilog. -Made for educational purposes. - -Test programs are in risc\_test\_program. +## TODO: +1. Fix sram in simulation to make sure it works properly. +2. Make sure logic works on MAX10 +3. Implement Linter and automatic formatter for Verilog +4. Design Cache +5. Refactor Verilog code to look neater. +6. Get SDRAM controller working diff --git a/data_addr_bus_controller.v b/data_addr_bus_controller.v deleted file mode 100644 index a4ba12b..0000000 --- a/data_addr_bus_controller.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1us/100ns - -`define READ_SIZE 32 -module data_addr_bus_controller (imem_data_out, dmem_data_out, data_out, imem_ready, dmem_ready, mem_ready, - imem_addr, dmem_addr, mem_addr, dmem_use); - - output reg [`READ_SIZE-1:0] imem_data_out; - output reg [`READ_SIZE-1:0] dmem_data_out; - output reg [31:0] mem_addr; - output imem_ready; - output dmem_ready; - input [`READ_SIZE-1:0] data_out; - input mem_ready; - input dmem_use; - input [31:0] imem_addr; - input [31:0] dmem_addr; - - assign imem_data_out = data_out & {`READ_SIZE{mem_ready}} & {`READ_SIZE{~dmem_use}}; - assign dmem_data_out = data_out & {`READ_SIZE{mem_ready}}; - assign imem_ready = mem_ready & ~dmem_use; - assign dmem_ready = mem_ready; - - always @(*) begin - if (dmem_use) begin - mem_addr = dmem_addr; - end - else begin - mem_addr = imem_addr; - end - end - -endmodule \ No newline at end of file diff --git a/de10_lite/Sdram_Control.v b/de10_lite/Sdram_Control.v deleted file mode 100644 index 7539276..0000000 --- a/de10_lite/Sdram_Control.v +++ /dev/null @@ -1,437 +0,0 @@ -module Sdram_Control( - // HOST Side - REF_CLK, - RESET_N, - CLK, - // FIFO Write Side - WR_DATA, - WR, - WR_ADDR, - WR_MAX_ADDR, - WR_LENGTH, - WR_LOAD, - WR_CLK, - WR_FULL, - WR_USE, - // FIFO Read Side - RD_DATA, - RD, - RD_ADDR, - RD_MAX_ADDR, - RD_LENGTH, - RD_LOAD, - RD_CLK, - RD_EMPTY, - RD_USE, - // SDRAM Side - SA, - BA, - CS_N, - CKE, - RAS_N, - CAS_N, - WE_N, - DQ, - DQM, - SDR_CLK - ); - - -`include "Sdram_Params.h" -// HOST Side -input REF_CLK; //System Clock -input RESET_N; //System Reset -// FIFO Write Side 1 -input [`DSIZE-1:0] WR_DATA; //Data input -input WR; //Write Request -input [`ASIZE-1:0] WR_ADDR; //Write start address -input [`ASIZE-1:0] WR_MAX_ADDR; //Write max address -input [8:0] WR_LENGTH; //Write length -input WR_LOAD; //Write register load & fifo clear -input WR_CLK; //Write fifo clock -output WR_FULL; //Write fifo full -output [15:0] WR_USE; //Write fifo usedw - -// FIFO Read Side 1 -output [`DSIZE-1:0] RD_DATA; //Data output -input RD; //Read Request -input [`ASIZE-1:0] RD_ADDR; //Read start address -input [`ASIZE-1:0] RD_MAX_ADDR; //Read max address -input [8:0] RD_LENGTH; //Read length -input RD_LOAD; //Read register load & fifo clear -input RD_CLK; //Read fifo clock -output RD_EMPTY; //Read fifo empty -output [15:0] RD_USE; //Read fifo usedw -// SDRAM Side -output [`SASIZE-1:0] SA; //SDRAM address output -output [1:0] BA; //SDRAM bank address -output [1:0] CS_N; //SDRAM Chip Selects -output CKE; //SDRAM clock enable -output RAS_N; //SDRAM Row address Strobe -output CAS_N; //SDRAM Column address Strobe -output WE_N; //SDRAM write enable -inout [`DSIZE-1:0] DQ; //SDRAM data bus -output [`DSIZE/8-1:0] DQM; //SDRAM data mask lines -output SDR_CLK; //SDRAM clock -// Internal Registers/Wires -// Controller -reg [`ASIZE-1:0] mADDR; //Internal address -reg [8:0] mLENGTH; //Internal length -reg [`ASIZE-1:0] rWR_ADDR; //Register write address - -reg [`ASIZE-1:0] rRD_ADDR; //Register read address -reg WR_MASK; //Write port active mask -reg RD_MASK; //Read port active mask -reg mWR_DONE; //Flag write done, 1 pulse SDR_CLK -reg mRD_DONE; //Flag read done, 1 pulse SDR_CLK -reg mWR,Pre_WR; //Internal WR edge capture -reg mRD,Pre_RD; //Internal RD edge capture -reg [9:0] ST; //Controller status -reg [1:0] CMD; //Controller command -reg PM_STOP; //Flag page mode stop -reg PM_DONE; //Flag page mode done -reg Read; //Flag read active -reg Write; //Flag write active -reg [`DSIZE-1:0] mDATAOUT; //Controller Data output - -wire [`DSIZE-1:0] mDATAIN; //Controller Data input 2 -wire CMDACK; //Controller command acknowledgement -// DRAM Control -reg [`DSIZE/8-1:0] DQM; //SDRAM data mask lines -reg [`SASIZE-1:0] SA; //SDRAM address output -reg [1:0] BA; //SDRAM bank address -reg [1:0] CS_N; //SDRAM Chip Selects -reg CKE; //SDRAM clock enable -reg RAS_N; //SDRAM Row address Strobe -reg CAS_N; //SDRAM Column address Strobe -reg WE_N; //SDRAM write enable -wire [`DSIZE-1:0] DQOUT; //SDRAM data out link -wire [`DSIZE/8-1:0] IDQM; //SDRAM data mask lines -wire [`SASIZE-1:0] ISA; //SDRAM address output -wire [1:0] IBA; //SDRAM bank address -wire [1:0] ICS_N; //SDRAM Chip Selects -wire ICKE; //SDRAM clock enable -wire IRAS_N; //SDRAM Row address Strobe -wire ICAS_N; //SDRAM Column address Strobe -wire IWE_N; //SDRAM write enable -// FIFO Control -reg OUT_VALID; //Output data request to read side fifo -reg IN_REQ; //Input data request to write side fifo -wire [15:0] write_side_fifo_rusedw; -wire [15:0] read_side_fifo_wusedw; - -// DRAM Internal Control -wire [`ASIZE-1:0] saddr; -wire load_mode; -wire nop; -wire reada; -wire writea; -wire refresh; -wire precharge; -wire oe; -wire ref_ack; -wire ref_req; -wire init_req; -wire cm_ack; -wire active; -output CLK; - -//sdram_pll0 sdram_pll0_inst( -// .refclk(REF_CLK), // refclk.clk -// .rst(1'b0), // reset.reset -// .outclk_0(CLK), // outclk0.clk -// .outclk_1(SDR_CLK), // outclk1.clk -// .locked() // locked.export -// ); - - -sdram_pll0 sdram_pll0_inst( - .areset(), - .inclk0(REF_CLK), - .c0(CLK), - .c1(SDR_CLK), - .locked()); - -control_interface control1 ( - .CLK(CLK), - .RESET_N(RESET_N), - .CMD(CMD), - .ADDR(mADDR), - .REF_ACK(ref_ack), - .CM_ACK(cm_ack), - .NOP(nop), - .READA(reada), - .WRITEA(writea), - .REFRESH(refresh), - .PRECHARGE(precharge), - .LOAD_MODE(load_mode), - .SADDR(saddr), - .REF_REQ(ref_req), - .INIT_REQ(init_req), - .CMD_ACK(CMDACK) - ); - -command command1( - .CLK(CLK), - .RESET_N(RESET_N), - .SADDR(saddr), - .NOP(nop), - .READA(reada), - .WRITEA(writea), - .REFRESH(refresh), - .LOAD_MODE(load_mode), - .PRECHARGE(precharge), - .REF_REQ(ref_req), - .INIT_REQ(init_req), - .REF_ACK(ref_ack), - .CM_ACK(cm_ack), - .OE(oe), - .PM_STOP(PM_STOP), - .PM_DONE(PM_DONE), - .SA(ISA), - .BA(IBA), - .CS_N(ICS_N), - .CKE(ICKE), - .RAS_N(IRAS_N), - .CAS_N(ICAS_N), - .WE_N(IWE_N) - ); - -sdr_data_path data_path1( - .CLK(CLK), - .RESET_N(RESET_N), - .DATAIN(mDATAIN), - .DM(2'b00), - .DQOUT(DQOUT), - .DQM(IDQM) - ); - -Sdram_WR_FIFO write_fifo1( - .data(WR_DATA), - .wrreq(WR), - .wrclk(WR_CLK), - .aclr(WR_LOAD), - .rdreq(IN_REQ&WR_MASK), - .rdclk(CLK), - .q(mDATAIN), - .wrfull(WR_FULL), - .wrusedw(WR_USE), - .rdusedw(write_side_fifo_rusedw) - ); - -reg flag; -always@(posedge CLK or negedge RESET_N) -begin - if(!RESET_N) - flag <= 0; - else - begin - if(write_side_fifo_rusedw==WR_LENGTH) - flag <= 1; - end -end - - -Sdram_RD_FIFO read_fifo1( - .data(mDATAOUT), - .wrreq(OUT_VALID&RD_MASK), - .wrclk(CLK), - .aclr(RD_LOAD), - .rdreq(RD), - .rdclk(RD_CLK), - .q(RD_DATA), - .wrusedw(read_side_fifo_wusedw), - .rdempty(RD_EMPTY), - .rdusedw(RD_USE) - ); - - -always @(posedge CLK) -begin - SA <= (ST==SC_CL+mLENGTH) ? 13'h200 : ISA; - BA <= IBA; - CS_N <= ICS_N; - CKE <= ICKE; - RAS_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IRAS_N; - CAS_N <= (ST==SC_CL+mLENGTH) ? 1'b1 : ICAS_N; - WE_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IWE_N; - PM_STOP <= (ST==SC_CL+mLENGTH) ? 1'b1 : 1'b0; - PM_DONE <= (ST==SC_CL+SC_RCD+mLENGTH+2) ? 1'b1 : 1'b0; - DQM <= ( active && (ST>=SC_CL) ) ? ( ((ST==SC_CL+mLENGTH) && Write)? 2'b11 : 2'b00 ) : 2'b11 ; - mDATAOUT<= DQ; -end - -assign DQ = oe ? DQOUT : `DSIZE'hzzzz; -assign active = Read | Write; - -always@(posedge CLK or negedge RESET_N) -begin - if(RESET_N==0) - begin - CMD <= 0; - ST <= 0; - Pre_RD <= 0; - Pre_WR <= 0; - Read <= 0; - Write <= 0; - OUT_VALID <= 0; - IN_REQ <= 0; - mWR_DONE <= 0; - mRD_DONE <= 0; - end - else - begin - Pre_RD <= mRD; - Pre_WR <= mWR; - case(ST) - 0: begin - if({Pre_RD,mRD}==2'b01) - begin - Read <= 1; - Write <= 0; - CMD <= 2'b01; - ST <= 1; - end - else if({Pre_WR,mWR}==2'b01) - begin - Read <= 0; - Write <= 1; - CMD <= 2'b10; - ST <= 1; - end - end - 1: begin - if(CMDACK==1) - begin - CMD<=2'b00; - ST<=2; - end - end - default: - begin - if(ST!=SC_CL+SC_RCD+mLENGTH+1) - ST<=ST+1; - else - ST<=0; - end - endcase - - if(Read) - begin - if(ST==SC_CL+SC_RCD+1) - OUT_VALID <= 1; - else if(ST==SC_CL+SC_RCD+mLENGTH+1) - begin - OUT_VALID <= 0; - Read <= 0; - mRD_DONE <= 1; - end - end - else - mRD_DONE <= 0; - - if(Write) - begin - if(ST==SC_CL-1) - IN_REQ <= 1; - else if(ST==SC_CL+mLENGTH-1) - IN_REQ <= 0; - else if(ST==SC_CL+SC_RCD+mLENGTH) - begin - Write <= 0; - mWR_DONE<= 1; - end - end - else - mWR_DONE<= 0; - - end -end -// Internal Address & Length Control -always@(posedge CLK or negedge RESET_N) -begin - if(!RESET_N) - begin - rWR_ADDR <= WR_ADDR; - rRD_ADDR <= RD_ADDR; - end - else - begin - // Write Side - if(WR_LOAD) - rWR_ADDR <= WR_ADDR; - else if(mWR_DONE&WR_MASK) - begin - if(rWR_ADDR= WR_LENGTH) && (WR_LENGTH!=0) ) - begin - mADDR <= rWR_ADDR; - mLENGTH <= WR_LENGTH; - WR_MASK <= 1'b1; - RD_MASK <= 1'b0; - mWR <= 1; - mRD <= 0; - end - // Read Side - else if( (read_side_fifo_wusedw < RD_LENGTH) ) - begin - mADDR <= rRD_ADDR; - mLENGTH <= RD_LENGTH; - WR_MASK <= 1'b0; - RD_MASK <= 1'b1; - mWR <= 0; - mRD <= 1; - end - - end - if(mWR_DONE) - begin - WR_MASK <= 0; - mWR <= 0; - end - if(mRD_DONE) - begin - RD_MASK <= 0; - mRD <= 0; - end - end -end - -endmodule diff --git a/de10_lite/Sdram_Params.h b/de10_lite/Sdram_Params.h deleted file mode 100644 index db0640e..0000000 --- a/de10_lite/Sdram_Params.h +++ /dev/null @@ -1,64 +0,0 @@ -// Address Space Parameters - -`define ROWSTART 10 -`define ROWSIZE 13 - -`define COLSTART 0 -`define COLSIZE 10 - -`define BANKSTART 23 -`define BANKSIZE 2 - - -// Address and Data Bus Sizes -`define SASIZE 13 - -`define ASIZE 25 // total address width of the SDRAM -`define DSIZE 16 // Width of data bus to SDRAMS - -//parameter INIT_PER = 100; // For Simulation - -// Controller Parameter -//////////// 133 MHz /////////////// -/* -parameter INIT_PER = 32000; -parameter REF_PER = 1536; -parameter SC_CL = 3; -parameter SC_RCD = 3; -parameter SC_RRD = 7; -parameter SC_PM = 1; -parameter SC_BL = 1; -*/ -/////////////////////////////////////// -//////////// 100 MHz /////////////// -parameter INIT_PER = 24000; -parameter REF_PER = 1024; -parameter SC_CL = 3; -parameter SC_RCD = 3; -parameter SC_RRD = 7; -parameter SC_PM = 1; -parameter SC_BL = 1; -/////////////////////////////////////// -//////////// 50 MHz /////////////// -/* -parameter INIT_PER = 12000; -parameter REF_PER = 512; -parameter SC_CL = 3; -parameter SC_RCD = 3; -parameter SC_RRD = 7; -parameter SC_PM = 1; -parameter SC_BL = 1; -*/ -/////////////////////////////////////// - -// SDRAM Parameter -parameter SDR_BL = (SC_PM == 1)? 3'b111 : - (SC_BL == 1)? 3'b000 : - (SC_BL == 2)? 3'b001 : - (SC_BL == 4)? 3'b010 : - 3'b011 ; -parameter SDR_BT = 1'b0; // Sequential - // 1'b1: // Interteave -parameter SDR_CL = (SC_CL == 2)? 3'b10: - 3'b11; - diff --git a/de10_lite/Sdram_RD_FIFO.qip b/de10_lite/Sdram_RD_FIFO.qip deleted file mode 100644 index b02f1dd..0000000 --- a/de10_lite/Sdram_RD_FIFO.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "FIFO" -set_global_assignment -name IP_TOOL_VERSION "16.0" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_RD_FIFO.v"] diff --git a/de10_lite/Sdram_RD_FIFO.v b/de10_lite/Sdram_RD_FIFO.v deleted file mode 100644 index 7d06dc0..0000000 --- a/de10_lite/Sdram_RD_FIFO.v +++ /dev/null @@ -1,196 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: Sdram_RD_FIFO.v -// Megafunction Name(s): -// dcfifo -// -// Simulation Library Files(s): -// -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 16.0.2 Build 222 07/20/2016 SJ Standard Edition -// ************************************************************ - - -//Copyright (C) 1991-2016 Altera Corporation. All rights reserved. -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, the Altera Quartus Prime License Agreement, -//the Altera MegaCore Function License Agreement, or other -//applicable license agreement, including, without limitation, -//that your use is for the sole purpose of programming logic -//devices manufactured by Altera and sold by Altera or its -//authorized distributors. Please refer to the applicable -//agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module Sdram_RD_FIFO ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdusedw, - wrfull, - wrusedw); - - input aclr; - input [15:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [15:0] q; - output rdempty; - output [8:0] rdusedw; - output wrfull; - output [8:0] wrusedw; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 aclr; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [15:0] sub_wire0; - wire sub_wire1; - wire [8:0] sub_wire2; - wire sub_wire3; - wire [8:0] sub_wire4; - wire [15:0] q = sub_wire0[15:0]; - wire rdempty = sub_wire1; - wire [8:0] rdusedw = sub_wire2[8:0]; - wire wrfull = sub_wire3; - wire [8:0] wrusedw = sub_wire4[8:0]; - - dcfifo dcfifo_component ( - .aclr (aclr), - .data (data), - .rdclk (rdclk), - .rdreq (rdreq), - .wrclk (wrclk), - .wrreq (wrreq), - .q (sub_wire0), - .rdempty (sub_wire1), - .rdusedw (sub_wire2), - .wrfull (sub_wire3), - .wrusedw (sub_wire4), - .eccstatus (), - .rdfull (), - .wrempty ()); - defparam - dcfifo_component.intended_device_family = "MAX 10", - dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", - dcfifo_component.lpm_numwords = 512, - dcfifo_component.lpm_showahead = "OFF", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 16, - dcfifo_component.lpm_widthu = 9, - dcfifo_component.overflow_checking = "ON", - dcfifo_component.rdsync_delaypipe = 4, - dcfifo_component.read_aclr_synch = "OFF", - dcfifo_component.underflow_checking = "ON", - dcfifo_component.use_eab = "ON", - dcfifo_component.write_aclr_synch = "OFF", - dcfifo_component.wrsync_delaypipe = 4; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "512" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "1" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: diff_widths NUMERIC "0" -// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" -// Retrieval info: PRIVATE: output_width NUMERIC "16" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" -// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" -// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" -// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]" -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" -// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_bb.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_wave*.jpg FALSE diff --git a/de10_lite/Sdram_WR_FIFO.qip b/de10_lite/Sdram_WR_FIFO.qip deleted file mode 100644 index badcd85..0000000 --- a/de10_lite/Sdram_WR_FIFO.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "FIFO" -set_global_assignment -name IP_TOOL_VERSION "16.0" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_WR_FIFO.v"] diff --git a/de10_lite/Sdram_WR_FIFO.v b/de10_lite/Sdram_WR_FIFO.v deleted file mode 100644 index 8aa255f..0000000 --- a/de10_lite/Sdram_WR_FIFO.v +++ /dev/null @@ -1,196 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: Sdram_WR_FIFO.v -// Megafunction Name(s): -// dcfifo -// -// Simulation Library Files(s): -// -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 16.0.2 Build 222 07/20/2016 SJ Standard Edition -// ************************************************************ - - -//Copyright (C) 1991-2016 Altera Corporation. All rights reserved. -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, the Altera Quartus Prime License Agreement, -//the Altera MegaCore Function License Agreement, or other -//applicable license agreement, including, without limitation, -//that your use is for the sole purpose of programming logic -//devices manufactured by Altera and sold by Altera or its -//authorized distributors. Please refer to the applicable -//agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module Sdram_WR_FIFO ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - rdusedw, - wrfull, - wrusedw); - - input aclr; - input [15:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [15:0] q; - output rdempty; - output [8:0] rdusedw; - output wrfull; - output [8:0] wrusedw; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 aclr; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [15:0] sub_wire0; - wire sub_wire1; - wire [8:0] sub_wire2; - wire sub_wire3; - wire [8:0] sub_wire4; - wire [15:0] q = sub_wire0[15:0]; - wire rdempty = sub_wire1; - wire [8:0] rdusedw = sub_wire2[8:0]; - wire wrfull = sub_wire3; - wire [8:0] wrusedw = sub_wire4[8:0]; - - dcfifo dcfifo_component ( - .aclr (aclr), - .data (data), - .rdclk (rdclk), - .rdreq (rdreq), - .wrclk (wrclk), - .wrreq (wrreq), - .q (sub_wire0), - .rdempty (sub_wire1), - .rdusedw (sub_wire2), - .wrfull (sub_wire3), - .wrusedw (sub_wire4), - .eccstatus (), - .rdfull (), - .wrempty ()); - defparam - dcfifo_component.intended_device_family = "MAX 10", - dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", - dcfifo_component.lpm_numwords = 512, - dcfifo_component.lpm_showahead = "OFF", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 16, - dcfifo_component.lpm_widthu = 9, - dcfifo_component.overflow_checking = "ON", - dcfifo_component.rdsync_delaypipe = 4, - dcfifo_component.read_aclr_synch = "OFF", - dcfifo_component.underflow_checking = "ON", - dcfifo_component.use_eab = "ON", - dcfifo_component.write_aclr_synch = "OFF", - dcfifo_component.wrsync_delaypipe = 4; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "4" -// Retrieval info: PRIVATE: Depth NUMERIC "512" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "1" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: diff_widths NUMERIC "0" -// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" -// Retrieval info: PRIVATE: output_width NUMERIC "16" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" -// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" -// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" -// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" -// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" -// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]" -// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" -// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" -// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]" -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0 -// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 -// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_bb.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_wave*.jpg FALSE diff --git a/de10_lite/command.v b/de10_lite/command.v deleted file mode 100644 index 6bc0248..0000000 --- a/de10_lite/command.v +++ /dev/null @@ -1,447 +0,0 @@ -module command( - CLK, - RESET_N, - SADDR, - NOP, - READA, - WRITEA, - REFRESH, - PRECHARGE, - LOAD_MODE, - REF_REQ, - INIT_REQ, - PM_STOP, - PM_DONE, - REF_ACK, - CM_ACK, - OE, - SA, - BA, - CS_N, - CKE, - RAS_N, - CAS_N, - WE_N - ); - -`include "Sdram_Params.h" - -input CLK; // System Clock -input RESET_N; // System Reset -input [`ASIZE-1:0] SADDR; // Address -input NOP; // Decoded NOP command -input READA; // Decoded READA command -input WRITEA; // Decoded WRITEA command -input REFRESH; // Decoded REFRESH command -input PRECHARGE; // Decoded PRECHARGE command -input LOAD_MODE; // Decoded LOAD_MODE command -input REF_REQ; // Hidden refresh request -input INIT_REQ; // Hidden initial request -input PM_STOP; // Page mode stop -input PM_DONE; // Page mode done -output REF_ACK; // Refresh request acknowledge -output CM_ACK; // Command acknowledge -output OE; // OE signal for data path module -output [`SASIZE-1:0] SA; // SDRAM address -output [1:0] BA; // SDRAM bank address -output [1:0] CS_N; // SDRAM chip selects -output CKE; // SDRAM clock enable -output RAS_N; // SDRAM RAS -output CAS_N; // SDRAM CAS -output WE_N; // SDRAM WE_N - - -reg CM_ACK; -reg REF_ACK; -reg OE; -reg [`SASIZE-1:0] SA; -reg [1:0] BA; -reg [1:0] CS_N; -reg CKE; -reg RAS_N; -reg CAS_N; -reg WE_N; - - - -// Internal signals -reg do_reada; -reg do_writea; -reg do_refresh; -reg do_precharge; -reg do_load_mode; -reg do_initial; -reg command_done; -reg [7:0] command_delay; -reg [1:0] rw_shift; -reg do_act; -reg rw_flag; -reg do_rw; -reg [6:0] oe_shift; -reg oe1; -reg oe2; -reg oe3; -reg oe4; -reg [3:0] rp_shift; -reg rp_done; -reg ex_read; -reg ex_write; - -wire [`ROWSIZE - 1:0] rowaddr; -wire [`COLSIZE - 1:0] coladdr; -wire [`BANKSIZE - 1:0] bankaddr; - -assign rowaddr = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART]; // assignment of the row address bits from SADDR -assign coladdr = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART]; // assignment of the column address bits -assign bankaddr = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART]; // assignment of the bank address bits - - - -// This always block monitors the individual command lines and issues a command -// to the next stage if there currently another command already running. -// -always @(posedge CLK or negedge RESET_N) -begin - if (RESET_N == 0) - begin - do_reada <= 0; - do_writea <= 0; - do_refresh <= 0; - do_precharge <= 0; - do_load_mode <= 0; - do_initial <= 0; - command_done <= 0; - command_delay <= 0; - rw_flag <= 0; - rp_shift <= 0; - rp_done <= 0; - ex_read <= 0; - ex_write <= 0; - end - - else - begin - -// Issue the appropriate command if the sdram is not currently busy - if( INIT_REQ == 1 ) - begin - do_reada <= 0; - do_writea <= 0; - do_refresh <= 0; - do_precharge <= 0; - do_load_mode <= 0; - do_initial <= 1; - command_done <= 0; - command_delay <= 0; - rw_flag <= 0; - rp_shift <= 0; - rp_done <= 0; - ex_read <= 0; - ex_write <= 0; - end - else - begin - do_initial <= 0; - - if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0 // Refresh - & do_reada == 0 & do_writea == 0) - do_refresh <= 1; - else - do_refresh <= 0; - - if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0)) // READA - begin - do_reada <= 1; - ex_read <= 1; - end - else - do_reada <= 0; - - if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0)) // WRITEA - begin - do_writea <= 1; - ex_write <= 1; - end - else - do_writea <= 0; - - if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0)) // PRECHARGE - do_precharge <= 1; - else - do_precharge <= 0; - - if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0)) // LOADMODE - do_load_mode <= 1; - else - do_load_mode <= 0; - -// set command_delay shift register and command_done flag -// The command delay shift register is a timer that is used to ensure that -// the SDRAM devices have had sufficient time to finish the last command. - - if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1) - | (do_load_mode == 1)) - begin - command_delay <= 8'b11111111; - command_done <= 1; - rw_flag <= do_reada; - end - - else - begin - command_done <= command_delay[0]; // the command_delay shift operation - command_delay <= (command_delay>>1); - end - - - // start additional timer that is used for the refresh, writea, reada commands - if (command_delay[0] == 0 & command_done == 1) - begin - rp_shift <= 4'b1111; - rp_done <= 1; - end - else - begin - if(SC_PM == 0) - begin - rp_shift <= (rp_shift>>1); - rp_done <= rp_shift[0]; - end - else - begin - if( (ex_read == 0) && (ex_write == 0) ) - begin - rp_shift <= (rp_shift>>1); - rp_done <= rp_shift[0]; - end - else - begin - if( PM_STOP==1 ) - begin - rp_shift <= (rp_shift>>1); - rp_done <= rp_shift[0]; - ex_read <= 1'b0; - ex_write <= 1'b0; - end - end - end - end - end - end -end - - -// logic that generates the OE signal for the data path module -// For normal burst write he duration of OE is dependent on the configured burst length. -// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command -// and is left on until a PRECHARGE(page burst terminate) is detected. -// -always @(posedge CLK or negedge RESET_N) -begin - if (RESET_N == 0) - begin - oe_shift <= 0; - oe1 <= 0; - oe2 <= 0; - OE <= 0; - end - else - begin - if (SC_PM == 0) - begin - if (do_writea == 1) - begin - if (SC_BL == 1) // Set the shift register to the appropriate - oe_shift <= 0; // value based on burst length. - else if (SC_BL == 2) - oe_shift <= 1; - else if (SC_BL == 4) - oe_shift <= 7; - else if (SC_BL == 8) - oe_shift <= 127; - oe1 <= 1; - end - else - begin - oe_shift <= (oe_shift>>1); - oe1 <= oe_shift[0]; - oe2 <= oe1; - oe3 <= oe2; - oe4 <= oe3; - if (SC_RCD == 2) - OE <= oe3; - else - OE <= oe4; - end - end - else - begin - if (do_writea == 1) // OE generation for page mode accesses - oe4 <= 1; - else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 ) - oe4 <= 0; - OE <= oe4; - end - - end -end - - - - -// This always block tracks the time between the activate command and the -// subsequent WRITEA or READA command, RC. The shift register is set using -// the configuration register setting SC_RCD. The shift register is loaded with -// a single '1' with the position within the register dependent on SC_RCD. -// When the '1' is shifted out of the register it sets so_rw which triggers -// a writea or reada command -// -always @(posedge CLK or negedge RESET_N) -begin - if (RESET_N == 0) - begin - rw_shift <= 0; - do_rw <= 0; - end - - else - begin - - if ((do_reada == 1) | (do_writea == 1)) - begin - if (SC_RCD == 1) // Set the shift register - do_rw <= 1; - else if (SC_RCD == 2) - rw_shift <= 1; - else if (SC_RCD == 3) - rw_shift <= 2; - end - else - begin - rw_shift <= (rw_shift>>1); - do_rw <= rw_shift[0]; - end - end -end - -// This always block generates the command acknowledge, CM_ACK, signal. -// It also generates the acknowledge signal, REF_ACK, that acknowledges -// a refresh request that was generated by the internal refresh timer circuit. -always @(posedge CLK or negedge RESET_N) -begin - - if (RESET_N == 0) - begin - CM_ACK <= 0; - REF_ACK <= 0; - end - - else - begin - if (do_refresh == 1 & REF_REQ == 1) // Internal refresh timer refresh request - REF_ACK <= 1; - else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1) // externa commands - | (do_load_mode)) - CM_ACK <= 1; - else - begin - REF_ACK <= 0; - CM_ACK <= 0; - end - end -end - - - - - - - -// This always block generates the address, cs, cke, and command signals(ras,cas,wen) -// -always @(posedge CLK ) begin - if (RESET_N==0) begin - SA <= 0; - BA <= 0; - CS_N <= 1; - RAS_N <= 1; - CAS_N <= 1; - WE_N <= 1; - CKE <= 0; - end - else begin - CKE <= 1; - -// Generate SA - if (do_writea == 1 | do_reada == 1) // ACTIVATE command is being issued, so present the row address - SA <= rowaddr; - else - SA <= coladdr; // else alway present column address - if ((do_rw==1) | (do_precharge)) - SA[10] <= !SC_PM; // set SA[10] for autoprecharge read/write or for a precharge all command - // don't set it if the controller is in page mode. - if (do_precharge==1 | do_load_mode==1) - BA <= 0; // Set BA=0 if performing a precharge or load_mode command - else - BA <= bankaddr[1:0]; // else set it with the appropriate address bits - - if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1) - CS_N <= 0; // Select both chip selects if performing - else // refresh, precharge(all) or load_mode - begin -// CS_N[0] <= SADDR[`ASIZE-1]; // else set the chip selects based off of the -// CS_N[1] <= ~SADDR[`ASIZE-1]; // msb address bit - CS_N <= 0; - end - - if(do_load_mode==1) - SA <= {2'b00,SDR_CL,SDR_BT,SDR_BL}; - - -//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N -//depending on the issued command. -// - if ( do_refresh==1 ) begin // Refresh: S=00, RAS=0, CAS=0, WE=1 - RAS_N <= 0; - CAS_N <= 0; - WE_N <= 1; - end - else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin // burst terminate if write is active - RAS_N <= 1; - CAS_N <= 1; - WE_N <= 0; - end - else if (do_precharge==1) begin // Precharge All: S=00, RAS=0, CAS=1, WE=0 - RAS_N <= 0; - CAS_N <= 1; - WE_N <= 0; - end - else if (do_load_mode==1) begin // Mode Write: S=00, RAS=0, CAS=0, WE=0 - RAS_N <= 0; - CAS_N <= 0; - WE_N <= 0; - end - else if (do_reada == 1 | do_writea == 1) begin // Activate: S=01 or 10, RAS=0, CAS=1, WE=1 - RAS_N <= 0; - CAS_N <= 1; - WE_N <= 1; - end - else if (do_rw == 1) begin // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1 - RAS_N <= 1; - CAS_N <= 0; - WE_N <= rw_flag; - end - else if (do_initial ==1) begin - RAS_N <= 1; - CAS_N <= 1; - WE_N <= 1; - end - else begin // No Operation: RAS=1, CAS=1, WE=1 - RAS_N <= 1; - CAS_N <= 1; - WE_N <= 1; - end - end -end - -endmodule diff --git a/de10_lite/control_interface.v b/de10_lite/control_interface.v deleted file mode 100644 index 2a96b40..0000000 --- a/de10_lite/control_interface.v +++ /dev/null @@ -1,198 +0,0 @@ -module control_interface( - CLK, - RESET_N, - CMD, - ADDR, - REF_ACK, - INIT_ACK, - CM_ACK, - NOP, - READA, - WRITEA, - REFRESH, - PRECHARGE, - LOAD_MODE, - SADDR, - REF_REQ, - INIT_REQ, - CMD_ACK - ); - -`include "Sdram_Params.h" - -input CLK; // System Clock -input RESET_N; // System Reset -input [2:0] CMD; // Command input -input [`ASIZE-1:0] ADDR; // Address -input REF_ACK; // Refresh request acknowledge -input INIT_ACK; // Initial request acknowledge -input CM_ACK; // Command acknowledge -output NOP; // Decoded NOP command -output READA; // Decoded READA command -output WRITEA; // Decoded WRITEA command -output REFRESH; // Decoded REFRESH command -output PRECHARGE; // Decoded PRECHARGE command -output LOAD_MODE; // Decoded LOAD_MODE command -output [`ASIZE-1:0] SADDR; // Registered version of ADDR -output REF_REQ; // Hidden refresh request -output INIT_REQ; // Hidden initial request -output CMD_ACK; // Command acknowledge - - - -reg NOP; -reg READA; -reg WRITEA; -reg REFRESH; -reg PRECHARGE; -reg LOAD_MODE; -reg [`ASIZE-1:0] SADDR; -reg REF_REQ; -reg INIT_REQ; -reg CMD_ACK; - -// Internal signals -reg [15:0] timer; -reg [15:0] init_timer; - - - -// Command decode and ADDR register -always @(posedge CLK or negedge RESET_N) -begin - if (RESET_N == 0) - begin - NOP <= 0; - READA <= 0; - WRITEA <= 0; - SADDR <= 0; - end - - else - begin - - SADDR <= ADDR; // register the address to keep proper - // alignment with the command - - if (CMD == 3'b000) // NOP command - NOP <= 1; - else - NOP <= 0; - - if (CMD == 3'b001) // READA command - READA <= 1; - else - READA <= 0; - - if (CMD == 3'b010) // WRITEA command - WRITEA <= 1; - else - WRITEA <= 0; - - end -end - - -// Generate CMD_ACK -always @(posedge CLK or negedge RESET_N) -begin - if (RESET_N == 0) - CMD_ACK <= 0; - else - if ((CM_ACK == 1) & (CMD_ACK == 0)) - CMD_ACK <= 1; - else - CMD_ACK <= 0; -end - - -// refresh timer -always @(posedge CLK or negedge RESET_N) begin - if (RESET_N == 0) - begin - timer <= 0; - REF_REQ <= 0; - end - else - begin - if (REF_ACK == 1) - begin - timer <= REF_PER; - REF_REQ <=0; - end - else if (INIT_REQ == 1) - begin - timer <= REF_PER+200; - REF_REQ <=0; - end - else - timer <= timer - 1'b1; - - if (timer==0) - REF_REQ <= 1; - - end -end - -// initial timer -always @(posedge CLK or negedge RESET_N) begin - if (RESET_N == 0) - begin - init_timer <= 0; - REFRESH <= 0; - PRECHARGE <= 0; - LOAD_MODE <= 0; - INIT_REQ <= 0; - end - else - begin - if (init_timer < (INIT_PER+201)) - init_timer <= init_timer+1; - - if (init_timer < INIT_PER) - begin - REFRESH <=0; - PRECHARGE <=0; - LOAD_MODE <=0; - INIT_REQ <=1; - end - else if(init_timer == (INIT_PER+20)) - begin - REFRESH <=0; - PRECHARGE <=1; - LOAD_MODE <=0; - INIT_REQ <=0; - end - else if( (init_timer == (INIT_PER+40)) || - (init_timer == (INIT_PER+60)) || - (init_timer == (INIT_PER+80)) || - (init_timer == (INIT_PER+100)) || - (init_timer == (INIT_PER+120)) || - (init_timer == (INIT_PER+140)) || - (init_timer == (INIT_PER+160)) || - (init_timer == (INIT_PER+180)) ) - begin - REFRESH <=1; - PRECHARGE <=0; - LOAD_MODE <=0; - INIT_REQ <=0; - end - else if(init_timer == (INIT_PER+200)) - begin - REFRESH <=0; - PRECHARGE <=0; - LOAD_MODE <=1; - INIT_REQ <=0; - end - else - begin - REFRESH <=0; - PRECHARGE <=0; - LOAD_MODE <=0; - INIT_REQ <=0; - end - end -end - -endmodule - diff --git a/de10_lite/risc_de10.htm b/de10_lite/risc_de10.htm deleted file mode 100644 index 5d6488d..0000000 --- a/de10_lite/risc_de10.htm +++ /dev/null @@ -1,753 +0,0 @@ - - -

DE10-Lite Kit Configuration

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Pin Assignments:

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Pin Assignment Table:

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- - - - - - - - - - - - - - - - - - - - - - - - -
CLOCK
NameLocationDirectionStandard
ADC_CLK_10N5input 3.3-V LVTTL
MAX10_CLK1_50P11input 3.3-V LVTTL
MAX10_CLK2_50N14input 3.3-V LVTTL
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- -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SDRAM
NameLocationDirectionStandard
DRAM_ADDR[0]U17output3.3-V LVTTL
DRAM_ADDR[1]W19output3.3-V LVTTL
DRAM_ADDR[2]V18output3.3-V LVTTL
DRAM_ADDR[3]U18output3.3-V LVTTL
DRAM_ADDR[4]U19output3.3-V LVTTL
DRAM_ADDR[5]T18output3.3-V LVTTL
DRAM_ADDR[6]T19output3.3-V LVTTL
DRAM_ADDR[7]R18output3.3-V LVTTL
DRAM_ADDR[8]P18output3.3-V LVTTL
DRAM_ADDR[9]P19output3.3-V LVTTL
DRAM_ADDR[10]T20output3.3-V LVTTL
DRAM_ADDR[11]P20output3.3-V LVTTL
DRAM_ADDR[12]R20output3.3-V LVTTL
DRAM_BA[0]T21output3.3-V LVTTL
DRAM_BA[1]T22output3.3-V LVTTL
DRAM_CAS_NU21output3.3-V LVTTL
DRAM_CKEN22output3.3-V LVTTL
DRAM_CLKL14output3.3-V LVTTL
DRAM_CS_NU20output3.3-V LVTTL
DRAM_DQ[0]Y21inout 3.3-V LVTTL
DRAM_DQ[1]Y20inout 3.3-V LVTTL
DRAM_DQ[2]AA22inout 3.3-V LVTTL
DRAM_DQ[3]AA21inout 3.3-V LVTTL
DRAM_DQ[4]Y22inout 3.3-V LVTTL
DRAM_DQ[5]W22inout 3.3-V LVTTL
DRAM_DQ[6]W20inout 3.3-V LVTTL
DRAM_DQ[7]V21inout 3.3-V LVTTL
DRAM_DQ[8]P21inout 3.3-V LVTTL
DRAM_DQ[9]J22inout 3.3-V LVTTL
DRAM_DQ[10]H21inout 3.3-V LVTTL
DRAM_DQ[11]H22inout 3.3-V LVTTL
DRAM_DQ[12]G22inout 3.3-V LVTTL
DRAM_DQ[13]G20inout 3.3-V LVTTL
DRAM_DQ[14]G19inout 3.3-V LVTTL
DRAM_DQ[15]F22inout 3.3-V LVTTL
DRAM_LDQMV22output3.3-V LVTTL
DRAM_RAS_NU22output3.3-V LVTTL
DRAM_UDQMJ21output3.3-V LVTTL
DRAM_WE_NV20output3.3-V LVTTL
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- -
-
- - - - - - - - - - - - - - - - - - -
KEY
NameLocationDirectionStandard
KEY[0]B8input 3.3 V Schmitt Trigger
KEY[1]A7input 3.3 V Schmitt Trigger
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- -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LED
NameLocationDirectionStandard
LEDR[0]A8output3.3-V LVTTL
LEDR[1]A9output3.3-V LVTTL
LEDR[2]A10output3.3-V LVTTL
LEDR[3]B10output3.3-V LVTTL
LEDR[4]D13output3.3-V LVTTL
LEDR[5]C13output3.3-V LVTTL
LEDR[6]E14output3.3-V LVTTL
LEDR[7]D14output3.3-V LVTTL
LEDR[8]A11output3.3-V LVTTL
LEDR[9]B11output3.3-V LVTTL
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- -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
VGA
NameLocationDirectionStandard
VGA_B[0]P1output3.3-V LVTTL
VGA_B[1]T1output3.3-V LVTTL
VGA_B[2]P4output3.3-V LVTTL
VGA_B[3]N2output3.3-V LVTTL
VGA_G[0]W1output3.3-V LVTTL
VGA_G[1]T2output3.3-V LVTTL
VGA_G[2]R2output3.3-V LVTTL
VGA_G[3]R1output3.3-V LVTTL
VGA_HSN3output3.3-V LVTTL
VGA_R[0]AA1output3.3-V LVTTL
VGA_R[1]V1output3.3-V LVTTL
VGA_R[2]Y2output3.3-V LVTTL
VGA_R[3]Y1output3.3-V LVTTL
VGA_VSN1output3.3-V LVTTL
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- -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
GPIO connect to GPIO Default
NameLocationDirectionStandardGPIO Pin Index
GPIO[0]V10inout 3.3-V LVTTL1
GPIO[1]W10inout 3.3-V LVTTL2
GPIO[2]V9inout 3.3-V LVTTL3
GPIO[3]W9inout 3.3-V LVTTL4
GPIO[4]V8inout 3.3-V LVTTL5
GPIO[5]W8inout 3.3-V LVTTL6
GPIO[6]V7inout 3.3-V LVTTL7
GPIO[7]W7inout 3.3-V LVTTL8
GPIO[8]W6inout 3.3-V LVTTL9
GPIO[9]V5inout 3.3-V LVTTL10
GPIO[10]W5inout 3.3-V LVTTL13
GPIO[11]AA15inout 3.3-V LVTTL14
GPIO[12]AA14inout 3.3-V LVTTL15
GPIO[13]W13inout 3.3-V LVTTL16
GPIO[14]W12inout 3.3-V LVTTL17
GPIO[15]AB13inout 3.3-V LVTTL18
GPIO[16]AB12inout 3.3-V LVTTL19
GPIO[17]Y11inout 3.3-V LVTTL20
GPIO[18]AB11inout 3.3-V LVTTL21
GPIO[19]W11inout 3.3-V LVTTL22
GPIO[20]AB10inout 3.3-V LVTTL23
GPIO[21]AA10inout 3.3-V LVTTL24
GPIO[22]AA9inout 3.3-V LVTTL25
GPIO[23]Y8inout 3.3-V LVTTL26
GPIO[24]AA8inout 3.3-V LVTTL27
GPIO[25]Y7inout 3.3-V LVTTL28
GPIO[26]AA7inout 3.3-V LVTTL31
GPIO[27]Y6inout 3.3-V LVTTL32
GPIO[28]AA6inout 3.3-V LVTTL33
GPIO[29]Y5inout 3.3-V LVTTL34
GPIO[30]AA5inout 3.3-V LVTTL35
GPIO[31]Y4inout 3.3-V LVTTL36
GPIO[32]AB3inout 3.3-V LVTTL37
GPIO[33]Y3inout 3.3-V LVTTL38
GPIO[34]AB2inout 3.3-V LVTTL39
GPIO[35]AA2inout 3.3-V LVTTL40
- - diff --git a/de10_lite/risc_de10.qpf b/de10_lite/risc_de10.qpf deleted file mode 100644 index 6e629c0..0000000 --- a/de10_lite/risc_de10.qpf +++ /dev/null @@ -1,6 +0,0 @@ -DATE = "12:27:18 August 03, 2024" -QUARTUS_VERSION = "16.0.0" - -# Revisions - -PROJECT_REVISION = "risc_de10" diff --git a/de10_lite/risc_de10.qsf b/de10_lite/risc_de10.qsf deleted file mode 100644 index d34559c..0000000 --- a/de10_lite/risc_de10.qsf +++ /dev/null @@ -1,251 +0,0 @@ -#============================================================ -# Build by Terasic System Builder -#============================================================ - -set_global_assignment -name FAMILY "MAX 10 FPGA" -set_global_assignment -name DEVICE 10M50DAF484C7G -set_global_assignment -name TOP_LEVEL_ENTITY "risc_de10" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.0.0" -set_global_assignment -name LAST_QUARTUS_VERSION "16.0.0" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:27:18 AUGUST 03,2024" -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 -set_global_assignment -name SDC_FILE risc_de10.SDC - -#============================================================ -# CLOCK -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 -set_location_assignment PIN_N5 -to ADC_CLK_10 -set_location_assignment PIN_P11 -to MAX10_CLK1_50 -set_location_assignment PIN_N14 -to MAX10_CLK2_50 - -#============================================================ -# SDRAM -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N -set_location_assignment PIN_U17 -to DRAM_ADDR[0] -set_location_assignment PIN_W19 -to DRAM_ADDR[1] -set_location_assignment PIN_V18 -to DRAM_ADDR[2] -set_location_assignment PIN_U18 -to DRAM_ADDR[3] -set_location_assignment PIN_U19 -to DRAM_ADDR[4] -set_location_assignment PIN_T18 -to DRAM_ADDR[5] -set_location_assignment PIN_T19 -to DRAM_ADDR[6] -set_location_assignment PIN_R18 -to DRAM_ADDR[7] -set_location_assignment PIN_P18 -to DRAM_ADDR[8] -set_location_assignment PIN_P19 -to DRAM_ADDR[9] -set_location_assignment PIN_T20 -to DRAM_ADDR[10] -set_location_assignment PIN_P20 -to DRAM_ADDR[11] -set_location_assignment PIN_R20 -to DRAM_ADDR[12] -set_location_assignment PIN_T21 -to DRAM_BA[0] -set_location_assignment PIN_T22 -to DRAM_BA[1] -set_location_assignment PIN_U21 -to DRAM_CAS_N -set_location_assignment PIN_N22 -to DRAM_CKE -set_location_assignment PIN_L14 -to DRAM_CLK -set_location_assignment PIN_U20 -to DRAM_CS_N -set_location_assignment PIN_Y21 -to DRAM_DQ[0] -set_location_assignment PIN_Y20 -to DRAM_DQ[1] -set_location_assignment PIN_AA22 -to DRAM_DQ[2] -set_location_assignment PIN_AA21 -to DRAM_DQ[3] -set_location_assignment PIN_Y22 -to DRAM_DQ[4] -set_location_assignment PIN_W22 -to DRAM_DQ[5] -set_location_assignment PIN_W20 -to DRAM_DQ[6] -set_location_assignment PIN_V21 -to DRAM_DQ[7] -set_location_assignment PIN_P21 -to DRAM_DQ[8] -set_location_assignment PIN_J22 -to DRAM_DQ[9] -set_location_assignment PIN_H21 -to DRAM_DQ[10] -set_location_assignment PIN_H22 -to DRAM_DQ[11] -set_location_assignment PIN_G22 -to DRAM_DQ[12] -set_location_assignment PIN_G20 -to DRAM_DQ[13] -set_location_assignment PIN_G19 -to DRAM_DQ[14] -set_location_assignment PIN_F22 -to DRAM_DQ[15] -set_location_assignment PIN_V22 -to DRAM_LDQM -set_location_assignment PIN_U22 -to DRAM_RAS_N -set_location_assignment PIN_J21 -to DRAM_UDQM -set_location_assignment PIN_V20 -to DRAM_WE_N - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[1] -set_location_assignment PIN_B8 -to KEY[0] -set_location_assignment PIN_A7 -to KEY[1] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] -set_location_assignment PIN_A8 -to LEDR[0] -set_location_assignment PIN_A9 -to LEDR[1] -set_location_assignment PIN_A10 -to LEDR[2] -set_location_assignment PIN_B10 -to LEDR[3] -set_location_assignment PIN_D13 -to LEDR[4] -set_location_assignment PIN_C13 -to LEDR[5] -set_location_assignment PIN_E14 -to LEDR[6] -set_location_assignment PIN_D14 -to LEDR[7] -set_location_assignment PIN_A11 -to LEDR[8] -set_location_assignment PIN_B11 -to LEDR[9] - -#============================================================ -# VGA -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS -set_location_assignment PIN_P1 -to VGA_B[0] -set_location_assignment PIN_T1 -to VGA_B[1] -set_location_assignment PIN_P4 -to VGA_B[2] -set_location_assignment PIN_N2 -to VGA_B[3] -set_location_assignment PIN_W1 -to VGA_G[0] -set_location_assignment PIN_T2 -to VGA_G[1] -set_location_assignment PIN_R2 -to VGA_G[2] -set_location_assignment PIN_R1 -to VGA_G[3] -set_location_assignment PIN_N3 -to VGA_HS -set_location_assignment PIN_AA1 -to VGA_R[0] -set_location_assignment PIN_V1 -to VGA_R[1] -set_location_assignment PIN_Y2 -to VGA_R[2] -set_location_assignment PIN_Y1 -to VGA_R[3] -set_location_assignment PIN_N1 -to VGA_VS - -#============================================================ -# GPIO, GPIO connect to GPIO Default -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] -set_location_assignment PIN_V10 -to GPIO[0] -set_location_assignment PIN_W10 -to GPIO[1] -set_location_assignment PIN_V9 -to GPIO[2] -set_location_assignment PIN_W9 -to GPIO[3] -set_location_assignment PIN_V8 -to GPIO[4] -set_location_assignment PIN_W8 -to GPIO[5] -set_location_assignment PIN_V7 -to GPIO[6] -set_location_assignment PIN_W7 -to GPIO[7] -set_location_assignment PIN_W6 -to GPIO[8] -set_location_assignment PIN_V5 -to GPIO[9] -set_location_assignment PIN_W5 -to GPIO[10] -set_location_assignment PIN_AA15 -to GPIO[11] -set_location_assignment PIN_AA14 -to GPIO[12] -set_location_assignment PIN_W13 -to GPIO[13] -set_location_assignment PIN_W12 -to GPIO[14] -set_location_assignment PIN_AB13 -to GPIO[15] -set_location_assignment PIN_AB12 -to GPIO[16] -set_location_assignment PIN_Y11 -to GPIO[17] -set_location_assignment PIN_AB11 -to GPIO[18] -set_location_assignment PIN_W11 -to GPIO[19] -set_location_assignment PIN_AB10 -to GPIO[20] -set_location_assignment PIN_AA10 -to GPIO[21] -set_location_assignment PIN_AA9 -to GPIO[22] -set_location_assignment PIN_Y8 -to GPIO[23] -set_location_assignment PIN_AA8 -to GPIO[24] -set_location_assignment PIN_Y7 -to GPIO[25] -set_location_assignment PIN_AA7 -to GPIO[26] -set_location_assignment PIN_Y6 -to GPIO[27] -set_location_assignment PIN_AA6 -to GPIO[28] -set_location_assignment PIN_Y5 -to GPIO[29] -set_location_assignment PIN_AA5 -to GPIO[30] -set_location_assignment PIN_Y4 -to GPIO[31] -set_location_assignment PIN_AB3 -to GPIO[32] -set_location_assignment PIN_Y3 -to GPIO[33] -set_location_assignment PIN_AB2 -to GPIO[34] -set_location_assignment PIN_AA2 -to GPIO[35] - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - diff --git a/de10_lite/risc_de10.sdc b/de10_lite/risc_de10.sdc deleted file mode 100644 index 7267c16..0000000 --- a/de10_lite/risc_de10.sdc +++ /dev/null @@ -1,86 +0,0 @@ -#************************************************************** -# This .sdc file is created by Terasic Tool. -# Users are recommended to modify this file to match users logic. -#************************************************************** - -#************************************************************** -# Create Clock -#************************************************************** -create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] -create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] -create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] - -#************************************************************** -# Create Generated Clock -#************************************************************** -derive_pll_clocks - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** -derive_clock_uncertainty - - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -#************************************************************** - - - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - - - -#************************************************************** -# Set Load -#************************************************************** - - - diff --git a/de10_lite/risc_de10.v b/de10_lite/risc_de10.v deleted file mode 100644 index 9404acb..0000000 --- a/de10_lite/risc_de10.v +++ /dev/null @@ -1,111 +0,0 @@ - -//======================================================= -// This code is generated by Terasic System Builder -//======================================================= - -module risc_de10( - - //////////// CLOCK ////////// - input ADC_CLK_10, - input MAX10_CLK1_50, - input MAX10_CLK2_50, - - //////////// SDRAM ////////// - output [12:0] DRAM_ADDR, - output [1:0] DRAM_BA, - output DRAM_CAS_N, - output DRAM_CKE, - output DRAM_CLK, - output DRAM_CS_N, - inout [15:0] DRAM_DQ, - output DRAM_LDQM, - output DRAM_RAS_N, - output DRAM_UDQM, - output DRAM_WE_N, - - //////////// KEY ////////// - input [1:0] KEY, - - //////////// LED ////////// - output [9:0] LEDR, - - //////////// VGA ////////// - output [3:0] VGA_B, - output [3:0] VGA_G, - output VGA_HS, - output [3:0] VGA_R, - output VGA_VS, - - //////////// GPIO, GPIO connect to GPIO Default ////////// - inout [35:0] GPIO -); - - - -//======================================================= -// REG/WIRE declarations -//======================================================= - wire rst; - // Data from data main memory - wire [31:0] dmem_data_out; - // Data going into data main memory - wire [31:0] dmem_data_in; - // Address for the data main memory - wire [15:0] dmem_addr; - // Write flag for data main memory - wire dmem_wr; - // Ready to read status for instruction main memory - wire dmem_ready; - // Data from instruction main memory - wire [31:0] imem_data_out; - // Data going into instruction main memory - wire [31:0] imem_data_in; - // Address for the instruction main memory - wire [15:0] imem_addr; - // Write flag for instruction main memory - wire imem_wr; - // Ready to read status for instruction main memory - wire imem_ready; - - - -//======================================================= -// Structural coding -//======================================================= - assign rst = KEY[0] | KEY[1] - - proc cpu (.dmem_data_out(dmem_data_out), .dmem_data_in(dmem_data_in), .dmem_addr(dmem_addr), .dmem_wr(dmem_wr), - .dmem_ready(dmem_ready), .imem_data_out(imem_data_out), .imem_data_in(imem_data_in), - .imem_addr(imem_addr), .imem_wr(imem_wr), .imem_ready(imem_ready), .clk(MAX10_CLK1_50), .rst(rst)); - - Sdram_Control u1 ( // HOST Side - .REF_CLK(MAX10_CLK1_50), - .RESET_N(rst), - // FIFO Write Side - .WR_DATA(writedata), - .WR(write), - .WR_ADDR(0), - .WR_MAX_ADDR(25'h1ffffff), // - .WR_LENGTH(9'h80), - .WR_LOAD(!test_global_reset_n ), - .WR_CLK(clk_test), - // FIFO Read Side - .RD_DATA(readdata), - .RD(read), - .RD_ADDR(0), // Read odd field and bypess blanking - .RD_MAX_ADDR(25'h1ffffff), - .RD_LENGTH(9'h80), - .RD_LOAD(!test_global_reset_n ), - .RD_CLK(clk_test), - // SDRAM Side - .SA(DRAM_ADDR), - .BA(DRAM_BA), - .CS_N(DRAM_CS_N), - .CKE(DRAM_CKE), - .RAS_N(DRAM_RAS_N), - .CAS_N(DRAM_CAS_N), - .WE_N(DRAM_WE_N), - .DQ(DRAM_DQ), - .DQM({DRAM_UDQM,DRAM_LDQM}), - .SDR_CLK(DRAM_CLK) ); -endmodule diff --git a/de10_lite/risc_de10_assignment_defaults.qdf b/de10_lite/risc_de10_assignment_defaults.qdf deleted file mode 100644 index 1d5aa27..0000000 --- a/de10_lite/risc_de10_assignment_defaults.qdf +++ /dev/null @@ -1,806 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2024 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition -# Date created = 13:04:50 August 03, 2024 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus Prime software and is used -# to preserve global assignments across Quartus Prime versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off -set_global_assignment -name IP_COMPONENT_INTERNAL Off -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -family "Arria V" -set_global_assignment -name REVISION_TYPE Base -family "Stratix V" -set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" -set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name DO_COMBINED_ANALYSIS Off -set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off -set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off -set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off -set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off -set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On -set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" -set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" -set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" -set_global_assignment -name OPTIMIZATION_MODE Balanced -set_global_assignment -name ALLOW_REGISTER_MERGING On -set_global_assignment -name ALLOW_REGISTER_DUPLICATION On -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" -set_global_assignment -name MUX_RESTRUCTURE Auto -set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off -set_global_assignment -name ENABLE_IP_DEBUG Off -set_global_assignment -name SAVE_DISK_SPACE On -set_global_assignment -name OCP_HW_EVAL -value OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE Any -set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name TRUE_WYSIWYG_FLOW Off -set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off -set_global_assignment -name STATE_MACHINE_PROCESSING Auto -set_global_assignment -name SAFE_STATE_MACHINE Off -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On -set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off -set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 -set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 -set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On -set_global_assignment -name PARALLEL_SYNTHESIS On -set_global_assignment -name DSP_BLOCK_BALANCING Auto -set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" -set_global_assignment -name NOT_GATE_PUSH_BACK On -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On -set_global_assignment -name IGNORE_CARRY_BUFFERS Off -set_global_assignment -name IGNORE_CASCADE_BUFFERS Off -set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_LCELL_BUFFERS Off -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO -set_global_assignment -name IGNORE_SOFT_BUFFERS On -set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off -set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off -set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On -set_global_assignment -name AUTO_GLOBAL_OE_MAX On -set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off -set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 -set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On -set_global_assignment -name PRPOF_ID Off -set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off -set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On -set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name PHYSICAL_SYNTHESIS Off -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" -set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" -set_global_assignment -name USE_CONF_DONE AUTO -set_global_assignment -name USE_PWRMGT_SCL AUTO -set_global_assignment -name USE_PWRMGT_SDA AUTO -set_global_assignment -name USE_PWRMGT_ALERT AUTO -set_global_assignment -name USE_INIT_DONE AUTO -set_global_assignment -name USE_CVP_CONFDONE AUTO -set_global_assignment -name USE_SEU_ERROR AUTO -set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On -set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name ENABLE_CONFIGURATION_PINS On -set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off -set_global_assignment -name ENABLE_BOOT_SEL_PIN On -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF -set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto -set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto -set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name RESERVE_PR_PINS Off -set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" -set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 -set_global_assignment -name SEU_FIT_REPORT Off -set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" -set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off -set_global_assignment -name POR_SCHEME "Instant ON" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP On -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On -set_global_assignment -name POF_VERIFY_PROTECT Off -set_global_assignment -name ENABLE_SPI_MODE_CHECK Off -set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On -set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 -set_global_assignment -name GENERATE_PMSF_FILES On -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name 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-set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name HPS_EARLY_IO_RELEASE Off -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off 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index fb01382..0000000 --- a/decode.v +++ /dev/null @@ -1,130 +0,0 @@ -`timescale 1us/100ns - -`include "decode_logic.v" -`include "latch.v" - -module decode_register_select(a0, a1, a2, a2_hazard, imm_to_reg, imm_to_addr, func, en_jmp, en_uncond_jmp, en_rel_reg_jmp, - en_mem_wr, ld_code, alu_data1, alu_data2, data_to_mem, en_reg_wr, dmem_addr_bus_use, - instr, d0, d1, stall, squash, clk, rst); - - // Register identifiers for computation - output wire [4:0] a0; - output wire [4:0] a1; - output wire [4:0] a2; - output wire [4:0] a2_hazard; - // Leaving decode stage, immediate values (if there is one) - output wire [31:0] imm_to_reg; - output wire [31:0] imm_to_addr; - // Leaving decode stage, function value (if there is one) - output wire [9:0] func; - // Leaving decode stage, enables if a jump can be taken - output wire en_jmp; - // Leaving decode stage, enables unconditional jumps - output wire en_uncond_jmp; - // Leaving decode stage, enables unconditional jump relative to value in a register - output wire en_rel_reg_jmp; - // Leaving decode stage, enables a write to memory - output wire en_mem_wr; - // Leaving decode stage, value that determines which value is put on the register write bus - output wire [2:0] ld_code; - // Leaving decode stage, output data from register file - output wire [31:0] alu_data1; - output wire [31:0] alu_data2; - // Leaving decode stage, data that is going to be written to memory - output wire [31:0] data_to_mem; - output wire en_reg_wr; - output wire dmem_addr_bus_use; - - // From fetch stage, the fetched instruction - input wire [31:0] instr; - input wire [31:0] d0; - input wire [31:0] d1; - input wire stall; - input wire squash; - input wire clk, rst; - - // Enables immediates for computation - wire en_imm; - wire input_en_reg_wr; - wire input_en_jmp; - wire input_en_uncond_jmp; - wire input_en_rel_reg_jmp; - wire [9:0] input_func; - reg [31:0] alu_input_data2; - wire [31:0] input_imm; - wire input_en_mem_wr; - wire [2:0] input_ld_code; - wire [4:0] input_a2; - - wire en_reg_wr_conn_latch1; - wire en_reg_wr_conn_latch2; - latch en_reg_wr_latch1 (.q(en_reg_wr_conn_latch1), .d(~squash & input_en_reg_wr), .stall(stall), .clk(clk), .rst(rst)); - latch en_reg_wr_latch2 (.q(en_reg_wr_conn_latch2), .d(en_reg_wr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - latch en_reg_wr_latch3 (.q(en_reg_wr), .d(en_reg_wr_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); - - latch en_jmp_latch (.q(en_jmp), .d(~squash & input_en_jmp), .stall(stall), .clk(clk), .rst(rst)); - - latch en_uncond_jmp_latch (.q(en_uncond_jmp), .d(~squash & input_en_uncond_jmp), .stall(stall), .clk(clk), .rst(rst)); - - latch en_rel_reg_jmp_latch (.q(en_rel_reg_jmp), .d(~squash &input_en_rel_reg_jmp), .stall(stall), .clk(clk), .rst(rst)); - - // Function code for ALU latch - latch function_code_latch [9:0] (.q(func), .d({10{~squash}} & input_func), .stall(stall), .clk(clk), .rst(rst)); - - // Data for ALU computation latch - latch data1_latch [31:0] (.q(alu_data1), .d({32{~squash}} & d0), .stall(stall), .clk(clk), .rst(rst)); - latch data2_latch [31:0] (.q(alu_data2), .d({32{~squash}} & alu_input_data2), .stall(stall), .clk(clk), .rst(rst)); - - // Memory data in latch - wire [31:0] data_to_mem_conn_latch1; - latch data_to_mem_latch1 [31:0] (.q(data_to_mem_conn_latch1), .d({32{~squash}} & d1), .stall(stall), .clk(clk), .rst(rst)); - latch data_to_mem_latch2 [31:0] (.q(data_to_mem), .d(data_to_mem_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - - // Immediate latch - wire [31:0] imm_conn_latch_conn; - latch immediate_latch1 [31:0] (.q(imm_to_addr), .d({32{~squash}} & input_imm), .stall(stall), .clk(clk), .rst(rst)); - latch immediate_latch2 [31:0] (.q(imm_conn_latch_conn), .d(imm_to_addr), .stall(stall), .clk(clk), .rst(rst)); - latch immediate_latch3 [31:0] (.q(imm_to_reg), .d(imm_conn_latch_conn), .stall(stall), .clk(clk), .rst(rst)); - - // Enable memory write latch - wire en_mem_wr_conn_latch1; - latch en_mem_wr_latch1(.q(en_mem_wr_conn_latch1), .d(~squash & input_en_mem_wr), .stall(stall), .clk(clk), .rst(rst)); - latch en_mem_wr_latch2(.q(en_mem_wr), .d(en_mem_wr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - - // Load Code latch - wire [2:0] ld_code_conn_latch1; - wire [2:0] ld_code_conn_latch2; - latch ld_code_latch1 [2:0] (.q(ld_code_conn_latch1), .d({3{~squash}} & input_ld_code), .stall(stall), .clk(clk), .rst(rst)); - latch ld_code_latch2 [2:0] (.q(ld_code_conn_latch2), .d(ld_code_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - latch ld_code_latch3 [2:0] (.q(ld_code), .d(ld_code_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); - - // a2 latch to tell the register file at the correct time - wire [4:0] a2_conn_latch1; - wire [4:0] a2_conn_latch2; - latch a2_latch1 [4:0] (.q(a2_conn_latch1), .d({5{~squash}} & input_a2), .stall(stall), .clk(clk), .rst(rst)); - latch a2_latch2 [4:0] (.q(a2_conn_latch2), .d(a2_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - latch a2_latch3 [4:0] (.q(a2), .d(a2_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); - - wire input_dmem_addr_bus_use; - wire dmem_addr_bus_use_conn_latch1; - latch dmem_addr_bus_use_latch1(.q(dmem_addr_bus_use_conn_latch1), .d(~squash & input_dmem_addr_bus_use), .stall(stall), .clk(clk), .rst(rst)); - latch dmem_addr_bus_use_latch2(.q(dmem_addr_bus_use), .d(dmem_addr_bus_use_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - - // Decode Logic - decode_logic dec (.a0(a0), .a1(a1), .a2(input_a2), .imm(input_imm), .func(input_func), - .en_jmp(input_en_jmp), .en_uncond_jmp(input_en_uncond_jmp), - .en_imm(en_imm), .en_reg_wr(input_en_reg_wr), .en_mem_wr(input_en_mem_wr), - .en_rel_reg_jmp(input_en_rel_reg_jmp), .ld_code(input_ld_code), .dmem_addr_bus_use(input_dmem_addr_bus_use), - .instr(instr)); - - assign a2_hazard = {5{~squash}} & input_a2; - always @(*) begin - - // Determine which value to use for the second value in the ALU operation - if (en_imm) - alu_input_data2 <= input_imm; - else - alu_input_data2 <= d1; - end - -endmodule diff --git a/decode_logic.v b/decode_logic.v deleted file mode 100644 index 5c0597d..0000000 --- a/decode_logic.v +++ /dev/null @@ -1,185 +0,0 @@ - -module decode_logic(a0, a1, a2, imm, func, en_jmp, en_uncond_jmp, en_imm, en_reg_wr, en_mem_wr, en_rel_reg_jmp, ld_code, dmem_addr_bus_use, instr); - `include "proc_params.h" - - input [31:0] instr; - output reg [`REG_BITS-1:0] a0; - output reg [`REG_BITS-1:0] a1; - output reg [`REG_BITS-1:0] a2; - output reg [31:0] imm; - output reg [`FUNC1_BITS+`FUNC2_BITS-1:0] func; - output reg en_jmp; - output reg en_uncond_jmp; - output reg en_imm; - output reg en_reg_wr; - output reg en_mem_wr; - output reg en_rel_reg_jmp; - output reg [2:0] ld_code; - output reg dmem_addr_bus_use; - - reg [2:0] imm_pos; - reg en_alu_str_func; - - reg [31:0] fu_imm; - reg [31:0] fi_imm; - reg [31:0] fs_imm; - reg [31:0] fb_imm; - reg [31:0] fj_imm; - - assign a0 = instr[`OPCODE_SIZE + 2*`REG_BITS + `FUNC1_BITS - 1:`OPCODE_SIZE + `REG_BITS + `FUNC1_BITS]; - assign a1 = instr[`OPCODE_SIZE + 3*`REG_BITS + `FUNC1_BITS - 1:`OPCODE_SIZE + 2*`REG_BITS + `FUNC1_BITS]; - assign a2 = instr[`OPCODE_SIZE + `REG_BITS - 1:`OPCODE_SIZE]; - assign func = {`FUNC1_BITS+`FUNC2_BITS{~en_alu_str_func}} & {instr[`OPCODE_SIZE + 3*`REG_BITS + `FUNC1_BITS + `FUNC2_BITS - 1:`OPCODE_SIZE + 3*`REG_BITS + `FUNC1_BITS], instr[`OPCODE_SIZE + `REG_BITS + `FUNC1_BITS - 1:`OPCODE_SIZE + `REG_BITS]}; - - assign fu_imm = {instr[31:12], {12{instr[31]}}}; - assign fi_imm = {{20{instr[31]}}, instr[31:20]}; - assign fs_imm = {{20{instr[31]}}, instr[31:25], instr[11:7]}; - assign fb_imm = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; - assign fj_imm = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; - - always @ (*) begin - case({instr[`OPCODE_SIZE-1:0]}) - `LOAD_UPPER_IMM: begin - imm_pos = `FORMAT_U; - ld_code = `IMM_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b0; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - `ADD_UPPER_IMM_PC: begin - imm_pos = `FORMAT_U; - ld_code = `PC_PIMM_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_imm = 1'b0; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - `JUMP_AND_LINK: begin - imm_pos = `FORMAT_J; - ld_code = `PC_LD; - en_jmp = 1'b1; - en_uncond_jmp = 1'b1; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b1; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - `JUMP_AND_LINK_REG: begin - imm_pos = `FORMAT_I; - ld_code = `PC_LD; - en_jmp = 1'b1; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b1; - en_imm = 1'b1; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - `LOAD_OP: begin - imm_pos = `FORMAT_I; - ld_code = `MEM_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b1; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b1; - dmem_addr_bus_use = 1'b1; - end - `STORE_OP: begin - imm_pos = `FORMAT_S; - ld_code = `NO_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b1; - en_reg_wr = 1'b0; - en_mem_wr = 1'b1; - en_alu_str_func = 1'b1; - dmem_addr_bus_use = 1'b1; - end - `BRANCH_OP: begin - imm_pos = `FORMAT_B; - ld_code = `NO_LD; - en_jmp = 1'b1; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b0; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - `IMM_ALU_OP: begin - imm_pos = `FORMAT_I; - ld_code = `ALU_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b1; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - `REG_ALU_OP: begin - imm_pos = `NO_IMM; - ld_code = `ALU_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b0; - en_reg_wr = 1'b1; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - default: begin - imm_pos = `NO_IMM; - ld_code = `NO_LD; - en_jmp = 1'b0; - en_uncond_jmp = 1'b0; - en_rel_reg_jmp = 1'b0; - en_imm = 1'b0; - en_reg_wr = 1'b0; - en_mem_wr = 1'b0; - en_alu_str_func = 1'b0; - dmem_addr_bus_use = 1'b0; - end - endcase - - case({imm_pos}) - `FORMAT_U: begin - imm = fu_imm; - end - `FORMAT_I: begin - imm = fi_imm; - end - `FORMAT_S: begin - imm = fs_imm; - end - `FORMAT_B: begin - imm = fb_imm; - end - `FORMAT_J: begin - imm = fj_imm; - end - default: begin - imm = fu_imm; - end - endcase - end - -endmodule \ No newline at end of file diff --git a/fetch.v b/fetch.v deleted file mode 100644 index 355c075..0000000 --- a/fetch.v +++ /dev/null @@ -1,95 +0,0 @@ -`timescale 1us/100ns - -`include "stallmem.v" -`include "latch.v" - -module fetch (curr_addr, instr_out, curr_addr_step_out, curr_addr_addval_out, - instr_in, jump_taken, alu_bits, en_uncond_jmp, en_rel_reg_jmp, - en_branch, en_jmp, imm, stall, imem_stall, clk, rst); - - // Current Address - output wire [31:0] curr_addr; - // Instruction coming out of fetch stage - output wire [31:0] instr_out; - // Leaving Fetch Stage, Current address plus four bytes - output wire [31:0] curr_addr_step_out; - // Leaving Fetch Stage, Current address plus relative jump - output wire [31:0] curr_addr_addval_out; - - - // Instruction coming directly from memory - input wire [31:0] instr_in; - // From Main Processor, signal that tells whether a jump will be taken or not - input wire jump_taken; - // From Execute, the address from the ALU - input wire [31:0] alu_bits; - // From Decode, signal that enables jumps - input wire en_jmp; - // From Decode, signal that enables unconditional jumps - input wire en_uncond_jmp; - // From Decode, signal that enables jumps using a register and an immediate - input wire en_rel_reg_jmp; - // From Decode, signal that enables a branch to be taken - input wire en_branch; - // From Decode, the immediate value from the instruction - input wire [31:0] imm; - // Signal that informs whether a stall is occuring from the data cache - input wire stall; - // Signal designating if the instruction memory was successfully read from - input wire imem_stall; - // Clock and Reset - input wire clk, rst; - - - // Current Address After 4 Byte Step - wire [31:0] curr_addr_step; - // Current Address plus relative jump - wire [31:0] curr_addr_addval; - - - // Next Address to be used put onto the cache - reg [31:0] next_addr; - - // Program Counter - latch pc [31:0] (.q(curr_addr), .d(next_addr), .stall(stall | imem_stall), .clk(clk), .rst(rst)); - - // Instruction Latch - latch instr_latch [31:0] (.q(instr_out), .d(instr_in), .stall(stall), .clk(clk), .rst(rst)); - - // Latch for the current address plus four bytes - wire [31:0] curr_addr_step_conn_latch1; - wire [31:0] curr_addr_step_conn_latch2; - wire [31:0] curr_addr_step_conn_latch3; - latch curr_addr_step_latch1 [31:0] (.q(curr_addr_step_conn_latch1), .d(curr_addr_step), .stall(stall), .clk(clk), .rst(rst)); - latch curr_addr_step_latch2 [31:0] (.q(curr_addr_step_conn_latch2), .d(curr_addr_step_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - latch curr_addr_step_latch3 [31:0] (.q(curr_addr_step_conn_latch3), .d(curr_addr_step_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); - latch curr_addr_step_latch4 [31:0] (.q(curr_addr_step_out), .d(curr_addr_step_conn_latch3), .stall(stall), .clk(clk), .rst(rst)); - - // Latch for the current address plus the additional value - wire [31:0] curr_addr_addval_conn_latch1; - latch curr_addr_addval_latch1 [31:0] (.q(curr_addr_addval_conn_latch1), .d(curr_addr_addval), .stall(stall), .clk(clk), .rst(rst)); - latch curr_addr_addval_latch2 [31:0] (.q(curr_addr_addval_out), .d(curr_addr_addval_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - - // Latch for current address - wire [31:0] curr_addr_conn_latch1; - wire [31:0] curr_addr_out; - latch curr_addr_latch1 [31:0] (.q(curr_addr_conn_latch1), .d(curr_addr), .stall(stall), .clk(clk), .rst(rst)); - latch curr_addr_latch2 [31:0] (.q(curr_addr_out), .d(curr_addr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); - - assign curr_addr_step = curr_addr + 4; - assign curr_addr_addval = curr_addr_out + imm; - - always @(*) begin - // Determine if a jump is to be taken - if (en_jmp & en_rel_reg_jmp) begin - next_addr <= alu_bits; - end - else if (en_jmp & (en_uncond_jmp | en_branch)) begin - next_addr <= curr_addr_addval; - end - else begin - next_addr <= curr_addr_step; - end - - end -endmodule diff --git a/latch.v b/latch.v deleted file mode 100644 index c1f887c..0000000 --- a/latch.v +++ /dev/null @@ -1,19 +0,0 @@ -`timescale 1us/100ns - -module latch (q, d, stall, clk, rst); - - output q; - input d; - input stall; - input clk; - input rst; - - reg state; - - assign #(1) q = state; - - always @(posedge clk) begin - state = rst? 0 : (stall ? q : d); - end - -endmodule diff --git a/left_barrel_shifter.v b/left_barrel_shifter.v deleted file mode 100644 index 47e04b3..0000000 --- a/left_barrel_shifter.v +++ /dev/null @@ -1,114 +0,0 @@ - -`timescale 1us/100ns - -module left_barrel_shifter(in_bits, out_bits, shift_len); - - input [31:0] in_bits; - input [4:0] shift_len; - output reg [31:0] out_bits; - - always @ (*) - case({shift_len}) - 5'd0: begin - out_bits = in_bits; - end - 5'd1: begin - out_bits[31:0] = {in_bits[30:0], 1'b0}; - end - 5'd2: begin - out_bits[31:0] = {in_bits[29:0], 2'b0}; - end - 5'd3: begin - out_bits[31:0] = {in_bits[28:0], 3'b0}; - end - 5'd4: begin - out_bits[31:0] = {in_bits[27:0], 4'b0}; - end - 5'd5: begin - out_bits[31:0] = {in_bits[26:0], 5'b0}; - end - 5'd6: begin - out_bits[31:0] = {in_bits[25:0], 6'b0}; - end - 5'd7: begin - out_bits[31:0] = {in_bits[24:0], 7'b0}; - end - 5'd8: begin - out_bits[31:0] = {in_bits[23:0], 8'b0}; - end - 5'd9: begin - out_bits[31:0] = {in_bits[22:0], 9'b0}; - end - 5'd10: begin - out_bits[31:0] = {in_bits[21:0], 10'b0}; - end - 5'd11: begin - out_bits[31:0] = {in_bits[20:0], 11'b0}; - end - 5'd12: begin - out_bits[31:0] = {in_bits[19:0], 12'b0}; - end - 5'd13: begin - out_bits[31:0] = {in_bits[18:0], 13'b0}; - end - 5'd14: begin - out_bits[31:0] = {in_bits[17:0], 14'b0}; - end - 5'd15: begin - out_bits[31:0] = {in_bits[16:0], 15'b0}; - end - 5'd16: begin - out_bits[31:0] = {in_bits[15:0], 16'b0}; - end - 5'd17: begin - out_bits[31:0] = {in_bits[14:0], 17'b0}; - end - 5'd18: begin - out_bits[31:0] = {in_bits[13:0], 18'b0}; - end - 5'd19: begin - out_bits[31:0] = {in_bits[12:0], 19'b0}; - end - 5'd20: begin - out_bits[31:0] = {in_bits[11:0], 20'b0}; - end - 5'd21: begin - out_bits[31:0] = {in_bits[10:0], 21'b0}; - end - 5'd22: begin - out_bits[31:0] = {in_bits[9:0], 22'b0}; - end - 5'd23: begin - out_bits[31:0] = {in_bits[8:0], 23'b0}; - end - 5'd24: begin - out_bits[31:0] = {in_bits[7:0], 24'b0}; - end - 5'd25: begin - out_bits[31:0] = {in_bits[6:0], 25'b0}; - end - 5'd26: begin - out_bits[31:0] = {in_bits[5:0], 26'b0}; - end - 5'd27: begin - out_bits[31:0] = {in_bits[4:0], 27'b0}; - end - 5'd28: begin - out_bits[31:0] = {in_bits[3:0], 28'b0}; - end - 5'd29: begin - out_bits[31:0] = {in_bits[2:0], 29'b0}; - end - 5'd30: begin - out_bits[31:0] = {in_bits[1:0], 30'b0}; - end - 5'd31: begin - out_bits[31:0] = {in_bits[0], 31'b0}; - end - default: begin - out_bits[31:0] = {32'b0}; - end - endcase - -endmodule - \ No newline at end of file diff --git a/package.json b/package.json new file mode 100644 index 0000000..10e5f1f --- /dev/null +++ b/package.json @@ -0,0 +1,43 @@ +{ + "name": "@/riscv-processor", + "version": "0.1.0", + "description": "A source xPack with ", + "main": "", + "scripts": { + "test": "echo \"Error: no test specified\" && exit 1" + }, + "repository": { + "type": "git", + "url": "https://github.com//riscv-processor.git" + }, + "homepage": "https://github.com//riscv-processor/", + "bugs": { + "url": "https://github.com//riscv-processor/issues/" + }, + "keywords": [ + "xpack" + ], + "author": { + "name": "", + "email": "", + "url": "" + }, + "license": "MIT", + "config": {}, + "dependencies": {}, + "devDependencies": {}, + "xpack": { + "minimumXpmRequired": "0.20.5", + "dependencies": {}, + "devDependencies": { + "@xpack-dev-tools/riscv-none-elf-gcc": { + "specifier": "14.2.0-3.1", + "local": "link", + "platforms": "all" + } + }, + "properties": {}, + "actions": {}, + "buildConfigurations": {} + } +} diff --git a/proc.v b/proc.v deleted file mode 100644 index 3416224..0000000 --- a/proc.v +++ /dev/null @@ -1,139 +0,0 @@ -`timescale 1us/100ns - -module proc(data_out, data_in, addr, mem_wr, mem_ready, - clk, rst); - - `include "proc_params.h" - - // Data from data main memory - input wire [31:0] data_out; - // Data going into data main memory - output wire [31:0] data_in; - // Address for the data main memory - output wire [31:0] addr; - // Write flag for data main memory - output wire mem_wr; - input wire mem_ready; - input wire clk, rst; - - // Intruction - wire [31:0] instr; - // Output from ALU operation - wire [31:0] alu_output_data_in; - // Data to be written to a register - reg [31:0] data_to_reg; - - // Register Numbers - wire [4:0] a0; - wire [4:0] a1; - wire [4:0] a2; - wire [4:0] a2_hazard; - // Output data from register file - wire [31:0] d0; - wire [31:0] d1; - // Data to be used in ALU comutation - wire [31:0] alu_data1; - wire [31:0] alu_data2; - // Immediate Value (if there is one) - wire [31:0] imm_to_reg; - wire [31:0] imm_to_addr; - // Function Value (if there is one) - wire [9:0] func; - - // Stall from data memory - wire dmem_stall; - // Stall from instruction memory - wire imem_stall; - // Enables if a jump can be taken - wire en_jmp; - // Enables unconditional jumps - wire en_uncond_jmp; - // Enables unconditional jump relative to value in a register - wire en_rel_reg_jmp; - // Enables if a branch is going to be be taken or not - wire en_branch; - // Enables a write to the register - wire en_reg_wr; - // Value that determines which value is put on the register write bus - wire [2:0] ld_code; - - wire [31:0] curr_addr_step; - wire [31:0] curr_addr_addval; - wire stall; - wire jump_taken; - wire control_hazard; - wire data_hazard; - - wire [31:0] imem_data_out; - wire [31:0] imem_addr; - wire imem_ready; - wire [31:0] dmem_data_out; - wire [31:0] dmem_addr; - wire dmem_ready; - wire dmem_use; - - data_addr_bus_controller dabc (.imem_data_out(imem_data_out), .dmem_data_out(dmem_data_out), .data_out(data_out), - .imem_ready(imem_ready), .dmem_ready(dmem_ready), .mem_ready(mem_ready), - .imem_addr(imem_addr), .dmem_addr(dmem_addr), .mem_addr(addr), .dmem_use(dmem_use)); - - wire [31:0] alu_output_data_as_addr; - wire [31:0] alu_output_data_to_reg; - latch alu_output_data_latch1 [31:0] (.q(alu_output_data_as_addr), .d(alu_output_data_in), .stall(stall), .clk(clk), .rst(rst)); - latch alu_output_data_latch2 [31:0] (.q(alu_output_data_to_reg), .d(alu_output_data_as_addr), .stall(stall), .clk(clk), .rst(rst)); - - wire [31:0] dmem_data_out_to_reg; - latch dmem_data_out_latch [31:0] (.q(dmem_data_out_to_reg), .d(dmem_data_out), .stall(stall), .clk(clk), .rst(rst)); - - hazards_controller hazards(.control_hazard(control_hazard), .data_hazard(data_hazard), .stall(stall), .dmem_stall(dmem_stall), - .imem_stall(imem_stall), .jump_taken(jump_taken), .dmem_ready(dmem_ready), - .imem_ready(imem_ready), .dmem_use(dmem_use), .a0(a0), .a1(a1), .a2(a2_hazard), .clk(clk), .rst(rst)); - assign jump_taken = (en_jmp) & (en_rel_reg_jmp | en_uncond_jmp | en_branch); - - // Fetch Stage - fetch fet (.curr_addr(imem_addr), .instr_out(instr), .curr_addr_step_out(curr_addr_step), .curr_addr_addval_out(curr_addr_addval), - .instr_in(imem_data_out), .jump_taken(jump_taken), .alu_bits(alu_output_data_in), .en_uncond_jmp(en_uncond_jmp), - .en_rel_reg_jmp(en_rel_reg_jmp), .en_branch(en_branch), .en_jmp(en_jmp), .imm(imm_to_addr), .stall(stall | data_hazard), - .imem_stall(imem_stall), .clk(clk), .rst(rst)); - // Decode Stage - decode_register_select drs(.a0(a0), .a1(a1), .a2(a2), .a2_hazard(a2_hazard), .imm_to_reg(imm_to_reg), .imm_to_addr(imm_to_addr), - .func(func), .en_jmp(en_jmp), .en_uncond_jmp(en_uncond_jmp), .en_rel_reg_jmp(en_rel_reg_jmp), .en_mem_wr(mem_wr), - .ld_code(ld_code), .alu_data1(alu_data1), .alu_data2(alu_data2), .data_to_mem(data_in), .en_reg_wr(en_reg_wr), - .dmem_addr_bus_use(dmem_use), .instr(instr), .d0(d0), .d1(d1), .stall(stall), .squash(data_hazard | control_hazard), - .clk(clk), .rst(rst)); - - // ALU - alu a(.bits_a(alu_data1), .bits_b(alu_data2), .func(func), .out_bits(alu_output_data_in), .compare_val(en_branch)); - - // Register File - reg_file regs (.a0(a0), .a1(a1), .a2(a2), - .din(data_to_reg), .reg_wr(en_reg_wr), - .d0(d0), .d1(d1), .clk(clk), .rst(rst)); - - assign dmem_addr = alu_output_data_as_addr; - - always @(*) begin - - // Mux to Determine Register Write Back - case({ld_code}) - `ALU_LD: begin - data_to_reg <= alu_output_data_to_reg; - end - `MEM_LD: begin - data_to_reg <= dmem_data_out_to_reg; - end - `IMM_LD: begin - data_to_reg <= imm_to_reg; - end - `PC_LD: begin - data_to_reg <= curr_addr_step; - end - `PC_PIMM_LD: begin - data_to_reg <= curr_addr_addval; - end - default: begin - data_to_reg <= curr_addr_step; - end - endcase - end -endmodule - \ No newline at end of file diff --git a/right_barrel_shifter.v b/right_barrel_shifter.v deleted file mode 100644 index 7f1eac6..0000000 --- a/right_barrel_shifter.v +++ /dev/null @@ -1,118 +0,0 @@ -`timescale 1us/100ns - -module right_barrel_shifter(in_bits, out_bits, shift_len, arithmetic); - - input [31:0] in_bits; - input [4:0] shift_len; - input arithmetic; - output reg [31:0] out_bits; - - wire shift_bit; - - assign shift_bit = arithmetic & in_bits[31]; - - always @ (*) - case({shift_len}) - 5'd0: begin - out_bits = in_bits; - end - 5'd1: begin - out_bits[31:0] = {{1{shift_bit}}, in_bits[31:1]}; - end - 5'd2: begin - out_bits[31:0] = {{2{shift_bit}}, in_bits[31:2]}; - end - 5'd3: begin - out_bits[31:0] = {{3{shift_bit}}, in_bits[31:3]}; - end - 5'd4: begin - out_bits[31:0] = {{4{shift_bit}}, in_bits[31:4]}; - end - 5'd5: begin - out_bits[31:0] = {{5{shift_bit}}, in_bits[31:5]}; - end - 5'd6: begin - out_bits[31:0] = {{6{shift_bit}}, in_bits[31:6]}; - end - 5'd7: begin - out_bits[31:0] = {{7{shift_bit}}, in_bits[31:7]}; - end - 5'd8: begin - out_bits[31:0] = {{8{shift_bit}}, in_bits[31:8]}; - end - 5'd9: begin - out_bits[31:0] = {{9{shift_bit}}, in_bits[31:9]}; - end - 5'd10: begin - out_bits[31:0] = {{10{shift_bit}}, in_bits[31:10]}; - end - 5'd11: begin - out_bits[31:0] = {{11{shift_bit}}, in_bits[31:11]}; - end - 5'd12: begin - out_bits[31:0] = {{12{shift_bit}}, in_bits[31:12]}; - end - 5'd13: begin - out_bits[31:0] = {{13{shift_bit}}, in_bits[31:13]}; - end - 5'd14: begin - out_bits[31:0] = {{14{shift_bit}}, in_bits[31:14]}; - end - 5'd15: begin - out_bits[31:0] = {{15{shift_bit}}, in_bits[31:15]}; - end - 5'd16: begin - out_bits[31:0] = {{16{shift_bit}}, in_bits[31:16]}; - end - 5'd17: begin - out_bits[31:0] = {{17{shift_bit}}, in_bits[31:17]}; - end - 5'd18: begin - out_bits[31:0] = {{18{shift_bit}}, in_bits[31:18]}; - end - 5'd19: begin - out_bits[31:0] = {{19{shift_bit}}, in_bits[31:19]}; - end - 5'd20: begin - out_bits[31:0] = {{20{shift_bit}}, in_bits[31:20]}; - end - 5'd21: begin - out_bits[31:0] = {{21{shift_bit}}, in_bits[31:21]}; - end - 5'd22: begin - out_bits[31:0] = {{22{shift_bit}}, in_bits[31:22]}; - end - 5'd23: begin - out_bits[31:0] = {{23{shift_bit}}, in_bits[31:23]}; - end - 5'd24: begin - out_bits[31:0] = {{24{shift_bit}}, in_bits[31:24]}; - end - 5'd25: begin - out_bits[31:0] = {{25{shift_bit}}, in_bits[31:25]}; - end - 5'd26: begin - out_bits[31:0] = {{26{shift_bit}}, in_bits[31:26]}; - end - 5'd27: begin - out_bits[31:0] = {{27{shift_bit}}, in_bits[31:27]}; - end - 5'd28: begin - out_bits[31:0] = {{28{shift_bit}}, in_bits[31:28]}; - end - 5'd29: begin - out_bits[31:0] = {{29{shift_bit}}, in_bits[31:29]}; - end - 5'd30: begin - out_bits[31:0] = {{30{shift_bit}}, in_bits[31:30]}; - end - 5'd31: begin - out_bits[31:0] = {{31{shift_bit}}, in_bits[31]}; - end - default: begin - out_bits[31:0] = {{32{shift_bit}}}; - end - endcase - -endmodule - \ No newline at end of file diff --git a/setup.sh b/setup.sh new file mode 100755 index 0000000..bf0da38 --- /dev/null +++ b/setup.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +xpm init +xpm install @xpack-dev-tools/riscv-none-elf-gcc@14.2.0-3.1 --verbose + diff --git a/sim/memory2c.v b/sim/memory2c.v deleted file mode 100644 index 179c94b..0000000 --- a/sim/memory2c.v +++ /dev/null @@ -1,95 +0,0 @@ -/* $Author: karu $ */ -/* $LastChangedDate: 2009-03-04 23:09:45 -0600 (Wed, 04 Mar 2009) $ */ -/* $Rev: 45 $ */ -////////////////////////////////////// -// -// Memory -- single cycle version -// -// written for CS/ECE 552, Spring '07 -// Pratap Ramamurthy, 19 Mar 2006 -// -// This is a byte-addressable, -// 16-bit wide, 64K-byte memory. -// -// All reads happen combinationally with zero delay. -// All writes occur on rising clock edge. -// Concurrent read and write not allowed. -// -// On reset, memory loads from file "loadfile_all.img". -// (You may change the name of the file in -// the $readmemh statement below.) -// File format: -// @0 -// -// -// ...etc -// -// If input "createdump" is true on rising clock, -// contents of memory will be dumped to -// file "dumpfile", from location 0 up through -// the highest location modified by a write. -// -// -////////////////////////////////////// - -module memory2c (data_out, data_in, addr, enable, wr, createdump, clk, rst); - - output [31:0] data_out; - input [31:0] data_in; - input [15:0] addr; - input enable; - input wr; - input createdump; - input clk; - input rst; - - wire [31:0] data_out; - - reg [7:0] mem [0:65535]; - reg loaded; - reg [16:0] largest; - - integer mcd; - integer i; - - - // assign data_temp_0 = mem[addr]; - // assign data_temp_2 = mem[{addr+8'h1]; - assign data_out = (enable & (~wr))? {mem[addr+3],mem[addr+2],mem[addr+1],mem[addr]}: 0; - initial begin - loaded = 0; - largest = 0; - for (i = 0; i< 65536; i=i+1) begin - mem[i] = 8'd0; - end - end - - always @(posedge clk) begin - if (rst) begin - // first init to 0, then load loadfile_all.img - if (!loaded) begin - $readmemh("merge_sort_verilog.txt", mem); - loaded = 1; - end - end - else begin - if (enable & wr) begin - mem[addr+3] = data_in[31:24]; // The actual write - mem[addr+2] = data_in[23:16]; // The actual write - mem[addr+1] = data_in[15:8]; // The actual write - mem[addr+0] = data_in[7:0]; // The actual write - if ({1'b0, addr} > largest) largest = addr; // avoid negative numbers - end - if (createdump) begin - mcd = $fopen("dumpfile", "w"); - for (i=0; i<=largest+1; i=i+1) begin - $fdisplay(mcd,"%4h %2h", i, mem[i]); - end - $fclose(mcd); - end - end - end - - -endmodule // memory2c -// DUMMY LINE FOR REV CONTROL :0: diff --git a/sim/proc_tb.v b/sim/proc_tb.v deleted file mode 100644 index c0d8d50..0000000 --- a/sim/proc_tb.v +++ /dev/null @@ -1,52 +0,0 @@ - -`timescale 1us/100ns - -module proc_tb(); - reg clk; - reg rst; - - // Data from data main memory - wire [31:0] data_out; - // Data going into data main memory - wire [31:0] data_in; - // Address for the data main memory - wire [31:0] addr; - // Write flag for data main memory - wire mem_wr; - // Ready to read status for instruction main memory - wire mem_ready; - - // Constants - // Enable Caches - wire enable; - wire createdump; - wire err; - - // Instruction Memory - stallmem mem (.data_out(data_out), .ready(mem_ready), .data_in(data_in), .addr(addr), .enable(enable), - .wr(mem_wr), .createdump(createdump), .clk(clk), .rst(rst), .err(err)); - // Processor - proc cpu (.data_out(data_out), .data_in(data_in), .addr(addr), .mem_wr(mem_wr), .mem_ready(mem_ready), - .clk(clk), .rst(rst)); - - // Constants - assign enable = 1'b1; - assign createdump = 1'b1; - - always #5 clk = ~clk; - - initial begin - clk = 0; - rst = 0; - - // reset logic - #2; - rst = 1; - #10; - rst = 0; - - #50000; - $finish; - end - -endmodule \ No newline at end of file diff --git a/sim/src/sdram_model.v b/sim/src/sdram_model.v new file mode 100644 index 0000000..3dc8ece --- /dev/null +++ b/sim/src/sdram_model.v @@ -0,0 +1,125 @@ + +`define DATA_SIZE 16 +module sdram_model +( +// SDRAM MODEL INTERFACE +input in_CLK, +input in_CS, // CHIP SELECT +input in_write_en, +input in_CAS, //COLUMN ADRESS STROBE +input in_RAS, //ROW ADRESS STROBE +input[1:0] in_bank_select, // BANK SELECTION BITS +input[12:0] in_sdram_addr, +input dram_ldqm, +input dram_udqm, +inout reg [15:0] dq +// SDRAM MODEL INTERFACE END +); + + parameter DATA = `DATA_SIZE, + ROW = 16384, + COLUMN = 512; + + wire ACT, + READ_CAS, + WRITE_CAS, + NOP, + WRITE_READY; + + + reg [13:0]registered_row = 14'b0; + reg [8:0]registered_column = 9'b0; + reg [1:0]registered_bank_sel = 2'b0; + reg [1:0]nop_counter = 2'b0; + reg registered_write_cas = 1'b0, registered_read_cas = 1'b0; + + assign ACT = ~in_CS && ~in_RAS && in_CAS && in_write_en; + assign READ_CAS = ~in_CS && in_RAS && ~in_CAS && in_write_en; + assign WRITE_CAS = ~in_CS && in_RAS && ~in_CAS && ~in_write_en; + assign NOP = ~in_CS && in_RAS && in_CAS && in_write_en; + assign WRITE_READY = (nop_counter == 2 && NOP && registered_write_cas)? 1'b1: 1'b0; + reg [DATA-1 : 0] bank0 [0 : ROW-1][0 : COLUMN-1]; + reg [DATA-1 : 0] bank1 [0 : ROW-1][0 : COLUMN-1]; + reg [DATA-1 : 0] bank2 [0 : ROW-1][0 : COLUMN-1]; + reg [DATA-1 : 0] bank3 [0 : ROW-1][0 : COLUMN-1]; + + + wire [`DATA_SIZE-1:0] idata; + reg [`DATA_SIZE-1:0] odata; + assign idata = in_write_en ? `DATA_SIZE'b0 : dq; + assign dq = odata; + + localparam BANK0 = 2'b00, + BANK1 = 2'b01, + BANK2 = 2'b10, + BANK3 = 2'b11; + + always @(posedge in_CLK)begin + if(!in_CS)begin + if(ACT) begin + registered_row[13:0] <= in_sdram_addr[13:0]; + registered_bank_sel[1:0] <= in_bank_select[1:0]; + end + else if (READ_CAS || WRITE_CAS)begin + registered_column[8:0] <= in_sdram_addr[8:0]; + registered_bank_sel[1:0] <= in_bank_select[1:0]; + registered_write_cas <= WRITE_CAS; + end + + if(nop_counter == 3)begin + nop_counter <= 2'b0; + end + else if(NOP)begin + nop_counter <= nop_counter + 1; + end + end + end + + always @(*) begin + if(WRITE_READY)begin + + case(registered_bank_sel) + + BANK0:begin + bank0[registered_row][registered_column] = idata; + end + + BANK1:begin + bank1[registered_row][registered_column] = idata; + end + + BANK2:begin + bank2[registered_row][registered_column] = idata; + end + + BANK3:begin + bank3[registered_row][registered_column] = idata; + end + + endcase + end + else if(in_write_en)begin + + case(registered_bank_sel) + + BANK0:begin + odata = bank0[registered_row][registered_column]; + end + + BANK1:begin + odata = bank1[registered_row][registered_column]; + end + + BANK2:begin + odata = bank2[registered_row][registered_column]; + end + + BANK3:begin + odata = bank3[registered_row][registered_column]; + end + + endcase + end + end + +endmodule \ No newline at end of file diff --git a/sim/stallmem.v b/sim/src/stallmem.v similarity index 85% rename from sim/stallmem.v rename to sim/src/stallmem.v index d301cfe..8c69d14 100644 --- a/sim/stallmem.v +++ b/sim/src/stallmem.v @@ -45,7 +45,7 @@ module stallmem (data_out, ready, data_in, addr, enable, wr, createdump, clk, rs output [31:0] data_out; output ready; input [31:0] data_in; - input [15:0] addr; + input [13:0] addr; input enable; input wr; input createdump; @@ -55,7 +55,7 @@ module stallmem (data_out, ready, data_in, addr, enable, wr, createdump, clk, rs wire [31:0] data_out; - reg [7:0] mem [0:65535]; + reg [31:0] mem [0:16384]; reg loaded; reg [16:0] largest; reg [31:0] rand_pat; @@ -65,7 +65,7 @@ module stallmem (data_out, ready, data_in, addr, enable, wr, createdump, clk, rs assign ready = enable & rand_pat[0]; assign err = ready & addr[0]; //word aligned; odd address is invalid - assign data_out = (enable & (~wr))? {mem[addr+3],mem[addr+2],mem[addr+1],mem[addr]}: 0; + assign data_out = (enable & (~wr))? {mem[addr]}: 0; integer seed; initial begin @@ -78,7 +78,7 @@ module stallmem (data_out, ready, data_in, addr, enable, wr, createdump, clk, rs $display("rand_pat=%08x %32b", rand_pat, rand_pat); // initialize memories to 0 first for (i=0; i<=65535; i=i+1) begin - mem[i] = 8'd0; + mem[i] = 32'd0; end end @@ -86,16 +86,13 @@ module stallmem (data_out, ready, data_in, addr, enable, wr, createdump, clk, rs always @(posedge clk) begin if (rst) begin if (!loaded) begin - $readmemh("risc_test_verilog.txt", mem); + $readmemh("../../test_programs/blinky.hex", mem); loaded = 1; end end else begin if (ready & wr & ~err) begin - mem[addr+3] = data_in[31:24]; // The actual write - mem[addr+2] = data_in[23:16]; // The actual write - mem[addr+1] = data_in[15:8]; // The actual write - mem[addr+0] = data_in[7:0]; // The actual write + mem[addr] = data_in[31:24]; // The actual write if ({1'b0, addr} > largest) largest = addr; // avoid negative numbers end if (createdump) begin diff --git a/sim/proc_sim.mpf b/sim/testbenches/cache_controller_tb.mpf similarity index 72% rename from sim/proc_sim.mpf rename to sim/testbenches/cache_controller_tb.mpf index 191621c..e65012c 100644 --- a/sim/proc_sim.mpf +++ b/sim/testbenches/cache_controller_tb.mpf @@ -238,7 +238,7 @@ IterationLimit = 5000 ; Stop the simulator after a VHDL/Verilog assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 +BreakOnAssertion = 1 ; Assertion Message Format ; %S - Severity Level @@ -254,7 +254,7 @@ BreakOnAssertion = 3 ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned -DefaultRadix = symbolic +DefaultRadix = hexadecimal ; VSIM Startup command ; Startup = do startup.do @@ -411,39 +411,17 @@ suppress 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work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Files_Count = 5 +Project_File_0 = /home/ikey/repos/riscv-processor/src/write_through_cache.v +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1731785580 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/ikey/repos/riscv-processor/src/cache_miss_controller.v +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1731803920 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = /home/ikey/repos/riscv-processor/sim/src/stallmem.v +Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1731645382 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_3 = /home/ikey/repos/riscv-processor/src/cache.v +Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1731863104 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_4 = /home/ikey/repos/riscv-processor/sim/testbenches/cache_controller_tb.v +Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1731777563 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/sim/testbenches/cache_controller_tb.v b/sim/testbenches/cache_controller_tb.v new file mode 100644 index 0000000..c3d3a0e --- /dev/null +++ b/sim/testbenches/cache_controller_tb.v @@ -0,0 +1,99 @@ +`timescale 1us/100ns + +module cache_controller_tb #(parameter BYTES_PER_WORD = 4, + parameter WORD_SIZE = 32, + parameter INDEX_BITS = 5, // Index into cache + parameter CACHE_LINES = 2**INDEX_BITS, // Number of cache lines + parameter BLOCK_OFFSET = 6, + parameter DATA_LENGTH = 2**BLOCK_OFFSET, // Cache line length in bytes + parameter TAG_BITS = 32 - INDEX_BITS - BLOCK_OFFSET, + parameter STATUS_BITS = 1, + parameter LINE_LENGTH = TAG_BITS + DATA_LENGTH*8 + STATUS_BITS, + parameter WORDS_PER_DATA_BLOCK = DATA_LENGTH / BYTES_PER_WORD)(); + reg clk; + reg rst; + + wire ready; + wire err; + + wire stall; + wire [WORD_SIZE-1:0] data_out; + reg [WORD_SIZE-1:0] data_in; + reg [31:0] addr; + wire [31:0] ext_addr; + wire [31:0] data_to_ext_mem; + reg wr; + reg re; + wire [31:0] data_from_ext_mem; + wire ext_re; + wire ext_wr; + + stallmem mem (.data_out(data_from_ext_mem), + .ready(ready), + .data_in(data_to_ext_mem), + .addr(ext_addr[15:2]), + .enable(1'b1), + .wr(ext_wr), + .createdump(1'b1), + .clk(clk), + .rst(rst), + .err(err)); + + write_through_cache #(.INDEX_BITS(INDEX_BITS), + .CACHE_LINES(CACHE_LINES), + .BLOCK_OFFSET(BLOCK_OFFSET), + .DATA_LENGTH(DATA_LENGTH), + .TAG_BITS(TAG_BITS), + .STATUS_BITS(STATUS_BITS), + .LINE_LENGTH(LINE_LENGTH), + .WORD_SIZE(WORD_SIZE), + .WORD_BYTES(BYTES_PER_WORD)) + cache (.data_out(data_out), + .data_in(data_in), + .addr(addr), + .wr(wr), + .re(re), + .enable(1'b1), + .stall(stall), + .ext_data_out(data_to_ext_mem), + .ext_data_in(data_from_ext_mem), + .ext_addr(ext_addr), + .ext_wr(ext_wr), + .ext_re(ext_re), + .ext_ack(ready), + .clk(clk), + .rst(rst)); + + always #5 clk = ~clk; + + initial begin + clk = 0; + rst = 0; + data_in = 32'b0; + addr = 32'h0; + wr = 1'b0; + re = 1'b0; + + // reset logic + #2; + rst = 1; + #10; + rst = 0; + + #10 + data_in = {32{1'b1}}; + addr = 32'hf0; + wr = 1'b1; + #10 + addr = 32'h1; + wr = 1'b0; + re = 1'b1; + + + + + #50000; + $finish; + end + +endmodule \ No newline at end of file diff --git a/sim/testbenches/proc_tb.mpf b/sim/testbenches/proc_tb.mpf new file mode 100644 index 0000000..db031ea --- /dev/null +++ b/sim/testbenches/proc_tb.mpf @@ -0,0 +1,515 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 10 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = hexadecimal + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +suppress = 3116 +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 26 +Project_File_0 = /home/ikey/repos/riscv-processor/src/sdram_read.v +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/ikey/repos/riscv-processor/src/sdram_controller.v +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = /home/ikey/repos/riscv-processor/src/fetch.v +Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1755369118 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_3 = /home/ikey/repos/riscv-processor/src/proc.v +Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_4 = /home/ikey/repos/riscv-processor/src/cache.v +Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1744435947 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_5 = /home/ikey/repos/riscv-processor/src/decode.v +Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_6 = /home/ikey/repos/riscv-processor/src/latch.v +Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_7 = /home/ikey/repos/riscv-processor/src/reg_dff.v +Project_File_P_7 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_8 = /home/ikey/repos/riscv-processor/src/memory_system.v +Project_File_P_8 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1753572846 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_9 = /home/ikey/repos/riscv-processor/src/hazards.v +Project_File_P_9 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_10 = /home/ikey/repos/riscv-processor/sim/src/sdram_model.v +Project_File_P_10 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_11 = /home/ikey/repos/riscv-processor/src/sdram_write.v +Project_File_P_11 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_12 = /home/ikey/repos/riscv-processor/src/decode_logic.v +Project_File_P_12 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1726799662 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_13 = /home/ikey/repos/riscv-processor/src/risc_de10.v +Project_File_P_13 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_14 = /home/ikey/repos/riscv-processor/src/alu.v +Project_File_P_14 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1726799662 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_15 = /home/ikey/repos/riscv-processor/src/cache_miss_controller.v +Project_File_P_15 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1744594572 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_16 = /home/ikey/repos/riscv-processor/src/reg_file.v +Project_File_P_16 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_17 = /home/ikey/repos/riscv-processor/src/write_through_cache.v +Project_File_P_17 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_18 = /home/ikey/repos/riscv-processor/src/sram.sv +Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_19 = /home/ikey/repos/riscv-processor/src/memory_map.v +Project_File_P_19 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1749270588 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_20 = /home/ikey/repos/riscv-processor/src/de10_bus_controller.v +Project_File_P_20 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_21 = /home/ikey/repos/riscv-processor/src/left_barrel_shifter.v +Project_File_P_21 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_22 = /home/ikey/repos/riscv-processor/src/sdram_intialize.v +Project_File_P_22 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_23 = /home/ikey/repos/riscv-processor/src/de10_peripherals.v +Project_File_P_23 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1743651132 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_24 = /home/ikey/repos/riscv-processor/sim/testbenches/proc_tb.v +Project_File_P_24 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1743651132 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_25 = /home/ikey/repos/riscv-processor/src/right_barrel_shifter.v +Project_File_P_25 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1726799662 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/sim/testbenches/proc_tb.v b/sim/testbenches/proc_tb.v new file mode 100644 index 0000000..7c835bd --- /dev/null +++ b/sim/testbenches/proc_tb.v @@ -0,0 +1,79 @@ + +`timescale 1us/100ns + +module proc_tb(); + reg clk; + + // input and output ports + wire [12:0] dram_addr; + wire [1:0] dram_ba; + wire dram_cas_n; + wire dram_cke; + wire dram_clk; + wire dram_cs_n; + wire [15:0] dram_dq; + wire dram_ldqm; + wire dram_ras_n; + wire dram_udqm; + wire dram_we_n; + reg [1:0] key; + wire [9:0] ledr; + wire [3:0] vga_b; + wire [3:0] vga_g; + wire vga_hs; + wire [3:0] vga_r; + wire vga_vs; + wire [35:0] gpio; + + sdram_model sdram (.in_CLK(clk), + .in_CS(dram_cs_n), // CHIP SELECT + .in_write_en(dram_we_n), + .in_CAS(dram_cs_n), //COLUMN ADRESS STROBE + .in_RAS(dram_ras_n), //ROW ADRESS STROBE + .in_bank_select(dram_ba), // BANK SELECTION BITS + .in_sdram_addr(dram_addr), + .dram_ldqm(dram_ldqm), + .dram_udqm(dram_udqm), + .dq(dram_dq)); + + risc_de10 board (.ADC_CLK_10(clk), + .MAX10_CLK1_50(clk), + .MAX10_CLK2_50(clk), + .DRAM_ADDR(dram_addr), + .DRAM_BA(dram_ba), + .DRAM_CAS_N(dram_cas_n), + .DRAM_CKE(dram_cke), + .DRAM_CLK(dram_clk), + .DRAM_CS_N(dram_cs_n), + .DRAM_DQ(dram_dq), + .DRAM_LDQM(dram_ldqm), + .DRAM_RAS_N(dram_ras_n), + .DRAM_UDQM(dram_udqm), + .DRAM_WE_N(dram_we_n), + .KEY(key), + .LEDR(ledr), + .VGA_B(vga_b), + .VGA_G(vga_g), + .VGA_HS(vga_hs), + .VGA_R(vga_r), + .VGA_VS(vga_vs), + .GPIO(gpio) + ); + + always #5 clk = ~clk; + + initial begin + clk = 0; + key = 2'b11; + + // reset logic + #2; + key = 2'b00; + #10; + key = 2'b11; + + #50000; + $finish; + end + +endmodule \ No newline at end of file diff --git a/sim/transcript b/sim/transcript deleted file mode 100644 index 4f417cb..0000000 --- a/sim/transcript +++ /dev/null @@ -1,64 +0,0 @@ -# Compile of stallmem.v was successful. -# Compile of memory2c.v was successful. -# Compile of proc_tb.v was successful. -# Compile of alu.v was successful. -# Compile of decode.v was successful. -# Compile of decode_logic.v was successful. -# Compile of fetch.v was successful. -# Compile of hazards.v failed with 1 errors. -# Compile of latch.v was successful. -# Compile of left_barrel_shifter.v was successful. -# Compile of proc.v was successful. -# Compile of reg_dff.v was successful. -# Compile of reg_file.v was successful. -# Compile of right_barrel_shifter.v was successful. -# Compile of data_addr_bus_controller.v was successful. -# 15 compiles, 1 failed with 1 error. -# Compile of stallmem.v was successful. -# Compile of memory2c.v was successful. -# Compile of proc_tb.v was successful. -# Compile of alu.v was successful. -# Compile of decode.v was successful. -# Compile of decode_logic.v was successful. -# Compile of fetch.v was successful. -# Compile of hazards.v failed with 2 errors. -# Compile of latch.v was successful. -# Compile of left_barrel_shifter.v was successful. -# Compile of proc.v was successful. -# Compile of reg_dff.v was successful. -# Compile of reg_file.v was successful. -# Compile of right_barrel_shifter.v was successful. -# Compile of data_addr_bus_controller.v was successful. -# 15 compiles, 1 failed with 2 errors. -# Compile of stallmem.v was successful. -# Compile of memory2c.v was successful. -# Compile of proc_tb.v was successful. -# Compile of alu.v was successful. -# Compile of decode.v was successful. -# Compile of decode_logic.v was successful. -# Compile of fetch.v was successful. -# Compile of hazards.v failed with 1 errors. -# Compile of latch.v was successful. -# Compile of left_barrel_shifter.v was successful. -# Compile of proc.v was successful. -# Compile of reg_dff.v was successful. -# Compile of reg_file.v was successful. -# Compile of right_barrel_shifter.v was successful. -# Compile of data_addr_bus_controller.v was successful. -# 15 compiles, 1 failed with 1 error. -# Compile of stallmem.v was successful. -# Compile of memory2c.v was successful. -# Compile of proc_tb.v was successful. -# Compile of alu.v was successful. -# Compile of decode.v was successful. -# Compile of decode_logic.v was successful. -# Compile of fetch.v was successful. -# Compile of hazards.v was successful. -# Compile of latch.v was successful. -# Compile of left_barrel_shifter.v was successful. -# Compile of proc.v was successful. -# Compile of reg_dff.v was successful. -# Compile of reg_file.v was successful. -# Compile of right_barrel_shifter.v was successful. -# Compile of data_addr_bus_controller.v was successful. -# 15 compiles, 0 failed with no errors. diff --git a/alu.v b/src/alu.sv similarity index 56% rename from alu.v rename to src/alu.sv index f0c08a2..f3205f2 100644 --- a/alu.v +++ b/src/alu.sv @@ -1,20 +1,16 @@ `timescale 1us/100ns -`include "left_barrel_shifter.v" -`include "right_barrel_shifter.v" - -module alu(bits_a, bits_b, func, out_bits, compare_val); +module alu( + input [31:0] data1, + input [31:0] data2, + input [9:0] func, + output reg [31:0] odata, + output reg compare_val); `include "proc_params.h" - input [31:0] bits_a; - input [31:0] bits_b; - input [9:0] func; - output reg [31:0] out_bits; - output reg compare_val; - - reg [31:0] compare_bits; - reg not_equal; - reg lesser; + wire [31:0] compare_bits; + wire not_equal; + wire lesser; wire [31:0] add_sub_bits; wire [31:0] and_bits; @@ -24,40 +20,40 @@ module alu(bits_a, bits_b, func, out_bits, compare_val); wire [31:0] bsl_bits; wire [31:0] bsr_bits; - left_barrel_shifter lbs(.in_bits(bits_a), .out_bits(bsl_bits), .shift_len(bits_b[4:0])); - right_barrel_shifter rbs(.in_bits(bits_a), .out_bits(bsr_bits), .shift_len(bits_b[4:0]), .arithmetic(func[8])); + left_barrel_shifter lbs(.idata(data1), .odata(bsl_bits), .shift_len(data2[4:0])); + right_barrel_shifter rbs(.idata(data1), .odata(bsr_bits), .shift_len(data2[4:0]), .arithmetic(func[8])); - assign add_sub_bits = bits_a + bits_b; - assign and_bits = bits_a & bits_b; - assign or_bits = bits_a | bits_b; - assign xor_bits = bits_a ^ bits_b; - assign compare_bits = bits_a - bits_b; + assign add_sub_bits = data1 + data2; + assign and_bits = data1 & data2; + assign or_bits = data1 | data2; + assign xor_bits = data1 ^ data2; + assign compare_bits = data1 - data2; assign not_equal = |compare_bits; - assign lesser = compare_bits[31]; // bits_a is less than bits_b + assign lesser = compare_bits[31]; // data1 is less than data2 always @ (*) begin // Arithmetic Computation case({func[2:0]}) `RISC_ADD_SUB_OP: begin - out_bits = add_sub_bits; // Replace with homebrew carry-look-ahead + odata = add_sub_bits; // Replace with homebrew carry-look-ahead end `RISC_AND_OP: begin - out_bits = and_bits; + odata = and_bits; end `RISC_OR_OP: begin - out_bits = or_bits; + odata = or_bits; end `RISC_XOR_OP: begin - out_bits = xor_bits; + odata = xor_bits; end `RISC_SHIFT_LEFT: begin - out_bits = bsl_bits; + odata = bsl_bits; end `RISC_SHIFT_RIGHT: begin - out_bits = bsr_bits; + odata = bsr_bits; end default: begin - out_bits = bits_a; + odata = data1; end endcase diff --git a/src/cache.sv b/src/cache.sv new file mode 100644 index 0000000..de9c253 --- /dev/null +++ b/src/cache.sv @@ -0,0 +1,201 @@ +`timescale 1us/100ns + +module cache #(parameter BYTES_PER_WORD = 4, + parameter WORD_SIZE = 32, + parameter INDEX_BITS = 5, // Index into cache + parameter CACHE_LINES = 2**INDEX_BITS, // Number of cache lines + parameter BLOCK_OFFSET = 6, + parameter DATA_LENGTH = 2**BLOCK_OFFSET, // Cache line length in bytes + parameter TAG_BITS = 32 - INDEX_BITS - BLOCK_OFFSET, + parameter STATUS_BITS = 1, + parameter LINE_LENGTH = TAG_BITS + DATA_LENGTH*8 + STATUS_BITS, + parameter WORDS_PER_DATA_BLOCK = DATA_LENGTH / BYTES_PER_WORD + ) + ( + output reg [WORD_SIZE-1:0] data_out, + input [WORD_SIZE-1:0] data_in, + input [LINE_LENGTH-1:0] new_cache_line, + input [31:0] addr, + input full_line_wr, + input wr, + input re, + input enable, + output hit, + + // Clock and reset + input clk, + input rst); + + wire [TAG_BITS-1:0] tag; + wire [INDEX_BITS-1:0] index; + wire [BLOCK_OFFSET-3:0] offset; + + wire valid; + wire [TAG_BITS-1:0] line_tag; + + reg [LINE_LENGTH-1:0] mem [CACHE_LINES-1:0]; + + assign index = addr[INDEX_BITS+BLOCK_OFFSET-1:BLOCK_OFFSET]; + assign tag = addr[31:INDEX_BITS+BLOCK_OFFSET]; + assign offset = addr[BLOCK_OFFSET-1:2]; + assign valid = mem[index][0]; + assign line_tag = mem[index][LINE_LENGTH-1:LINE_LENGTH-TAG_BITS]; + + integer i; + initial begin + for (i = 0; i< CACHE_LINES; i=i+1) begin + mem[i] = {LINE_LENGTH{1'b0}}; + end + end + + assign hit = (valid == 1'b1) & (line_tag == tag); + + always @(*) begin + if (rst | ~enable) begin + data_out <= {WORD_SIZE{1'b0}}; + end + else begin + case (offset) + 4'd0: + begin + data_out <= mem[index][WORD_SIZE + STATUS_BITS - 1: STATUS_BITS]; + end + 4'd1: + begin + data_out <= mem[index][2*WORD_SIZE + STATUS_BITS - 1: WORD_SIZE + STATUS_BITS]; + end + 4'd2: + begin + data_out <= mem[index][3*WORD_SIZE + STATUS_BITS - 1: 2*WORD_SIZE + STATUS_BITS]; + end + 4'd3: + begin + data_out <= mem[index][4*WORD_SIZE + STATUS_BITS - 1: 3*WORD_SIZE + STATUS_BITS]; + end + 4'd4: + begin + data_out <= mem[index][5*WORD_SIZE + STATUS_BITS - 1: 4*WORD_SIZE + STATUS_BITS]; + end + 4'd5: + begin + data_out <= mem[index][6*WORD_SIZE + STATUS_BITS - 1: 5*WORD_SIZE + STATUS_BITS]; + end + 4'd6: + begin + data_out <= mem[index][7*WORD_SIZE + STATUS_BITS - 1: 6*WORD_SIZE + STATUS_BITS]; + end + 4'd7: + begin + data_out <= mem[index][8*WORD_SIZE + STATUS_BITS - 1: 7*WORD_SIZE + STATUS_BITS]; + end + 4'd8: + begin + data_out <= mem[index][9*WORD_SIZE + STATUS_BITS - 1: 8*WORD_SIZE + STATUS_BITS]; + end + 4'd9: + begin + data_out <= mem[index][10*WORD_SIZE + STATUS_BITS - 1: 9*WORD_SIZE + STATUS_BITS]; + end + 4'd10: + begin + data_out <= mem[index][11*WORD_SIZE + STATUS_BITS - 1: 10*WORD_SIZE + STATUS_BITS]; + end + 4'd11: + begin + data_out <= mem[index][12*WORD_SIZE + STATUS_BITS - 1: 11*WORD_SIZE + STATUS_BITS]; + end + 4'd12: + begin + data_out <= mem[index][13*WORD_SIZE + STATUS_BITS - 1: 12*WORD_SIZE + STATUS_BITS]; + end + 4'd13: + begin + data_out <= mem[index][14*WORD_SIZE + STATUS_BITS - 1: 13*WORD_SIZE + STATUS_BITS]; + end + 4'd14: + begin + data_out <= mem[index][15*WORD_SIZE + STATUS_BITS - 1: 14*WORD_SIZE + STATUS_BITS]; + end + 4'd15: + begin + data_out <= mem[index][16*WORD_SIZE + STATUS_BITS - 1: 15*WORD_SIZE + STATUS_BITS]; + end + endcase + end + end + + always @(posedge clk or posedge rst) begin + if (full_line_wr & enable) begin + mem[index] <= new_cache_line; + end + + if (hit & wr & ~re & enable) begin + case (offset) + 4'd0: + begin + mem[index][WORD_SIZE + STATUS_BITS - 1: STATUS_BITS] <= data_in; + end + 4'd1: + begin + mem[index][2*WORD_SIZE + STATUS_BITS - 1: WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd2: + begin + mem[index][3*WORD_SIZE + STATUS_BITS - 1: 2*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd3: + begin + mem[index][4*WORD_SIZE + STATUS_BITS - 1: 3*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd4: + begin + mem[index][5*WORD_SIZE + STATUS_BITS - 1: 4*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd5: + begin + mem[index][6*WORD_SIZE + STATUS_BITS - 1: 5*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd6: + begin + mem[index][7*WORD_SIZE + STATUS_BITS - 1: 6*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd7: + begin + mem[index][8*WORD_SIZE + STATUS_BITS - 1: 7*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd8: + begin + mem[index][9*WORD_SIZE + STATUS_BITS - 1: 8*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd9: + begin + mem[index][10*WORD_SIZE + STATUS_BITS - 1: 9*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd10: + begin + mem[index][11*WORD_SIZE + STATUS_BITS - 1: 10*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd11: + begin + mem[index][12*WORD_SIZE + STATUS_BITS - 1: 11*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd12: + begin + mem[index][13*WORD_SIZE + STATUS_BITS - 1: 12*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd13: + begin + mem[index][14*WORD_SIZE + STATUS_BITS - 1: 13*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd14: + begin + mem[index][15*WORD_SIZE + STATUS_BITS - 1: 14*WORD_SIZE + STATUS_BITS] <= data_in; + end + 4'd15: + begin + mem[index][16*WORD_SIZE + STATUS_BITS - 1: 15*WORD_SIZE + STATUS_BITS] <= data_in; + end + endcase + end + end +endmodule \ No newline at end of file diff --git a/src/cache_miss_controller.sv b/src/cache_miss_controller.sv new file mode 100644 index 0000000..8b3fd86 --- /dev/null +++ b/src/cache_miss_controller.sv @@ -0,0 +1,265 @@ +`timescale 1us/100ns + +`define CONTROLLER_IDLE 4'b0000 +`define CONTROLLER_READ 4'b0001 +`define CONTROLLER_READING 4'b0011 +`define CONTROLLER_WRITE 4'b0010 +`define CONTROLLER_READ_FIN 4'b0100 +`define CONTROLLER_WRITE_FIN 4'b1000 +`define CONTROLLER_CACHE_WRITE 4'b0111 + +module cache_miss_controller#(parameter BYTES_PER_WORD = 4, + parameter WORD_SIZE = 32, + parameter INDEX_BITS = 5, // Index into cache + parameter CACHE_LINES = 2**INDEX_BITS, // Number of cache lines + parameter BLOCK_OFFSET = 6, + parameter DATA_LENGTH = 2**BLOCK_OFFSET, // Cache line length in bytes + parameter TAG_BITS = 32 - INDEX_BITS - BLOCK_OFFSET, + parameter STATUS_BITS = 1, + parameter LINE_LENGTH = TAG_BITS + DATA_LENGTH*8 + STATUS_BITS, + parameter WORDS_PER_DATA_BLOCK = DATA_LENGTH / BYTES_PER_WORD) + ( + input [31:0] addr, + input [WORD_SIZE-1:0] data_from_cache, + output reg [LINE_LENGTH-1:0] data_to_cache, + input [WORD_SIZE-1:0] ext_data_in, + output reg [WORD_SIZE-1:0] ext_data_out, + output [31:0] ext_addr, + input ext_ack, + output reg ext_re, + output reg ext_wr, + output reg wr_ack, + output reg re_ack, + input re, + input wr, + output reg full_line_wr, + input enable, + input clk, + input rst + ); + + wire [TAG_BITS-1:0] tag; + + reg [DATA_LENGTH*8-1:0] data; + reg read_into_data; + reg [3:0] state; + reg update_addr; + reg [7:0] counter; + reg [31:0] curr_addr; + reg ctr_rst; + reg update_counter; + + assign tag = addr[31:INDEX_BITS+BLOCK_OFFSET]; + assign ext_addr = curr_addr; + + always @(posedge update_addr or posedge update_counter or posedge ctr_rst or posedge rst or posedge enable) + begin + if (ctr_rst | rst | ~enable) begin + counter <= #1 8'b0; + curr_addr <= #1 32'b0; + end + else begin + if(update_addr) begin + if (update_counter) begin + counter <= #1 (counter + 1'b1); + curr_addr <= #1 curr_addr + 4; + end + else begin + counter <= #1 counter; + if (counter == 0) begin + if (wr) begin + curr_addr <= #1 addr; + end + else begin + curr_addr <= #1 addr & ~32'b111111; + end + end + else begin + curr_addr <= #1 curr_addr; + end + end + end + else begin + counter <= #1 counter; + curr_addr <= #1 curr_addr; + end + end + end + assign data_count = (counter == (DATA_LENGTH >> 2)); + + always @(posedge read_into_data or posedge rst) + begin + if (rst) begin + data <= #1 {DATA_LENGTH*8{1'b0}}; + end + else begin + data <= #1 ((data >> WORD_SIZE) | {ext_data_in, {DATA_LENGTH*8-WORD_SIZE{1'b0}}}); + end + end + + always @(posedge clk) begin + if (rst | ~enable) begin + state <= `CONTROLLER_IDLE; + end + else begin + case(state) + `CONTROLLER_IDLE: + if(wr | re) begin + if (wr) begin + state <= `CONTROLLER_WRITE; + end + else begin + state <= `CONTROLLER_READ; + end + end + else begin + state <= `CONTROLLER_IDLE; + end + `CONTROLLER_WRITE: + if (ext_ack) begin + state <= `CONTROLLER_WRITE_FIN; + end + else begin + state <= `CONTROLLER_WRITE; + end + `CONTROLLER_WRITE_FIN: + state <= `CONTROLLER_IDLE; + `CONTROLLER_READ: + if (data_count) begin + state <= `CONTROLLER_CACHE_WRITE; + end + else begin + if (ext_ack) begin + state <= `CONTROLLER_READING; + end + else begin + state <= `CONTROLLER_READ; + end + end + `CONTROLLER_READING: + if (data_count) begin + state <= `CONTROLLER_CACHE_WRITE; + end + else begin + if (ext_ack) begin + state <= `CONTROLLER_READ; + end + else begin + state <= `CONTROLLER_READING; + end + end + `CONTROLLER_CACHE_WRITE: + state <= `CONTROLLER_READ_FIN; + `CONTROLLER_READ_FIN: + state <= `CONTROLLER_IDLE; + default: + state <= `CONTROLLER_IDLE; + endcase + end + end + + always @(state) + begin + case(state) + `CONTROLLER_IDLE: + begin + data_to_cache <= #2 {LINE_LENGTH{1'b0}}; + ext_data_out <= #2 {WORD_SIZE{1'b0}}; + read_into_data <= #2 1'b0; + ext_re <= #2 1'b0; + ext_wr <= #2 1'b0; + full_line_wr <= #2 1'b0; + wr_ack <= #2 1'b0; + re_ack <= #2 1'b0; + update_addr <= #2 1'b0; + update_counter <= #2 1'b0; + ctr_rst <= #2 1'b1; + end + `CONTROLLER_WRITE: + begin + data_to_cache <= #2 {LINE_LENGTH{1'b0}}; + ext_data_out <= #2 data_from_cache; + read_into_data <= #2 1'b0; + ext_re <= #2 1'b0; + ext_wr <= #2 1'b1; + full_line_wr <= #2 1'b0; + wr_ack <= #2 1'b0; + re_ack <= #2 1'b0; + update_addr <= #2 1'b1; + update_counter <= #2 1'b0; + ctr_rst <= #2 1'b0; + end + `CONTROLLER_WRITE_FIN: + begin + data_to_cache <= #2 {LINE_LENGTH{1'b0}}; + ext_data_out <= #2 data_from_cache; + read_into_data <= #2 1'b0; + ext_re <= #2 1'b0; + ext_wr <= #2 1'b0; + full_line_wr <= #2 1'b0; + wr_ack <= #2 1'b1; + re_ack <= #2 1'b0; + update_addr <= #2 1'b0; + update_counter <= #2 1'b0; + ctr_rst <= #2 1'b0; + end + `CONTROLLER_READ: + begin + data_to_cache <= #2 {LINE_LENGTH{1'b0}}; + ext_data_out <= #2 {WORD_SIZE{1'b0}}; + read_into_data <= #2 1'b0; + ext_re <= #2 1'b1; + ext_wr <= #2 1'b0; + full_line_wr <= #2 1'b0; + wr_ack <= #2 1'b0; + re_ack <= #2 1'b0; + update_addr <= #2 1'b1; + update_counter <= #2 1'b0; + ctr_rst <= #2 1'b0; + end + `CONTROLLER_READING: + begin + data_to_cache <= #2 {LINE_LENGTH{1'b0}}; + ext_data_out <= #2 {WORD_SIZE{1'b0}}; + read_into_data <= #2 1'b1; + ext_re <= #2 1'b1; + ext_wr <= #2 1'b0; + full_line_wr <= #2 1'b0; + wr_ack <= #2 1'b0; + re_ack <= #2 1'b0; + update_addr <= #2 1'b1; + update_counter <= #2 1'b1; + ctr_rst <= #2 1'b0; + end + `CONTROLLER_CACHE_WRITE: + begin + data_to_cache <= #2 {tag, data, 1'b1}; + ext_data_out <= #2 {WORD_SIZE{1'b0}}; + read_into_data <= #2 1'b1; + ext_re <= #2 1'b0; + ext_wr <= #2 1'b0; + full_line_wr <= #2 1'b1; + wr_ack <= #2 1'b0; + re_ack <= #2 1'b0; + update_addr <= #2 1'b0; + update_counter <= #2 1'b0; + ctr_rst <= #2 1'b0; + end + `CONTROLLER_READ_FIN: + begin + data_to_cache <= #2 {LINE_LENGTH{1'b0}}; + ext_data_out <= #2 {WORD_SIZE{1'b0}}; + read_into_data <= #2 1'b0; + ext_re <= #2 1'b0; + ext_wr <= #2 1'b0; + full_line_wr <= #2 1'b0; + wr_ack <= #2 1'b0; + re_ack <= #2 1'b1; + update_addr <= #2 1'b0; + update_counter <= #2 1'b0; + ctr_rst <= #2 1'b0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/src/de10_bus_controller.sv b/src/de10_bus_controller.sv new file mode 100644 index 0000000..557e1ca --- /dev/null +++ b/src/de10_bus_controller.sv @@ -0,0 +1,73 @@ +module de10_bus_controller( + input [31:0] addr, + input [31:0] sram_data, + input [31:0] sdram_data, + input [31:0] peripheral_data, + input sram_ready, + input sdram_ready, + input peripheral_ready, + output oen_sram, + output oen_sdram, + output oen_peripherals, + output reg [31:0] odata, + output omem_ready, + input clk, + input rst); + + wire [9:0] tag; + + reg en_sram; + reg en_sdram; + reg en_peripherals; + reg mem_ready; + + assign tag = addr[31:22]; + + assign oen_sram = en_sram; + assign oen_sdram = en_sdram; + assign oen_peripherals = en_peripherals; + assign omem_ready = mem_ready; + + always @ (*) begin + if (tag == 10'h0) begin + en_sram <= 1'b1; + en_sdram <= 1'b0; + en_peripherals <= 1'b0; + mem_ready <= sram_ready; + end + else if (tag == 10'h1) begin + en_sram <= 1'b0; + en_sdram <= 1'b0; + en_peripherals <= 1'b1; + mem_ready <= peripheral_ready; + end + else if (tag == 10'h2) begin + en_sram <= 1'b0; + en_sdram <= 1'b1; + en_peripherals <= 1'b0; + mem_ready <= sdram_ready; + end + else begin + en_sram <= 1'b0; + en_sdram <= 1'b0; + en_peripherals <= 1'b0; + mem_ready <= 1'b1; + end + end + + always @ (*) begin + if (tag == 10'h0) begin + odata <= sram_data; + end + else if (tag == 10'h1) begin + odata <= peripheral_data; + end + else if (tag == 10'h2) begin + odata <= sdram_data; + end + else begin + odata <= 32'b0; + end + end + +endmodule \ No newline at end of file diff --git a/src/de10_peripherals.sv b/src/de10_peripherals.sv new file mode 100644 index 0000000..c6572d6 --- /dev/null +++ b/src/de10_peripherals.sv @@ -0,0 +1,60 @@ +`timescale 1us/100ns + +`define PERIPH_REG_NUM 2 +`define ADDR_LEN 22 +module de10_peripherals( + input [31:0] addr, + input wr, + input [31:0] idata, + output [31:0] odata, + input clk, + input rst, + output [9:0] LEDR, + inout [35:0] GPIO +); + wire [21:0] periph_addr; + wire [31:0] qn [`PERIPH_REG_NUM-1:0]; + reg [`PERIPH_REG_NUM-1:0] we; + reg [31:0] data; + reg [31:0] delayed_data; + + assign periph_addr = addr[21:0]; + assign LEDR = qn[0][9:0]; + assign GPIO = {qn[1][13:0], qn[0][31:10]}; + assign #(1) odata = data; + + reg_dflop gpio1 [31:0] (.q(qn[0]), .d(idata), .we(we[0]), .clk(clk), .rst(rst)); + reg_dflop gpio2 [31:0] (.q(qn[1]), .d(idata), .we(we[1]), .clk(clk), .rst(rst)); + + always @ (*) begin + case({periph_addr}) + 22'd0: begin + data <= qn[0]; + end + 22'd1: begin + data <= qn[1]; + end + default: begin + data <= 32'b0; + end + endcase + + if (wr) begin + case({periph_addr}) + 22'd0: begin + we <= `PERIPH_REG_NUM'b01; + end + 22'd1: begin + we <= `PERIPH_REG_NUM'b10; + end + default: begin + we <= `PERIPH_REG_NUM'b00; + end + endcase + end + else begin + we <= `PERIPH_REG_NUM'b00; + end + end + +endmodule \ No newline at end of file diff --git a/src/decode.sv b/src/decode.sv new file mode 100644 index 0000000..ba041e2 --- /dev/null +++ b/src/decode.sv @@ -0,0 +1,122 @@ +`timescale 1us/100ns + +module decode_register_select( + output [4:0] a0, // Register identifiers for computation + output [4:0] a1, + output [4:0] a2, + output [4:0] a2_hazard, // Register identifier going to hazard controller + output [31:0] imm_to_reg, // Immediate value going to register file + output [31:0] imm_to_addr, // Immediate value going to address bus + output [9:0] func, // Function value for ALU control + output en_jmp, // Enables jumps + output en_uncond_jmp, // Signals unconditional jump + output en_rel_reg_jmp, // Signals relative from register jump + output en_mem_wr, // Enables write to memory + output en_mem_re, // Enables read to memory + output [2:0] ld_code, // Load code for write-back stage + output [31:0] alu_data1, // 1st argument for ALU + output [31:0] alu_data2, // 2nd argument for ALU + output [31:0] data_to_mem, // Data going to memory + output en_reg_wr, // Enables write to memory + input [31:0] instr, // Instruction + input [31:0] d0, // 1st piece of data from register file + input [31:0] d1, // 2nd piece of data from register file + input stall, // Signal for stalling pipeline + input squash, // Signal to squash instruction + input clk, // Clock + input rst); // Reset + + // Enables immediates for computation + wire en_imm; + wire input_en_jmp; + wire input_en_uncond_jmp; + wire input_en_rel_reg_jmp; + wire [9:0] input_func; + reg [31:0] alu_input_data2; + wire [31:0] input_imm; + wire [2:0] input_ld_code; + wire [4:0] input_a2; + + wire input_en_reg_wr; + wire en_reg_wr_conn_latch1; + wire en_reg_wr_conn_latch2; + pipeline_latch en_reg_wr_latch1 (.q(en_reg_wr_conn_latch1), .d(~squash & input_en_reg_wr), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch en_reg_wr_latch2 (.q(en_reg_wr_conn_latch2), .d(en_reg_wr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch en_reg_wr_latch3 (.q(en_reg_wr), .d(en_reg_wr_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); + + pipeline_latch en_jmp_latch (.q(en_jmp), .d(~squash & input_en_jmp), .stall(stall), .clk(clk), .rst(rst)); + + pipeline_latch en_uncond_jmp_latch (.q(en_uncond_jmp), .d(~squash & input_en_uncond_jmp), .stall(stall), .clk(clk), .rst(rst)); + + pipeline_latch en_rel_reg_jmp_latch (.q(en_rel_reg_jmp), .d(~squash &input_en_rel_reg_jmp), .stall(stall), .clk(clk), .rst(rst)); + + // Function code for ALU latch + pipeline_latch function_code_latch [9:0] (.q(func), .d({10{~squash}} & input_func), .stall(stall), .clk(clk), .rst(rst)); + + // Data for ALU computation latch + pipeline_latch data1_latch [31:0] (.q(alu_data1), .d({32{~squash}} & d0), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch data2_latch [31:0] (.q(alu_data2), .d({32{~squash}} & alu_input_data2), .stall(stall), .clk(clk), .rst(rst)); + + // Memory data in latch + wire [31:0] data_to_mem_conn_latch1; + pipeline_latch data_to_mem_latch1 [31:0] (.q(data_to_mem_conn_latch1), .d({32{~squash}} & d1), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch data_to_mem_latch2 [31:0] (.q(data_to_mem), .d(data_to_mem_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + + // Immediate latch + wire [31:0] imm_conn_latch_conn; + pipeline_latch immediate_latch1 [31:0] (.q(imm_to_addr), .d({32{~squash}} & input_imm), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch immediate_latch2 [31:0] (.q(imm_conn_latch_conn), .d(imm_to_addr), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch immediate_latch3 [31:0] (.q(imm_to_reg), .d(imm_conn_latch_conn), .stall(stall), .clk(clk), .rst(rst)); + + // Enable memory write latch + wire input_en_mem_wr; + wire en_mem_wr_conn_latch1; + pipeline_latch en_mem_wr_latch1(.q(en_mem_wr_conn_latch1), .d(~squash & input_en_mem_wr), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch en_mem_wr_latch2(.q(en_mem_wr), .d(en_mem_wr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + + // Enable memory read latch + wire input_en_mem_re; + wire en_mem_re_conn_latch1; + pipeline_latch en_mem_re_latch1(.q(en_mem_re_conn_latch1), .d(~squash & input_en_mem_re), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch en_mem_re_latch2(.q(en_mem_re), .d(en_mem_re_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + + // Load Code latch + wire [2:0] ld_code_conn_latch1; + wire [2:0] ld_code_conn_latch2; + pipeline_latch ld_code_latch1 [2:0] (.q(ld_code_conn_latch1), .d({3{~squash}} & input_ld_code), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch ld_code_latch2 [2:0] (.q(ld_code_conn_latch2), .d(ld_code_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch ld_code_latch3 [2:0] (.q(ld_code), .d(ld_code_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); + + // a2 latch to tell the register file at the correct time + wire [4:0] a2_conn_latch1; + wire [4:0] a2_conn_latch2; + pipeline_latch a2_latch1 [4:0] (.q(a2_conn_latch1), .d({5{~squash}} & input_a2), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch a2_latch2 [4:0] (.q(a2_conn_latch2), .d(a2_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch a2_latch3 [4:0] (.q(a2), .d(a2_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); + + // Decode Logic + decode_logic dec (.a0(a0), + .a1(a1), + .a2(input_a2), + .imm(input_imm), + .func(input_func), + .en_jmp(input_en_jmp), + .en_uncond_jmp(input_en_uncond_jmp), + .en_imm(en_imm), + .en_reg_wr(input_en_reg_wr), + .en_mem_wr(input_en_mem_wr), + .en_mem_re(input_en_mem_re), + .en_rel_reg_jmp(input_en_rel_reg_jmp), + .ld_code(input_ld_code), + .instr(instr)); + + assign a2_hazard = {5{~squash}} & input_a2; + always @(*) begin + // Determine which value to use for the second value in the ALU operation + if (en_imm) + alu_input_data2 <= input_imm; + else + alu_input_data2 <= d1; + end + +endmodule diff --git a/src/decode_logic.sv b/src/decode_logic.sv new file mode 100644 index 0000000..9310d56 --- /dev/null +++ b/src/decode_logic.sv @@ -0,0 +1,185 @@ + +module decode_logic( + `include "proc_params.h" + output [`REG_BITS-1:0] a0, + output [`REG_BITS-1:0] a1, + output [`REG_BITS-1:0] a2, + output reg [31:0] imm, + output [`FUNC1_BITS+`FUNC2_BITS-1:0] func, + output reg en_jmp, + output reg en_uncond_jmp, + output reg en_imm, + output reg en_reg_wr, + output reg en_mem_wr, + output reg en_mem_re, + output reg en_rel_reg_jmp, + output reg [2:0] ld_code, + input [31:0] instr); + + reg [2:0] imm_pos; + reg en_alu_str_func; + + wire [31:0] fu_imm; + wire [31:0] fi_imm; + wire [31:0] fs_imm; + wire [31:0] fb_imm; + wire [31:0] fj_imm; + + assign a0 = instr[`OPCODE_SIZE + 2*`REG_BITS + `FUNC1_BITS - 1:`OPCODE_SIZE + `REG_BITS + `FUNC1_BITS]; + assign a1 = instr[`OPCODE_SIZE + 3*`REG_BITS + `FUNC1_BITS - 1:`OPCODE_SIZE + 2*`REG_BITS + `FUNC1_BITS]; + assign a2 = instr[`OPCODE_SIZE + `REG_BITS - 1:`OPCODE_SIZE]; + assign func = {`FUNC1_BITS+`FUNC2_BITS{~en_alu_str_func}} & {instr[`OPCODE_SIZE + 3*`REG_BITS + `FUNC1_BITS + `FUNC2_BITS - 1:`OPCODE_SIZE + 3*`REG_BITS + `FUNC1_BITS], instr[`OPCODE_SIZE + `REG_BITS + `FUNC1_BITS - 1:`OPCODE_SIZE + `REG_BITS]}; + + assign fu_imm = {instr[31:12], {12{instr[31]}}}; + assign fi_imm = {{20{instr[31]}}, instr[31:20]}; + assign fs_imm = {{20{instr[31]}}, instr[31:25], instr[11:7]}; + assign fb_imm = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; + assign fj_imm = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; + + always @ (*) begin + case({instr[`OPCODE_SIZE-1:0]}) + `LOAD_UPPER_IMM: begin + imm_pos <= `FORMAT_U; + ld_code <= `IMM_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b0; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + `ADD_UPPER_IMM_PC: begin + imm_pos <= `FORMAT_U; + ld_code <= `PC_PIMM_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b0; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + `JUMP_AND_LINK: begin + imm_pos <= `FORMAT_J; + ld_code <= `PC_LD; + en_jmp <= 1'b1; + en_uncond_jmp <= 1'b1; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b1; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + `JUMP_AND_LINK_REG: begin + imm_pos <= `FORMAT_I; + ld_code <= `PC_LD; + en_jmp <= 1'b1; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b1; + en_imm <= 1'b1; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + `LOAD_OP: begin + imm_pos <= `FORMAT_I; + ld_code <= `MEM_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b1; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b1; + en_alu_str_func <= 1'b1; + end + `STORE_OP: begin + imm_pos <= `FORMAT_S; + ld_code <= `NO_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b1; + en_reg_wr <= 1'b0; + en_mem_wr <= 1'b1; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b1; + end + `BRANCH_OP: begin + imm_pos <= `FORMAT_B; + ld_code <= `NO_LD; + en_jmp <= 1'b1; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b0; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + `IMM_ALU_OP: begin + imm_pos <= `FORMAT_I; + ld_code <= `ALU_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b1; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + `REG_ALU_OP: begin + imm_pos <= `NO_IMM; + ld_code <= `ALU_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b0; + en_reg_wr <= 1'b1; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + default: begin + imm_pos <= `NO_IMM; + ld_code <= `NO_LD; + en_jmp <= 1'b0; + en_uncond_jmp <= 1'b0; + en_rel_reg_jmp <= 1'b0; + en_imm <= 1'b0; + en_reg_wr <= 1'b0; + en_mem_wr <= 1'b0; + en_mem_re <= 1'b0; + en_alu_str_func <= 1'b0; + end + endcase + + case({imm_pos}) + `FORMAT_U: begin + imm <= fu_imm; + end + `FORMAT_I: begin + imm <= fi_imm; + end + `FORMAT_S: begin + imm <= fs_imm; + end + `FORMAT_B: begin + imm <= fb_imm; + end + `FORMAT_J: begin + imm <= fj_imm; + end + default: begin + imm <= fu_imm; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/src/fetch.sv b/src/fetch.sv new file mode 100644 index 0000000..4b4085b --- /dev/null +++ b/src/fetch.sv @@ -0,0 +1,73 @@ +`timescale 1us/100ns + +module fetch ( + output [31:0] curr_addr, // Current Address + output [31:0] oinstr, // Instruction coming out of fetch stage + output [31:0] ocurr_addr_step, // Current address plus four bytes + output [31:0] ocurr_addr_reljmp, // Current address plus relative jump + input [31:0] iinstr, // Instruction coming directly from cache + input jump_taken, // Signal telling whether a jump will be taken or not + input [31:0] addr_rel_reg, // Relative from register jump address + input en_uncond_jmp, // Signal for unconditional jumps + input en_rel_reg_jmp, // Signal for jumps using a register and an immediate + input en_branch, // Signal for a branch to be taken + input en_jmp, // Signal that enables jumps + input [31:0] imm, // The immediate value from the instruction + input stall, // Signal for a full pipeline a stall is occuring + input imem_stall, // Signal for specifcally a stall due to instruction cache + input clk, // Clock + input rst); // Reset + + // Current Address After 4 Byte Step + wire [31:0] curr_addr_step; + // Current Address plus relative jump + wire [31:0] curr_addr_addval; + + // Next Address to be used put onto the cache + reg [31:0] next_addr; + + // Program Counter + pipeline_latch pc [31:0] (.q(curr_addr), .d(next_addr), .stall(stall | imem_stall), .clk(clk), .rst(rst)); + + // Instruction Latch + pipeline_latch instr_latch [31:0] (.q(oinstr), .d(iinstr), .stall(stall), .clk(clk), .rst(rst)); + + // Latch for the current address plus four bytes + wire [31:0] curr_addr_step_conn_latch1; + wire [31:0] curr_addr_step_conn_latch2; + wire [31:0] curr_addr_step_conn_latch3; + pipeline_latch curr_addr_step_latch1 [31:0] (.q(curr_addr_step_conn_latch1), .d(curr_addr_step), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch curr_addr_step_latch2 [31:0] (.q(curr_addr_step_conn_latch2), .d(curr_addr_step_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch curr_addr_step_latch3 [31:0] (.q(curr_addr_step_conn_latch3), .d(curr_addr_step_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch curr_addr_step_latch4 [31:0] (.q(ocurr_addr_step), .d(curr_addr_step_conn_latch3), .stall(stall), .clk(clk), .rst(rst)); + + // Latch for the current address plus the additional value + wire [31:0] curr_addr_addval_conn_latch1; + wire [31:0] curr_addr_addval_conn_latch2; + pipeline_latch curr_addr_addval_latch1 [31:0] (.q(curr_addr_addval_conn_latch1), .d(curr_addr_addval), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch curr_addr_addval_latch2 [31:0] (.q(curr_addr_addval_conn_latch2), .d(curr_addr_addval_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch curr_addr_addval_latch3 [31:0] (.q(ocurr_addr_reljmp), .d(curr_addr_addval_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); + + // Latch for current + wire [31:0] curr_addr_conn_latch1; + wire [31:0] curr_addr_out; + pipeline_latch curr_addr_latch1 [31:0] (.q(curr_addr_conn_latch1), .d(curr_addr), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch curr_addr_latch2 [31:0] (.q(curr_addr_out), .d(curr_addr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); + + assign curr_addr_step = curr_addr + 4; + assign curr_addr_addval = curr_addr_out + imm; + + always @(*) begin + // Determine if a jump is to be taken + if (en_jmp & en_rel_reg_jmp) begin + next_addr <= addr_rel_reg; + end + else if (en_jmp & (en_uncond_jmp | en_branch)) begin + next_addr <= curr_addr_addval; + end + else begin + next_addr <= curr_addr_step; + end + + end +endmodule diff --git a/hazards.v b/src/hazards.sv similarity index 58% rename from hazards.v rename to src/hazards.sv index 562040f..21e5fd6 100644 --- a/hazards.v +++ b/src/hazards.sv @@ -1,32 +1,26 @@ -`include "latch.v" -module hazards_controller(control_hazard, data_hazard, stall, dmem_stall, imem_stall, jump_taken, dmem_ready, imem_ready, dmem_use, a0, a1, a2, clk, rst); - - output wire control_hazard; - output wire data_hazard; - output wire dmem_stall; - output wire imem_stall; - output wire stall; +module hazards_controller( + output control_hazard, // Signal if there is a control hazard + output data_hazard, // Signal if there is a data hazard + input jump_taken, + input [4:0] a0, // 1st register identifier + input [4:0] a1, // 2nd register identifier + input [4:0] a2, // 3rd register identifier + input stall, + input clk, // Clock + input rst); // Reset - input wire jump_taken; - input wire dmem_ready; - input wire imem_ready; - input wire dmem_use; - input wire [4:0] a0; - input wire [4:0] a1; - input wire [4:0] a2; - input wire clk, rst; wire control_hazard_input; wire control_hazard_latch1_conn; - latch control_hazard_latch1 (.q(control_hazard_latch1_conn), .d(control_hazard_input), .stall(stall | data_hazard), .clk(clk), .rst(rst)); - + pipeline_latch control_hazard_latch1 (.q(control_hazard_latch1_conn), .d(control_hazard_input), .stall(stall | data_hazard), .clk(clk), .rst(rst)); + wire [4:0] a2_latch1_conn; wire a1_equal_a2_latch1; wire a0_equal_a2_latch1; wire a2_equal_zero_latch1; wire data_hazard_latch1; - latch register_wr_latch1 [4:0] (.q(a2_latch1_conn), .d(a2), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch register_wr_latch1 [4:0] (.q(a2_latch1_conn), .d(a2), .stall(stall), .clk(clk), .rst(rst)); assign a2_equal_zero_latch1 = ~(|(a2_latch1_conn ^ 5'b0)); assign a1_equal_a2_latch1 = ~(|(a2_latch1_conn ^ a1)); assign a0_equal_a2_latch1 = ~(|(a2_latch1_conn ^ a0)); @@ -37,7 +31,7 @@ module hazards_controller(control_hazard, data_hazard, stall, dmem_stall, imem_s wire a0_equal_a2_latch2; wire a2_equal_zero_latch2; wire data_hazard_latch2; - latch register_wr_latch2 [4:0] (.q(a2_latch2_conn), .d(a2_latch1_conn), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch register_wr_latch2 [4:0] (.q(a2_latch2_conn), .d(a2_latch1_conn), .stall(stall), .clk(clk), .rst(rst)); assign a2_equal_zero_latch2 = ~(|(a2_latch2_conn ^ 5'b0)); assign a1_equal_a2_latch2 = ~(|(a2_latch2_conn ^ a1)); assign a0_equal_a2_latch2 = ~(|(a2_latch2_conn ^ a0)); @@ -48,7 +42,7 @@ module hazards_controller(control_hazard, data_hazard, stall, dmem_stall, imem_s wire a0_equal_a2_latch3; wire a2_equal_zero_latch3; wire data_hazard_latch3; - latch register_wr_latch3 [4:0] (.q(a2_latch3_conn), .d(a2_latch2_conn), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch register_wr_latch3 [4:0] (.q(a2_latch3_conn), .d(a2_latch2_conn), .stall(stall), .clk(clk), .rst(rst)); assign a2_equal_zero_latch3 = ~(|(a2_latch3_conn ^ 5'b0)); assign a1_equal_a2_latch3 = ~(|(a2_latch3_conn ^ a1)); assign a0_equal_a2_latch3 = ~(|(a2_latch3_conn ^ a0)); @@ -58,7 +52,4 @@ module hazards_controller(control_hazard, data_hazard, stall, dmem_stall, imem_s assign data_hazard = (data_hazard_latch1 | data_hazard_latch2 | data_hazard_latch3) & ~control_hazard; assign control_hazard = control_hazard_input | control_hazard_latch1_conn; - assign imem_stall = ~imem_ready; - assign dmem_stall = ~dmem_ready & dmem_use; - assign stall = dmem_stall | (imem_stall & ~dmem_use & jump_taken); endmodule \ No newline at end of file diff --git a/src/latch.sv b/src/latch.sv new file mode 100644 index 0000000..5346b00 --- /dev/null +++ b/src/latch.sv @@ -0,0 +1,18 @@ +`timescale 1us/100ns + +module pipeline_latch ( + output q, + input d, + input stall, + input clk, + input rst); + + reg state; + + assign #(1) q = state; + + always @(posedge clk) begin + state = rst? 0 : (stall ? q : d); + end + +endmodule diff --git a/src/left_barrel_shifter.sv b/src/left_barrel_shifter.sv new file mode 100644 index 0000000..70af759 --- /dev/null +++ b/src/left_barrel_shifter.sv @@ -0,0 +1,113 @@ + +`timescale 1us/100ns + +module left_barrel_shifter( + input [31:0] idata, + output reg [31:0] odata, + input [4:0] shift_len); + + always @ (*) + case({shift_len}) + 5'd0: begin + odata = idata; + end + 5'd1: begin + odata[31:0] = {idata[30:0], 1'b0}; + end + 5'd2: begin + odata[31:0] = {idata[29:0], 2'b0}; + end + 5'd3: begin + odata[31:0] = {idata[28:0], 3'b0}; + end + 5'd4: begin + odata[31:0] = {idata[27:0], 4'b0}; + end + 5'd5: begin + odata[31:0] = {idata[26:0], 5'b0}; + end + 5'd6: begin + odata[31:0] = {idata[25:0], 6'b0}; + end + 5'd7: begin + odata[31:0] = {idata[24:0], 7'b0}; + end + 5'd8: begin + odata[31:0] = {idata[23:0], 8'b0}; + end + 5'd9: begin + odata[31:0] = {idata[22:0], 9'b0}; + end + 5'd10: begin + odata[31:0] = {idata[21:0], 10'b0}; + end + 5'd11: begin + odata[31:0] = {idata[20:0], 11'b0}; + end + 5'd12: begin + odata[31:0] = {idata[19:0], 12'b0}; + end + 5'd13: begin + odata[31:0] = {idata[18:0], 13'b0}; + end + 5'd14: begin + odata[31:0] = {idata[17:0], 14'b0}; + end + 5'd15: begin + odata[31:0] = {idata[16:0], 15'b0}; + end + 5'd16: begin + odata[31:0] = {idata[15:0], 16'b0}; + end + 5'd17: begin + odata[31:0] = {idata[14:0], 17'b0}; + end + 5'd18: begin + odata[31:0] = {idata[13:0], 18'b0}; + end + 5'd19: begin + odata[31:0] = {idata[12:0], 19'b0}; + end + 5'd20: begin + odata[31:0] = {idata[11:0], 20'b0}; + end + 5'd21: begin + odata[31:0] = {idata[10:0], 21'b0}; + end + 5'd22: begin + odata[31:0] = {idata[9:0], 22'b0}; + end + 5'd23: begin + odata[31:0] = {idata[8:0], 23'b0}; + end + 5'd24: begin + odata[31:0] = {idata[7:0], 24'b0}; + end + 5'd25: begin + odata[31:0] = {idata[6:0], 25'b0}; + end + 5'd26: begin + odata[31:0] = {idata[5:0], 26'b0}; + end + 5'd27: begin + odata[31:0] = {idata[4:0], 27'b0}; + end + 5'd28: begin + odata[31:0] = {idata[3:0], 28'b0}; + end + 5'd29: begin + odata[31:0] = {idata[2:0], 29'b0}; + end + 5'd30: begin + odata[31:0] = {idata[1:0], 30'b0}; + end + 5'd31: begin + odata[31:0] = {idata[0], 31'b0}; + end + default: begin + odata[31:0] = {32'b0}; + end + endcase + +endmodule + \ No newline at end of file diff --git a/src/memory_map.sv b/src/memory_map.sv new file mode 100644 index 0000000..8bc1c70 --- /dev/null +++ b/src/memory_map.sv @@ -0,0 +1,56 @@ + +module memory_map( + input [31:0] imem_addr, + input [31:0] dmem_addr, + output reg imem_cache_enable, + output reg dmem_cache_enable, + output reg imem_valid_addr, + output reg dmem_valid_addr +); + wire [9:0] imem_tag; + wire [9:0] dmem_tag; + + assign imem_tag = imem_addr[31:22]; + assign dmem_tag = dmem_addr[31:22]; + + always @ (*) begin + case(imem_tag) + 10'h0: begin + imem_cache_enable <= 1'b1; + imem_valid_addr <= 1'b1; + end + 10'h1: begin + imem_cache_enable <= 1'b0; + imem_valid_addr <= 1'b1; + end + 10'h2: begin + imem_cache_enable <= 1'b1; + imem_valid_addr <= 1'b1; + end + default: begin + imem_cache_enable <= 1'b0; + imem_valid_addr <= 1'b0; + end + endcase + + case(dmem_tag) + 10'h0: begin + dmem_cache_enable <= 1'b1; + dmem_valid_addr <= 1'b1; + end + 10'h1: begin + dmem_cache_enable <= 1'b0; + dmem_valid_addr <= 1'b1; + end + 10'h2: begin + dmem_cache_enable <= 1'b1; + dmem_valid_addr <= 1'b1; + end + default: begin + dmem_cache_enable <= 1'b0; + dmem_valid_addr <= 1'b0; + end + endcase + end + +endmodule \ No newline at end of file diff --git a/src/memory_system.sv b/src/memory_system.sv new file mode 100644 index 0000000..fbb3736 --- /dev/null +++ b/src/memory_system.sv @@ -0,0 +1,239 @@ +`timescale 1us/100ns + +`define IMEM_OP 2'b01 +`define DMEM_OP 2'b10 + +module memory_system #(parameter WORD_SIZE = 32) + (output reg [WORD_SIZE-1:0] imem_data_out, + output [WORD_SIZE-1:0] dmem_data_out, + input [WORD_SIZE-1:0] dmem_data_in, + input [WORD_SIZE-1:0] data_out, + output reg [WORD_SIZE-1:0] data_in, + output imem_stall, + output dmem_stall, + output stall, + output first_stage_stall, + output squash, + input mem_ready, + input jump_taken, + input [31:0] imem_addr, + input [31:0] dmem_addr, + output reg [31:0] mem_addr, + input en_mem_re, + input en_mem_wr, + output reg en_ext_mem_re, + output reg en_ext_mem_wr, + input data_hazard, + input control_hazard, + input clk, + input rst); + + wire imem_valid_addr; + wire dmem_valid_addr; + wire dmem_op; + + wire [WORD_SIZE-1:0] dmem_data; + reg [WORD_SIZE-1:0] input_dmem_data_out; + reg [31:0] dmem_addr_out; + wire [WORD_SIZE-1:0] data_from_dmem_cache; + wire [31:0] dmem_ext_addr_cache; + wire dmem_ext_re_cache; + wire dmem_ext_wr_cache; + reg dmem_ext_mem_ready; + wire dmem_enable_cache; + wire dmem_cache_miss_stall; + reg dmem_ready; + wire dmem_re_en; + wire dmem_wr_en; + reg dmem_ext_re; + reg dmem_ext_wr; + reg dmem_ext_mem_op; + + wire [WORD_SIZE-1:0] imem_data; + reg [31:0] imem_addr_out; + wire [WORD_SIZE-1:0] data_from_imem_cache; + wire [31:0] imem_ext_addr_cache; + wire imem_ext_re_cache; + wire imem_ext_wr_cache; + reg imem_ext_mem_ready; + wire imem_enable_cache; + wire imem_cache_miss_stall; + reg imem_ready; + wire imem_re_en; + wire imem_wr_en; + reg imem_ext_re; + reg imem_ext_wr; + reg imem_ext_mem_op; + + wire full_imem_stall; + + // Incoming read and write signals are always on for dmem operations except it is an invalid address + assign dmem_re_en = en_mem_re; + assign dmem_wr_en = en_mem_wr; + // You know it is a dmem operation if there is a read or write signal, if it is not a dmem op, then it is implied that it is an imem op + assign dmem_op = dmem_re_en | dmem_wr_en; + + // Imem will always read unless it is an invalid address and never write + assign imem_re_en = 1'b1; + assign imem_wr_en = 1'b0; + + assign full_imem_stall = imem_stall & ~dmem_ext_mem_op & jump_taken; // Full pipeline stall for the icache if there is not a miss in the dcache and jump is going to be taken + assign imem_stall = ~imem_ready & ~control_hazard & imem_valid_addr; + assign dmem_stall = ~dmem_ready & dmem_valid_addr; + assign stall = dmem_stall | full_imem_stall; + assign first_stage_stall = stall | data_hazard | (imem_stall & control_hazard); + + assign squash = data_hazard | control_hazard; + + pipeline_latch dmem_data_output_latch [31:0] (.q(dmem_data_out), .d(input_dmem_data_out), .stall(stall), .clk(clk), .rst(rst)); + + write_through_cache imem_cache + (.data_out(imem_data), + .data_in({WORD_SIZE{1'b0}}), + .addr(imem_addr), + .wr(imem_wr_en), + .re(imem_re_en), + .enable(imem_enable_cache), + .cache_miss_stall(imem_cache_miss_stall), + .ext_data_out(data_from_imem_cache), + .ext_data_in(data_out), + .ext_addr(imem_ext_addr_cache), + .ext_wr(imem_ext_wr_cache), + .ext_re(imem_ext_re_cache), + .ext_ack(imem_ext_mem_ready), + .clk(clk), + .rst(rst)); + + write_through_cache dmem_cache + (.data_out(dmem_data), + .data_in(dmem_data_in), + .addr(dmem_addr), + .wr(dmem_wr_en), + .re(dmem_re_en), + .enable(dmem_enable_cache), + .cache_miss_stall(dmem_cache_miss_stall), + .ext_data_out(data_from_dmem_cache), + .ext_data_in(data_out), + .ext_addr(dmem_ext_addr_cache), + .ext_wr(dmem_ext_wr_cache), + .ext_re(dmem_ext_re_cache), + .ext_ack(dmem_ext_mem_ready), + .clk(clk), + .rst(rst)); + + memory_map mm ( + .imem_addr(imem_addr), + .dmem_addr(dmem_addr), + .imem_cache_enable(imem_enable_cache), + .dmem_cache_enable(dmem_enable_cache), + .imem_valid_addr(imem_valid_addr), + .dmem_valid_addr(dmem_valid_addr) + ); + + reg [1:0] state; + reg [1:0] next_state; + + always @(posedge clk or posedge rst) + begin + if(rst) + state <= #1 `IMEM_OP; + else + state <= #1 next_state; + end + + always @(state or dmem_ready or imem_ready or dmem_op) begin + case(state) + `DMEM_OP: + if (dmem_ready) begin // If stall finished during a dmem operation, operation is said to be finished + next_state <= `IMEM_OP; + end + else begin + next_state <= `DMEM_OP; + end + `IMEM_OP: + if (dmem_op & dmem_valid_addr) begin + next_state <= `DMEM_OP; + end + else begin + next_state <= `IMEM_OP; + end + endcase + end + + always @(*) + begin + case(state) + `DMEM_OP: + begin + mem_addr <= #1 dmem_addr_out; + en_ext_mem_re <= #1 dmem_ext_re; + en_ext_mem_wr <= #1 dmem_ext_wr; + imem_ext_mem_ready <= #1 1'b0; + dmem_ext_mem_ready <= #1 mem_ready; + imem_ext_mem_op <= #1 1'b0; + dmem_ext_mem_op <= #1 1'b1; + end + `IMEM_OP: + begin + mem_addr <= #1 imem_addr_out; + en_ext_mem_re <= #1 imem_ext_re; + en_ext_mem_wr <= #1 imem_ext_wr; + imem_ext_mem_ready <= #1 mem_ready; + dmem_ext_mem_ready <= #1 1'b0; + imem_ext_mem_op <= #1 1'b1; + dmem_ext_mem_op <= #1 1'b0; + end + endcase + + if (rst & imem_valid_addr) begin + imem_data_out <= {WORD_SIZE{1'b0}}; + imem_addr_out <= 32'b0; + imem_ready <= 1'b1; + imem_ext_re <= 1'b0; + imem_ext_wr <= 1'b0; + end + else begin + if (imem_enable_cache) begin + imem_data_out <= imem_data; + imem_addr_out <= imem_ext_addr_cache; + imem_ready <= ~imem_cache_miss_stall; + imem_ext_re <= imem_ext_re_cache; + imem_ext_wr <= imem_ext_wr_cache; + end + else begin + imem_data_out <= data_out & {32{mem_ready & (imem_re_en | imem_wr_en)}}; + imem_addr_out <= imem_addr; + imem_ready <= imem_ext_mem_ready; + imem_ext_re <= imem_re_en; + imem_ext_wr <= imem_wr_en; + end + end + + if (rst & dmem_valid_addr) begin + data_in <= {WORD_SIZE{1'b0}}; + input_dmem_data_out <= {WORD_SIZE{1'b0}}; + dmem_addr_out <= 32'b0; + dmem_ready <= 1'b1; + dmem_ext_re <= 1'b0; + dmem_ext_wr <= 1'b0; + end + else begin + if (dmem_enable_cache) begin + data_in <= data_from_dmem_cache; + input_dmem_data_out <= dmem_data; + dmem_addr_out <= dmem_ext_addr_cache; + dmem_ready <= ~dmem_cache_miss_stall; + dmem_ext_re <= dmem_ext_re_cache; + dmem_ext_wr <= dmem_ext_wr_cache; + end + else begin + data_in <= dmem_data_in; + input_dmem_data_out <= data_out & {32{mem_ready & (dmem_re_en | dmem_wr_en)}}; + dmem_addr_out <= dmem_addr; + dmem_ready <= dmem_ext_mem_ready; + dmem_ext_re <= dmem_re_en; + dmem_ext_wr <= dmem_wr_en; + end + end + end +endmodule \ No newline at end of file diff --git a/src/proc.sv b/src/proc.sv new file mode 100644 index 0000000..45c9876 --- /dev/null +++ b/src/proc.sv @@ -0,0 +1,205 @@ +`timescale 1us/100ns + +module proc(input [31:0] data_out, + output [31:0] data_in, + output [31:0] addr, + output omem_wr, + output omem_re, + input mem_ready, + input clk, + input rst); + + `include "proc_params.h" + + // Intruction + wire [31:0] instr; + // Output from ALU operation + wire [31:0] ialu_odata; + // Data to be written to a register + reg [31:0] data_to_reg; + + // Register Numbers + wire [4:0] a0; + wire [4:0] a1; + wire [4:0] a2; + wire [4:0] a2_hazard; + // Output data from register file + wire [31:0] d0; + wire [31:0] d1; + // Data to be used in ALU comutation + wire [31:0] alu_data1; + wire [31:0] alu_data2; + // Immediate Value (if there is one) + wire [31:0] imm_to_reg; + wire [31:0] imm_to_addr; + // Function Value (if there is one) + wire [9:0] func; + + // Stall from data memory + wire dmem_stall; + // Stall from instruction memory + wire imem_stall; + // Enables if a jump can be taken + wire en_jmp; + // Enables unconditional jumps + wire en_uncond_jmp; + // Enables unconditional jump relative to value in a register + wire en_rel_reg_jmp; + // Enables if a branch is going to be be taken or not + wire en_branch; + // Enables a write to the register + wire en_reg_wr; + // Value that determines which value is put on the register write bus + wire [2:0] ld_code; + + wire [31:0] curr_addr_step; + wire [31:0] curr_addr_addval; + wire stall; + wire first_stage_stall; + wire jump_taken; + wire control_hazard; + wire data_hazard; + wire squash; + + wire [31:0] imem_data_out; + wire [31:0] imem_addr; + wire imem_ready; + wire [31:0] dmem_data_out; + wire [31:0] dmem_addr; + wire dmem_ready; + wire mem_wr; + wire mem_re; + + wire [31:0] data_to_cache; + + memory_system ms (.imem_data_out(imem_data_out), + .dmem_data_out(dmem_data_out), + .dmem_data_in(data_to_cache), + .data_out(data_out), + .data_in(data_in), + .imem_stall(imem_stall), + .dmem_stall(dmem_stall), + .stall(stall), + .first_stage_stall(first_stage_stall), + .squash(squash), + .mem_ready(mem_ready), + .jump_taken(jump_taken), + .imem_addr(imem_addr), + .dmem_addr(dmem_addr), + .mem_addr(addr), + .en_mem_re(mem_re), + .en_mem_wr(mem_wr), + .en_ext_mem_re(omem_re), + .en_ext_mem_wr(omem_wr), + .data_hazard(data_hazard), + .control_hazard(control_hazard), + .clk(clk), + .rst(rst)); + + hazards_controller hazards(.control_hazard(control_hazard), + .data_hazard(data_hazard), + .jump_taken(jump_taken), + .a0(a0), + .a1(a1), + .a2(a2_hazard), + .stall(stall), + .clk(clk), + .rst(rst)); + + // Fetch Stage + fetch fet (.curr_addr(imem_addr), + .oinstr(instr), + .ocurr_addr_step(curr_addr_step), + .ocurr_addr_reljmp(curr_addr_addval), + .iinstr(imem_data_out), + .jump_taken(jump_taken), + .addr_rel_reg(ialu_odata), + .en_uncond_jmp(en_uncond_jmp), + .en_rel_reg_jmp(en_rel_reg_jmp), + .en_branch(en_branch), + .en_jmp(en_jmp), + .imm(imm_to_addr), + .stall(first_stage_stall), + .imem_stall(imem_stall), + .clk(clk), + .rst(rst)); + + // Decode Stage + decode_register_select drs(.a0(a0), + .a1(a1), + .a2(a2), + .a2_hazard(a2_hazard), + .imm_to_reg(imm_to_reg), + .imm_to_addr(imm_to_addr), + .func(func), + .en_jmp(en_jmp), + .en_uncond_jmp(en_uncond_jmp), + .en_rel_reg_jmp(en_rel_reg_jmp), + .en_mem_wr(mem_wr), + .en_mem_re(mem_re), + .ld_code(ld_code), + .alu_data1(alu_data1), + .alu_data2(alu_data2), + .data_to_mem(data_to_cache), + .en_reg_wr(en_reg_wr), + .instr(instr), + .d0(d0), + .d1(d1), + .stall(stall), + .squash(squash), + .clk(clk), + .rst(rst)); + + // ALU + alu a(.data1(alu_data1), + .data2(alu_data2), + .func(func), + .odata(ialu_odata), + .compare_val(en_branch)); + + // Register File + reg_file regs (.a0(a0), + .a1(a1), + .a2(a2), + .din(data_to_reg), + .reg_wr(en_reg_wr), + .d0(d0), + .d1(d1), + .clk(clk), + .rst(rst)); + + wire [31:0] alu_odata_as_addr; + wire [31:0] alu_odata_to_reg; + pipeline_latch alu_output_data_latch1 [31:0] (.q(alu_odata_as_addr), .d(ialu_odata), .stall(stall), .clk(clk), .rst(rst)); + pipeline_latch alu_output_data_latch2 [31:0] (.q(alu_odata_to_reg), .d(alu_odata_as_addr), .stall(stall), .clk(clk), .rst(rst)); + + assign dmem_addr = alu_odata_as_addr; + + assign jump_taken = (en_jmp) & (en_rel_reg_jmp | en_uncond_jmp | en_branch); + + always @(*) begin + + // Mux to Determine Register Write Back + case({ld_code}) + `ALU_LD: begin + data_to_reg <= alu_odata_to_reg; + end + `MEM_LD: begin + data_to_reg <= dmem_data_out; + end + `IMM_LD: begin + data_to_reg <= imm_to_reg; + end + `PC_LD: begin + data_to_reg <= curr_addr_step; + end + `PC_PIMM_LD: begin + data_to_reg <= curr_addr_addval; + end + default: begin + data_to_reg <= curr_addr_step; + end + endcase + end +endmodule + \ No newline at end of file diff --git a/proc_params.h b/src/proc_params.h similarity index 100% rename from proc_params.h rename to src/proc_params.h diff --git a/reg_dff.v b/src/reg_dff.sv similarity index 63% rename from reg_dff.v rename to src/reg_dff.sv index b40c9fc..b359a58 100644 --- a/reg_dff.v +++ b/src/reg_dff.sv @@ -3,12 +3,14 @@ module reg_dflop (q, d, we, clk, rst); - output q; - input d; - input we; - input clk; - input rst; + output wire q; + input wire d; + input wire we; + input wire clk; + input wire rst; + wire dd; + reg state; assign #(1) q = state; diff --git a/reg_file.v b/src/reg_file.sv similarity index 99% rename from reg_file.v rename to src/reg_file.sv index 82abe95..cdef056 100644 --- a/reg_file.v +++ b/src/reg_file.sv @@ -1,6 +1,4 @@ -`include "reg_dff.v" - `define REG_BITS 5 `define OPCODE_SIZE 7 `define REG_NUM 32 diff --git a/src/right_barrel_shifter.sv b/src/right_barrel_shifter.sv new file mode 100644 index 0000000..98a0e89 --- /dev/null +++ b/src/right_barrel_shifter.sv @@ -0,0 +1,117 @@ +`timescale 1us/100ns + +module right_barrel_shifter( + input [31:0] idata, + output reg [31:0] odata, + input [4:0] shift_len, + input arithmetic); + + wire shift_bit; + + assign shift_bit = arithmetic & idata[31]; + + always @ (*) + case({shift_len}) + 5'd0: begin + odata = idata; + end + 5'd1: begin + odata[31:0] = {{1{shift_bit}}, idata[31:1]}; + end + 5'd2: begin + odata[31:0] = {{2{shift_bit}}, idata[31:2]}; + end + 5'd3: begin + odata[31:0] = {{3{shift_bit}}, idata[31:3]}; + end + 5'd4: begin + odata[31:0] = {{4{shift_bit}}, idata[31:4]}; + end + 5'd5: begin + odata[31:0] = {{5{shift_bit}}, idata[31:5]}; + end + 5'd6: begin + odata[31:0] = {{6{shift_bit}}, idata[31:6]}; + end + 5'd7: begin + odata[31:0] = {{7{shift_bit}}, idata[31:7]}; + end + 5'd8: begin + odata[31:0] = {{8{shift_bit}}, idata[31:8]}; + end + 5'd9: begin + odata[31:0] = {{9{shift_bit}}, idata[31:9]}; + end + 5'd10: begin + odata[31:0] = {{10{shift_bit}}, idata[31:10]}; + end + 5'd11: begin + odata[31:0] = {{11{shift_bit}}, idata[31:11]}; + end + 5'd12: begin + odata[31:0] = {{12{shift_bit}}, idata[31:12]}; + end + 5'd13: begin + odata[31:0] = {{13{shift_bit}}, idata[31:13]}; + end + 5'd14: begin + odata[31:0] = {{14{shift_bit}}, idata[31:14]}; + end + 5'd15: begin + odata[31:0] = {{15{shift_bit}}, idata[31:15]}; + end + 5'd16: begin + odata[31:0] = {{16{shift_bit}}, idata[31:16]}; + end + 5'd17: begin + odata[31:0] = {{17{shift_bit}}, idata[31:17]}; + end + 5'd18: begin + odata[31:0] = {{18{shift_bit}}, idata[31:18]}; + end + 5'd19: begin + odata[31:0] = {{19{shift_bit}}, idata[31:19]}; + end + 5'd20: begin + odata[31:0] = {{20{shift_bit}}, idata[31:20]}; + end + 5'd21: begin + odata[31:0] = {{21{shift_bit}}, idata[31:21]}; + end + 5'd22: begin + odata[31:0] = {{22{shift_bit}}, idata[31:22]}; + end + 5'd23: begin + odata[31:0] = {{23{shift_bit}}, idata[31:23]}; + end + 5'd24: begin + odata[31:0] = {{24{shift_bit}}, idata[31:24]}; + end + 5'd25: begin + odata[31:0] = {{25{shift_bit}}, idata[31:25]}; + end + 5'd26: begin + odata[31:0] = {{26{shift_bit}}, idata[31:26]}; + end + 5'd27: begin + odata[31:0] = {{27{shift_bit}}, idata[31:27]}; + end + 5'd28: begin + odata[31:0] = {{28{shift_bit}}, idata[31:28]}; + end + 5'd29: begin + odata[31:0] = {{29{shift_bit}}, idata[31:29]}; + end + 5'd30: begin + odata[31:0] = {{30{shift_bit}}, idata[31:30]}; + end + 5'd31: begin + odata[31:0] = {{31{shift_bit}}, idata[31]}; + end + default: begin + odata[31:0] = {{32{shift_bit}}}; + end + endcase + +endmodule + \ No newline at end of file diff --git a/src/risc_de10.sv b/src/risc_de10.sv new file mode 100644 index 0000000..e504384 --- /dev/null +++ b/src/risc_de10.sv @@ -0,0 +1,152 @@ + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +module risc_de10#(parameter INIT_PROGRAM = "./tests/hex/risc_test.hex") +( + + //////////// CLOCK ////////// + input ADC_CLK_10, + input MAX10_CLK1_50, + input MAX10_CLK2_50, + + //////////// SDRAM ////////// + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, + + //////////// KEY ////////// + input [1:0] KEY, + + //////////// LED ////////// + output [9:0] LEDR, + + //////////// VGA ////////// + output [3:0] VGA_B, + output [3:0] VGA_G, + output VGA_HS, + output [3:0] VGA_R, + output VGA_VS, + + //////////// GPIO, GPIO connect to GPIO Default ////////// + inout [35:0] GPIO +); + + + +//======================================================= +// REG/WIRE declarations +//======================================================= + wire clk; + wire rst; + + // Data from main memory from processor + wire [31:0] data_out; + // Data going directly into main memory + wire [31:0] data_in; + // Address going into the main memory + wire [31:0] addr; + // Write flag going into main memory + wire mem_wr; + // Read flag for data main memory + wire mem_re; + // Ready to read status for instruction main memory + wire mem_ready; + wire write_finished; + wire read_finished; + wire in_use; + wire en_sdram; + wire en_peripherals; + wire en_sram; + wire [31:0] periph_data; + wire [31:0] sdram_data; + wire [31:0] sram_data; + wire sram_ready; + wire sdram_ready; + +//======================================================= +// Structural coding +//======================================================= + assign rst = ~(KEY[0] & KEY[1]); + assign clk = MAX10_CLK1_50; + + // Processor + proc cpu (.data_out(data_out), .data_in(data_in), .addr(addr), .omem_wr(mem_wr), .omem_re(mem_re), .mem_ready(mem_ready), + .clk(clk), .rst(rst)); + + de10_bus_controller bus_controller (.addr(addr), + .sram_data(sram_data), + .sdram_data(sdram_data), + .peripheral_data(periph_data), + .sram_ready(sram_ready), + .sdram_ready(sdram_ready), + .peripheral_ready(1'b1), + .oen_sram(en_sram), + .oen_sdram(en_sdram), + .oen_peripherals(en_peripherals), + .odata(data_out), + .omem_ready(mem_ready), + .clk(clk), + .rst(rst)); + + sram #( + .INIT_PROGRAM(INIT_PROGRAM) + ) sr (.data(data_in), + .oq(sram_data), + .omem_ready(sram_ready), + .be(4'b1111), + .addr(addr[15:2]), + .we(mem_wr & en_sram), + .re(mem_re & en_sram), + .clk(clk), + .rst(rst)); + + de10_peripherals periph (.addr(addr), + .wr(mem_wr & en_peripherals), + .idata(data_in), + .odata(periph_data), + .clk(clk), + .rst(rst), + .LEDR(LEDR), + .GPIO(GPIO) + ); + + sdram_controller sdram_controller( + .iclk(clk), + .ireset(rst), + .omem_ready(sdram_ready), + + .iwrite_req(mem_wr & en_sdram), + .iwrite_address(addr[21:0]), + .iwrite_data(data_in), + .owrite_ack(write_finished), + + .iread_req(mem_re & en_sdram), + .iread_address(addr[21:0]), + .oread_data(sdram_data), + .oread_ack(read_finished), + + //////////// SDRAM ////////// + .DRAM_ADDR(DRAM_ADDR), + .DRAM_BA(DRAM_BA), + .DRAM_CAS_N(DRAM_CAS_N), + .DRAM_CKE(DRAM_CKE), + .DRAM_CLK(DRAM_CLK), + .DRAM_CS_N(DRAM_CS_N), + .DRAM_DQ(DRAM_DQ), + .DRAM_LDQM(DRAM_LDQM), + .DRAM_RAS_N(DRAM_RAS_N), + .DRAM_UDQM(DRAM_UDQM), + .DRAM_WE_N(DRAM_WE_N) + ); + +endmodule diff --git a/src/sdram_controller.h b/src/sdram_controller.h new file mode 100644 index 0000000..7e0471d --- /dev/null +++ b/src/sdram_controller.h @@ -0,0 +1,14 @@ +`define DSIZE_DB_WIDTH 2 +`define DB_WIDTH 16 +`define DATA_BLOCK_SIZE 32 +`define DATA_BLOCK_SIZE_MINUS_WIDTH 16 + +`define INIT1 9'b000000001 +`define INIT2 9'b000000010 +`define IDLE_SC 9'b000000100 +`define WRITE1 9'b000001000 +`define WRITE2 9'b000010000 +`define WRITE3 9'b000100000 +`define READ1 9'b001000000 +`define READ2 9'b010000000 +`define READ3 9'b100000000 \ No newline at end of file diff --git a/src/sdram_controller.sv b/src/sdram_controller.sv new file mode 100644 index 0000000..8886592 --- /dev/null +++ b/src/sdram_controller.sv @@ -0,0 +1,329 @@ +`timescale 1us/100ns + +module sdram_controller( + `include "sdram_controller.h" + + input iclk, + input ireset, + output omem_ready, + + input iwrite_req, + input [21:0] iwrite_address, + input [`DATA_BLOCK_SIZE-1:0] iwrite_data, + output owrite_ack, + + input iread_req, + input [21:0] iread_address, + output [`DATA_BLOCK_SIZE-1:0] oread_data, + output oread_ack, + + //////////// SDRAM ////////// + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [`DB_WIDTH-1:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N +); + +//======================================================= +// REG/WIRE declarations +//======================================================= +reg [8:0] state = `INIT1; +reg [8:0] next_state = `INIT1; +reg [2:0] mul_state = 3'b001; + +reg mem_ready = 1'b1; +reg read_ack = 1'b0; +reg write_ack = 1'b0; + +//SDRAM INITLIZE MODULE +reg init_ireq = 1'b0; +wire init_ienb; +wire init_fin; + +//SDRAM WRITE MODULE +reg write_ireq = 1'b0; +wire write_ienb; +wire [12:0] write_irow; +wire [9:0] write_icolumn; +wire [1:0] write_ibank; +wire write_fin; + +//SDRAM READ MODULE +reg read_ireq = 1'b0; +wire read_ienb; +wire [12:0] read_irow; +wire [9:0] read_icolumn; +wire [1:0] read_ibank; +wire read_fin; + + +//======================================================= +// Structural coding +//======================================================= +assign {write_ibank, write_irow, write_icolumn} = {iwrite_address, 3'b0}; +assign {read_ibank, read_irow, read_icolumn} = {iread_address, 3'b0}; + +assign omem_ready = mem_ready; +assign owrite_ack = write_ack; +assign oread_ack = read_ack; + +assign {read_ienb, write_ienb, init_ienb} = mul_state; + +always @(posedge iclk) +begin + if(ireset == 1'b1) + state <= #1 `INIT1; + else + state <= #1 next_state; +end + +always @(state or init_fin or iwrite_req or iread_req or write_fin or read_fin) +begin + case(state) + //Init States + `INIT1: + next_state <= `INIT2; + `INIT2: + if(init_fin) + next_state <= `IDLE_SC; + else + next_state <= `INIT2; + + //Idle State + `IDLE_SC: + if(iwrite_req) + next_state <= `WRITE1; + else if(iread_req) + next_state <= `READ1; + else + next_state <= `IDLE_SC; + //Write States + `WRITE1: + next_state <= `WRITE2; + `WRITE2: + if(write_fin) + next_state <= `WRITE3; + else + next_state <= `WRITE2; + `WRITE3: + next_state <= `IDLE_SC; + + //Read States ` + `READ1: + next_state <= `READ2; + `READ2: + if(read_fin) + next_state <= `READ3; + else + next_state <= `READ2; + `READ3: + next_state <= `IDLE_SC; + default: + next_state <= `INIT1; + endcase +end + +always @(state) +begin + case(state) + //Init States + `INIT1: + begin + init_ireq <= 1'b1; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b0; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b001; + end + `INIT2: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b0; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b001; + end + + //Idle State + `IDLE_SC: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b1; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b001; + end + + //Write States + `WRITE1: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b1; + read_ireq <= 1'b0; + + mem_ready <= 1'b0; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b010; + end + + `WRITE2: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b0; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b010; + end + `WRITE3: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b0; + write_ack <= 1'b1; + read_ack <= 1'b0; + + mul_state <= 3'b010; + end + + //Read States + `READ1: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b1; + + mem_ready <= 1'b0; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b100; + end + `READ2: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b1; + write_ack <= 1'b0; + read_ack <= 1'b0; + + mul_state <= 3'b100; + end + `READ3: + begin + init_ireq <= 1'b0; + write_ireq <= 1'b0; + read_ireq <= 1'b0; + + mem_ready <= 1'b0; + write_ack <= 1'b0; + read_ack <= 1'b1; + + mul_state <= 3'b100; + end + endcase +end + +sdram_initalize sdram_init ( + .iclk(iclk), + .ireset(ireset), + + .ireq(init_ireq), + .ienb(init_ienb), + + .ofin(init_fin), + + .DRAM_ADDR(DRAM_ADDR), + .DRAM_BA(DRAM_BA), + .DRAM_CAS_N(DRAM_CAS_N), + .DRAM_CKE(DRAM_CKE), + .DRAM_CLK(DRAM_CLK), + .DRAM_CS_N(DRAM_CS_N), + .DRAM_DQ(DRAM_DQ), + .DRAM_LDQM(DRAM_LDQM), + .DRAM_RAS_N(DRAM_RAS_N), + .DRAM_UDQM(DRAM_UDQM), + .DRAM_WE_N(DRAM_WE_N) +); + +sdram_write sdram_write ( + .iclk(iclk), + .ireset(ireset), + + .ireq(write_ireq), + .ienb(write_ienb), + + .irow(write_irow), + .icolumn(write_icolumn), + .ibank(write_ibank), + .idata(iwrite_data), + .ofin(write_fin), + + .DRAM_ADDR(DRAM_ADDR), + .DRAM_BA(DRAM_BA), + .DRAM_CAS_N(DRAM_CAS_N), + .DRAM_CKE(DRAM_CKE), + .DRAM_CLK(DRAM_CLK), + .DRAM_CS_N(DRAM_CS_N), + .DRAM_DQ(DRAM_DQ), + .DRAM_LDQM(DRAM_LDQM), + .DRAM_RAS_N(DRAM_RAS_N), + .DRAM_UDQM(DRAM_UDQM), + .DRAM_WE_N(DRAM_WE_N) +); + +sdram_read sdram_read ( + .iclk(iclk), + .ireset(ireset), + + .ireq(read_ireq), + .ienb(read_ienb), + + .irow(read_irow), + .icolumn(read_icolumn), + .ibank(read_ibank), + .odata(oread_data), + .ofin(read_fin), + + .DRAM_ADDR(DRAM_ADDR), + .DRAM_BA(DRAM_BA), + .DRAM_CAS_N(DRAM_CAS_N), + .DRAM_CKE(DRAM_CKE), + .DRAM_CLK(DRAM_CLK), + .DRAM_CS_N(DRAM_CS_N), + .DRAM_DQ(DRAM_DQ), + .DRAM_LDQM(DRAM_LDQM), + .DRAM_RAS_N(DRAM_RAS_N), + .DRAM_UDQM(DRAM_UDQM), + .DRAM_WE_N(DRAM_WE_N) +); + +endmodule diff --git a/src/sdram_intialize.sv b/src/sdram_intialize.sv new file mode 100644 index 0000000..5174c13 --- /dev/null +++ b/src/sdram_intialize.sv @@ -0,0 +1,188 @@ +`timescale 1us/100ns + +// SDRAM Settings +// Write Bust -- Single Location +// CAS Latency -- 2 +// Burst -- Sequential +// Burst Length -- 1 +module sdram_initalize( + input iclk, + input ireset, + input ireq, + input ienb, + output ofin, + + output DRAM_CLK, + output DRAM_CKE, + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CS_N, + output DRAM_RAS_N, + output DRAM_WE_N, + output DRAM_LDQM, + output DRAM_UDQM, + output [15:0] DRAM_DQ +); + +reg [7:0] state = 8'b00000001; +reg [7:0] next_state; + +reg [3:0] command = 4'h0; +reg [12:0] address = 13'h0; +reg [1:0] bank = 2'b00; +reg [1:0] dqm = 2'b11; + +reg ready = 1'b0; + +reg [15:0] counter = 16'h0; +reg ctr_reset = 0; + +wire ref_cycles; +wire init_begin_counter; + +assign ofin = ready; + +assign DRAM_ADDR = ienb ? address : 13'bz; +assign DRAM_BA = ienb ? bank : 2'bz; +assign {DRAM_CS_N, DRAM_RAS_N, DRAM_CAS_N, DRAM_WE_N} = ienb ? command : 4'bz; +assign {DRAM_UDQM, DRAM_LDQM} = ienb ? dqm : 2'bz; +assign DRAM_CLK = ienb ? ~iclk : 1'bz; +assign DRAM_CKE = ienb ? 1'b1 : 1'bz; +assign DRAM_DQ = ienb ? 16'h0000 : 16'bz; + +always @(posedge iclk or posedge ctr_reset) +begin + if(ctr_reset) + counter <= #1 16'h0; + else + counter <= #1 (counter + 1'b1); +end + +//ref_cycles > 16 - refresh, nop - 8 times +assign ref_cycles = (counter >= 16); +assign init_begin_counter = (counter >= 10000); +//assign init_begin_counter = (counter >= 12); + +always @(posedge iclk) +begin + if(ireset == 1'b1) + state <= #1 8'b00000001; + else + state <= #1 next_state; +end + +always @(state or ireq or ref_cycles or init_begin_counter) +begin + case(state) + //IDLE + 8'b00000001: + if(ireq) + next_state <= 8'b00000010; + else + next_state <= 8'b00000001; + //NOP - POWER UP + 8'b00000010: + if(init_begin_counter) + next_state <= 8'b00000100; + else + next_state <= 8'b00000010; + 8'b00000100: + next_state <= 8'b00001000; + 8'b00001000: + next_state <= 8'b00010000; + 8'b00010000: + if(ref_cycles) + next_state <= 8'b00100000; + else + next_state <= 8'b00001000; + 8'b00100000: + next_state <= 8'b01000000; + 8'b01000000: + next_state <= 8'b10000000; + 8'b10000000: + next_state <= 8'b10000000; + default: + next_state <= 8'b00000001; + endcase +end + +always @(state) +begin + case(state) + 8'b00000001: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b1; + end + 8'b00000010: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + 8'b00000100: + begin + command <= #1 4'b0010; + address <= #1 13'b0010000000000; + bank <= #1 2'b11; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b1; + end + 8'b00001000: + begin + command <= #1 4'b0001; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + 8'b00010000: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + 8'b00100000: + begin + command <= #1 4'b0000; + bank <= #1 2'b00; + address <= #1 13'b0000000100011; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + 8'b01000000: + begin + command <= #1 4'b0111; + bank <= #1 2'b00; + address <= #1 13'b0000000000000; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + 8'b10000000: + begin + command <= #1 4'b0111; + bank <= #1 2'b00; + address <= #1 13'b0000000000000; + ready <= #1 1'b1; + + ctr_reset <= #1 1'b0; + end + endcase +end + +endmodule diff --git a/src/sdram_read.h b/src/sdram_read.h new file mode 100644 index 0000000..9860900 --- /dev/null +++ b/src/sdram_read.h @@ -0,0 +1,8 @@ +`define IDLE_READ 8'b00000001 +`define ACTIVE_READ 8'b00000010 +`define NOP 8'b00000100 +`define READ 8'b00001000 +`define CAS1 8'b00010000 +`define CAS2 8'b00100000 +`define READING 8'b01000000 +`define FIN_READ 8'b10000000 \ No newline at end of file diff --git a/src/sdram_read.sv b/src/sdram_read.sv new file mode 100644 index 0000000..68dc22e --- /dev/null +++ b/src/sdram_read.sv @@ -0,0 +1,199 @@ +`timescale 1us/100ns + +module sdram_read( + `include "sdram_controller.h" + input iclk, + input ireset, + input ireq, + input ienb, + output ofin, + + input [12:0] irow, + input [9:0] icolumn, + input [1:0] ibank, + output [`DATA_BLOCK_SIZE-1:0] odata, + + output DRAM_CLK, + output DRAM_CKE, + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CS_N, + output DRAM_RAS_N, + output DRAM_WE_N, + output DRAM_LDQM, + output DRAM_UDQM, + input [`DB_WIDTH-1:0] DRAM_DQ +); + +`include "sdram_read.h" + +reg [7:0] state = `IDLE_READ; +reg [7:0] next_state; + +reg [3:0] command = 4'h0; +reg [12:0] address = 13'h0; +reg [1:0] bank = 2'b00; +reg [`DATA_BLOCK_SIZE-1:0] data = `DATA_BLOCK_SIZE'b0; +reg [1:0] dqm = 2'b11; + +reg ready = 1'b0; + +reg [7:0] counter = 8'h0; +reg ctr_reset = 0; + +wire data_count; + +assign ofin = ready; +assign odata = data; + +assign DRAM_ADDR = ienb ? address : 13'bz; +assign DRAM_BA = ienb ? bank : 2'bz; +assign {DRAM_CS_N, DRAM_RAS_N, DRAM_CAS_N, DRAM_WE_N} = ienb ? command : 4'bz; +assign {DRAM_UDQM, DRAM_LDQM} = ienb ? dqm : 2'bz; +assign DRAM_CLK = ienb ? ~iclk : 1'bz; +assign DRAM_CKE = ienb ? 1'b1 : 1'bz; + +always @(posedge iclk or posedge ctr_reset) +begin + if(ctr_reset) + counter <= #1 8'h0; + else + counter <= #1 (counter + 1'b1); +end + +assign data_count = (counter == `DSIZE_DB_WIDTH); + +always @(posedge iclk) +begin + if(ireset == 1'b1) + state <= #1 `IDLE_READ; + else + state <= #1 next_state; +end + +always @(state or ireq or data_count) +begin + case(state) + `IDLE_READ: + if(ireq) + next_state <= `ACTIVE_READ; + else + next_state <= `IDLE_READ; + `ACTIVE_READ: + next_state <= `NOP; + `NOP: + next_state <= `READ; + `READ: + next_state <= `CAS1; + `CAS1: + next_state <= `CAS2; + `CAS2: + next_state <= `READING; + `READING: + if(data_count) + next_state <= `FIN_READ; + else + next_state <= `READING; + `FIN_READ: + next_state <= `IDLE_READ; + default: + next_state <= `IDLE_READ; + endcase +end + +always @(state) +begin + case(state) + `IDLE_READ: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `ACTIVE_READ: + begin + command <= #1 4'b0011; + address <= #1 irow; + bank <= #1 ibank; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `NOP: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `READ: + begin + command <= #1 4'b0101; + address <= #1 {3'b001, icolumn}; + bank <= #1 ibank; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `CAS1: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b00; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `CAS2: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b00; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b1; + end + `READING: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b00; + data <= #1 ((data << `DB_WIDTH) | {`DATA_BLOCK_SIZE_MINUS_WIDTH'b0, DRAM_DQ}); + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `FIN_READ: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b1; + + ctr_reset <= #1 1'b0; + end + endcase +end + +endmodule diff --git a/src/sdram_write.h b/src/sdram_write.h new file mode 100644 index 0000000..3c97a6b --- /dev/null +++ b/src/sdram_write.h @@ -0,0 +1,7 @@ +`define IDLE_WRITE 7'b0000001 +`define ACTIVE_WRITE 7'b0000010 +`define NOP1 7'b0000100 +`define WRITE 7'b0001000 +`define WRITING 7'b0010000 +`define NOP2 7'b0100000 +`define FIN_WRITE 7'b1000000 \ No newline at end of file diff --git a/src/sdram_write.sv b/src/sdram_write.sv new file mode 100644 index 0000000..b81a987 --- /dev/null +++ b/src/sdram_write.sv @@ -0,0 +1,185 @@ +`timescale 1us/100ns + +module sdram_write( + `include "sdram_controller.h" + input iclk, + input ireset, + input ireq, + input ienb, + output ofin, + + input [12:0] irow, + input [9:0] icolumn, + input [1:0] ibank, + input [`DATA_BLOCK_SIZE-1:0] idata, + + output DRAM_CLK, + output DRAM_CKE, + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CS_N, + output DRAM_RAS_N, + output DRAM_WE_N, + output DRAM_LDQM, + output DRAM_UDQM, + output [`DB_WIDTH-1:0] DRAM_DQ +); +`include "sdram_write.h" + +reg [6:0] state = `IDLE_WRITE; +reg [6:0] next_state; + +reg [3:0] command = 4'h0; +reg [12:0] address = 13'h0; +reg [1:0] bank = 2'b00; +reg [`DATA_BLOCK_SIZE-1:0] data = `DATA_BLOCK_SIZE'b0; +reg [1:0] dqm = 2'b11; + +reg ready = 1'b0; + +reg [7:0] counter = 8'h0; +reg ctr_reset = 0; + +wire data_count; + +assign ofin = ready; + +assign DRAM_ADDR = ienb ? address : 13'bz; +assign DRAM_BA = ienb ? bank : 2'bz; +assign {DRAM_CS_N, DRAM_RAS_N, DRAM_CAS_N, DRAM_WE_N} = ienb ? command : 4'bz; +assign {DRAM_UDQM, DRAM_LDQM} = ienb ? dqm : 2'bz; +assign DRAM_CLK = ienb ? ~iclk : 1'bz; +assign DRAM_CKE = ienb ? 1'b1 : 1'bz; +assign DRAM_DQ = ienb ? data[`DATA_BLOCK_SIZE-1:`DATA_BLOCK_SIZE-`DB_WIDTH-1] : `DB_WIDTH'bz; + +always @(posedge iclk or posedge ctr_reset) +begin + if(ctr_reset) + counter <= #1 8'h0; + else + counter <= #1 (counter + 1'b1); +end + +assign data_count = (counter == 5); + +always @(posedge iclk) +begin + if(ireset == 1'b1) + state <= #1 `IDLE_WRITE; + else + state <= #1 next_state; +end + +always @(state or ireq or data_count) +begin + case(state) + `IDLE_WRITE: + if(ireq) + next_state <= `ACTIVE_WRITE; + else + next_state <= `IDLE_WRITE; + `ACTIVE_WRITE: + next_state <= `NOP1; + `NOP1: + next_state <= `WRITE; + `WRITE: + next_state <= `WRITING; + `WRITING: + if(data_count) + next_state <= `NOP2; + else + next_state <= `WRITING; + `NOP2: + next_state <= `FIN_WRITE; + `FIN_WRITE: + next_state <= `IDLE_WRITE; + default: + next_state <= `IDLE_WRITE; + endcase +end + +always @(posedge iclk) +begin + case(state) + `IDLE_WRITE: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `ACTIVE_WRITE: + begin + command <= #1 4'b0011; + address <= #1 irow; + bank <= #1 ibank; + dqm <= #1 2'b11; + data <= #1 idata; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `NOP1: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b1; + end + `WRITE: + begin + command <= #1 4'b0100; + address <= #1 {3'b001, icolumn}; + bank <= #1 ibank; + dqm <= #1 2'b00; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b1; + end + `WRITING: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b00; + data <= #1 (data << `DB_WIDTH); + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `NOP2: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b0; + + ctr_reset <= #1 1'b0; + end + `FIN_WRITE: + begin + command <= #1 4'b0111; + address <= #1 13'b0000000000000; + bank <= #1 2'b00; + dqm <= #1 2'b11; + data <= #1 data; + ready <= #1 1'b1; + + ctr_reset <= #1 1'b0; + end + endcase +end + +endmodule diff --git a/src/sram.sv b/src/sram.sv new file mode 100644 index 0000000..35017c3 --- /dev/null +++ b/src/sram.sv @@ -0,0 +1,96 @@ +`timescale 1us/100ns + +module sram + #(parameter int ADDR_WIDTH = 14, + parameter int BYTE_WIDTH = 8, + parameter int BYTES = 4, + parameter int WIDTH = BYTES * BYTE_WIDTH, + parameter INIT_PROGRAM = "./tests/hex/risc_test.hex" + ) +( + input [ADDR_WIDTH-1:0] addr, + input [BYTES-1:0] be, + input [WIDTH-1:0] data, + input we, re, clk, rst, + output reg [WIDTH - 1:0] oq, + output omem_ready +); + localparam int WORDS = 1 << ADDR_WIDTH ; + + integer mcd; + integer i; + integer j; + + // use a multi-dimensional packed array to model individual bytes within the word + logic [BYTES-1:0][BYTE_WIDTH-1:0] ram[0:WORDS-1]; + + reg rest; + reg rest_state; + reg [WIDTH - 1:0] q; + + wire mem_transaction; + + assign mem_transaction = we | re; + + // Initializing memory with initalization program + initial + begin : INIT + integer i; + for(i = 0; i < 2**ADDR_WIDTH; i = i + 1) + ram[i] = {WIDTH{1'b1}}; + $readmemh(INIT_PROGRAM, ram); + end + + + // Memory Control Logic + always @(posedge clk) + begin + if (rst) begin + #(1) oq <= {WIDTH{1'b0}}; + end + else begin + #(1) oq <= q & {WIDTH{re}}; + end + end + + always @(posedge clk) + begin + if (rst) begin + rest <= 1'b0; + end + else begin + rest <= ~rest_state & mem_transaction; + end + end + + assign #(1) rest_state = rest; + + // Memory is ready to be read if there are not memory transactions happening or there is no transaction rest + assign omem_ready = ~mem_transaction | ~rest; + + // Memory read/write logic + always_ff@(posedge clk) + begin + if(we) begin + // edit this code if using other than four bytes per word + if(be[0]) ram[addr][0] <= data[BYTE_WIDTH - 1:0]; + if(be[1]) ram[addr][1] <= data[2*BYTE_WIDTH - 1:BYTE_WIDTH]; + if(be[2]) ram[addr][2] <= data[3*BYTE_WIDTH - 1:2*BYTE_WIDTH]; + if(be[3]) ram[addr][3] <= data[4*BYTE_WIDTH - 1:3*BYTE_WIDTH]; + end + q <= ram[addr]; + end + + // synthesis translate_off + always @(posedge clk) + begin + mcd = $fopen("sram_dumpfile", "w"); + for (i=0; i < WORDS*BYTES; i=i+1) begin + for (j=0; j < BYTES; j=j+1) begin + $fdisplay(mcd,"%4h %2h", i*BYTES + j, ram[i][j]); + end + end + $fclose(mcd); + end + // synthesis translate_on +endmodule : sram diff --git a/src/write_through_cache.sv b/src/write_through_cache.sv new file mode 100644 index 0000000..76880ac --- /dev/null +++ b/src/write_through_cache.sv @@ -0,0 +1,118 @@ +`timescale 1us/100ns + +module write_through_cache #(parameter INDEX_BITS = 5, // Index into cache + parameter CACHE_LINES = 2**INDEX_BITS, // Number of cache lines + parameter BLOCK_OFFSET = 6, + parameter DATA_LENGTH = 2**BLOCK_OFFSET, // Cache line length in bytes + parameter TAG_BITS = 32 - INDEX_BITS - BLOCK_OFFSET, + parameter STATUS_BITS = 1, + parameter LINE_LENGTH = TAG_BITS + DATA_LENGTH*8 + STATUS_BITS, + parameter WORD_SIZE = 32, + parameter WORD_BYTES = WORD_SIZE / 8, + parameter WORDS_PER_DATA_BLOCK = DATA_LENGTH / WORD_BYTES) + (output [WORD_SIZE-1:0] data_out, + input [WORD_SIZE-1:0] data_in, + input [31:0] addr, + input wr, + input re, + input enable, + output reg cache_miss_stall, + + output [WORD_SIZE-1:0] ext_data_out, + input [WORD_SIZE-1:0] ext_data_in, + output [31:0] ext_addr, + output ext_wr, + output ext_re, + input ext_ack, + + // Clock and reset + input clk, + input rst); + + + + wire [LINE_LENGTH-1:0] new_line; + wire full_line_wr; + wire hit; + + wire write_miss; + wire read_miss; + + wire wr_ack; + wire re_ack; + + assign write_miss = ~hit & wr & ~re; + assign read_miss = ~hit & ~wr & re; + + cache_miss_controller #( + .BYTES_PER_WORD(WORD_BYTES), + .WORD_SIZE(WORD_SIZE), + .INDEX_BITS(INDEX_BITS), + .CACHE_LINES(CACHE_LINES), + .BLOCK_OFFSET(BLOCK_OFFSET), + .DATA_LENGTH(DATA_LENGTH), + .TAG_BITS(TAG_BITS), + .STATUS_BITS(STATUS_BITS), + .LINE_LENGTH(LINE_LENGTH), + .WORDS_PER_DATA_BLOCK(WORDS_PER_DATA_BLOCK)) + cont (.addr(addr), + .data_from_cache(data_in), + .data_to_cache(new_line), + .ext_data_in(ext_data_in), + .ext_data_out(ext_data_out), + .ext_addr(ext_addr), + .ext_ack(ext_ack), + .ext_re(ext_re), + .ext_wr(ext_wr), + .wr_ack(wr_ack), + .re_ack(re_ack), + .re(read_miss), + .wr(wr), + .full_line_wr(full_line_wr), + .enable(enable), + .clk(clk), + .rst(rst)); + + cache #( + .BYTES_PER_WORD(WORD_BYTES), + .WORD_SIZE(WORD_SIZE), + .INDEX_BITS(INDEX_BITS), + .CACHE_LINES(CACHE_LINES), + .BLOCK_OFFSET(BLOCK_OFFSET), + .DATA_LENGTH(DATA_LENGTH), + .TAG_BITS(TAG_BITS), + .STATUS_BITS(STATUS_BITS), + .LINE_LENGTH(LINE_LENGTH) + ) + cch(.data_out(data_out), + .data_in(data_in), + .new_cache_line(new_line), + .addr(addr), + .full_line_wr(full_line_wr), + .wr(wr), + .re(re), + .enable(enable), + .hit(hit), + .clk(clk), + .rst(rst)); + + always @(rst or enable or wr_ack or re_ack or read_miss or wr) + begin + if(rst | ~enable) // Reset or disabled defaults to no cache miss + cache_miss_stall <= 1'b0; + else begin + if (cache_miss_stall) begin + if (wr_ack | re_ack) begin // If ACK signal recieved from cache controller, not in cache miss stall state anymore + cache_miss_stall <= 1'b0; + end + else begin + cache_miss_stall <= cache_miss_stall; + end + end + else begin // If not in cache miss, check if a read miss happened or if a write through operation needs to happen + cache_miss_stall <= read_miss | wr; + end + end + end + +endmodule \ No newline at end of file diff --git a/test_programs/Makefile b/test_programs/Makefile deleted file mode 100644 index 854ce77..0000000 --- a/test_programs/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -CC := riscv32-unknown-elf-gcc -OBJDUMP := riscv32-unknown-elf-objdump -OBJCOPY := riscv32-unknown-elf-objcopy - -CFLAGS := -O0 -Xlinker -g -Trisc.ld -nostdlib -ffreestanding -fno-pie -fno-stack-protector -Wall -mno-fdiv -march=rv32i -mabi=ilp32 - -all: - $(CC) $(CFLAGS) risc_test.c start.s -o risc_test - $(CC) $(CFLAGS) merge_sort.c -o merge_sort - $(OBJCOPY) risc_test -O verilog risc_test_verilog.txt - $(OBJCOPY) merge_sort -O verilog merge_sort_verilog.txt - mv risc_test_verilog.txt merge_sort_verilog.txt ../sim/ - -dump: - $(OBJDUMP) -D risc_test - -clean: - rm risc_test risc_test_verilog.txt merge_sort merge_sort_verilog.txt - - diff --git a/test_programs/merge_sort b/test_programs/merge_sort deleted file mode 100755 index a974317..0000000 Binary files a/test_programs/merge_sort and /dev/null differ diff --git a/test_programs/risc_test.c b/test_programs/risc_test.c deleted file mode 100644 index 27b1276..0000000 --- a/test_programs/risc_test.c +++ /dev/null @@ -1,23 +0,0 @@ -int main(void)__attribute__ ((section (".text.start"))); -int a = 126; -int b = 246; - -void fib(int n1, int n2, int N, int* arr) { - int val; - if (N == 0) { - return; - } - val = n1 + n2; - *arr = val; - fib(n2, val, --N, ++arr); - return; -} - -int main() { - asm volatile ("lui sp,0x8; addi s0,sp,64;"); - int c = a + b; - int nums[10]; - fib(0, 1, 2, nums); - - return c; -} diff --git a/test_programs/start.s b/test_programs/start.s deleted file mode 100644 index 27efa0d..0000000 --- a/test_programs/start.s +++ /dev/null @@ -1,2 +0,0 @@ -_start: - j main diff --git a/tests/fix_addr.py b/tests/fix_addr.py new file mode 100644 index 0000000..ad7dcfa --- /dev/null +++ b/tests/fix_addr.py @@ -0,0 +1,49 @@ +import argparse +from tempfile import mkstemp +from shutil import move, copymode +from os import fdopen, remove + + +def get_command_line_args(): + parser = argparse.ArgumentParser() + + parser.add_argument( + "-f", "--file_name", type=str, default="" + ) + + parser.add_argument( + "-w", "--data_width", type=int, default=1 + ) + + args = parser.parse_args() + + file_name = getattr(args, "file_name") + data_width = getattr(args, "data_width") + + return file_name, data_width + +def fix_address(line, data_width): + if line[0] == "@": + mem_addr = int(line[1:], 16) + mem_addr = mem_addr // 4 + line = f"@{mem_addr:0{8}X}\n" + return line + +def fix_addresses(file_name, data_width): + #Create temp file + fh, abs_path = mkstemp() + with fdopen(fh,'w') as new_file: + with open(file_name) as old_file: + for line in old_file: + new_file.write(fix_address(line, data_width)) + #Copy the file permissions from the old file to the new file + copymode(file_name, abs_path) + #Remove original file + remove(file_name) + #Move new file + move(abs_path, file_name) + +if __name__ == "__main__": + file_name, data_width = get_command_line_args() + fix_addresses(file_name, data_width) + diff --git a/test_programs/risc.ld b/tests/risc.ld similarity index 96% rename from test_programs/risc.ld rename to tests/risc.ld index e46e59c..b6a4e1b 100644 --- a/test_programs/risc.ld +++ b/tests/risc.ld @@ -5,7 +5,7 @@ SECTIONS . = 0x0; .text : { - *(.text.start) + *(.text.main) *(.text) } . = ALIGN(4096); /* align to page size */ diff --git a/tests/src/blink_test.c b/tests/src/blink_test.c new file mode 100644 index 0000000..523dd1a --- /dev/null +++ b/tests/src/blink_test.c @@ -0,0 +1,31 @@ +#include + +#define GPIO_REG (volatile uint32_t*) 0x400000 +#define ANSWER_1 (volatile uint32_t*) 0x100 +#define ANSWER_2 (volatile uint32_t*) 0x200 + +void delay() { + for (int i = 0; i < 1; i++) + asm volatile ("nop"); +} + +void blink() { + volatile uint32_t* gpio = GPIO_REG; + uint32_t state = *gpio; + state = state ^ 0x3FF; + *gpio = state; +} + +__attribute__((naked)) +int main() { + asm volatile ("lui sp, 0x8;"); + volatile uint32_t* gpio = GPIO_REG; + volatile uint32_t* answer_1 = ANSWER_1; + volatile uint32_t* answer_2 = ANSWER_2; + blink(); + *answer_1 = *gpio; + delay(); + blink(); + *answer_2 = *gpio; + while(1); +} \ No newline at end of file diff --git a/tests/src/blinky.c b/tests/src/blinky.c new file mode 100644 index 0000000..6856b0c --- /dev/null +++ b/tests/src/blinky.c @@ -0,0 +1,23 @@ +#include + +#define GPIO_REG (volatile uint32_t*) 0x400000 + +void delay() { + for (int i = 0; i < 1; i++) + asm volatile ("nop"); +} + +void blink() { + volatile uint32_t* gpio = GPIO_REG; + uint32_t state = *gpio; + state = state ^ 0x3FF; + *gpio = state; +} + +int main() { + asm volatile ("lui sp, 0x8; addi sp,sp,-16; sw ra,12(sp); sw s0,8(sp)"); + while (1) { + blink(); + delay(); + } +} \ No newline at end of file diff --git a/tests/src/fib_test.c b/tests/src/fib_test.c new file mode 100644 index 0000000..ce439da --- /dev/null +++ b/tests/src/fib_test.c @@ -0,0 +1,21 @@ +#include + +#define ANSWER_1 (uint32_t*) 0x100 + +void fib(uint32_t n1, uint32_t n2, uint32_t N, uint32_t* arr) { + uint32_t val; + if (N == 0) { + return; + } + val = n1 + n2; + *arr = val; + fib(n2, val, --N, ++arr); + return; +} + +__attribute__ ((naked, section (".text.main"))) +int main() { + asm volatile ("lui sp,0x8"); + uint32_t* nums = ANSWER_1; + fib(0, 1, 2, nums); +} \ No newline at end of file diff --git a/tests/src/jump_instructions_test.c b/tests/src/jump_instructions_test.c new file mode 100644 index 0000000..7684cc1 --- /dev/null +++ b/tests/src/jump_instructions_test.c @@ -0,0 +1,23 @@ +__attribute__((naked)) +int main() { + asm volatile ("j 0x8;\n" // Jump to 0x8 + "li x31, -1;\n" // If it fails, put -1 in x31 + "jal x4, 0x10;\n" // Jump to 0x10, place 0xC in x4 + "li x30, -1;\n" // If it fails, put -1 in x30 + "addi x8,x8,0x10;\n" // Place 0x10 in x8 + "jalr x5, x8, 0xC;\n" // Jump to 0x1C, place 0x18 in x5 + "li x29, -1;\n" // If it fails, put -1 in x29 + "li x28, 1;" // Done! + ); + while(1); + /* + End Result: + x31 is 0 + x30 is 0 + x29 is 0 + x28 is 1s + x8 is 0x10 + x4 is 0xC + x5 is 0x18 + */ +} \ No newline at end of file diff --git a/tests/src/load_store_instruction_test.c b/tests/src/load_store_instruction_test.c new file mode 100644 index 0000000..58ed97f --- /dev/null +++ b/tests/src/load_store_instruction_test.c @@ -0,0 +1,18 @@ +__attribute__((naked)) +int main() { + asm volatile ("lui x9, 0x8;\n" // Set x9 as 0x800 + "addi x8,x8,0x10;\n" // Set x8 as 0x10 + "sw x8,0(x9);\n" // Store x8 at x9 (this should not pull a cache line and just write through to memory) + "lw x8,0(x9);\n" // Load the value at x9 into x8 (this should cause a cache miss) + "add x8,x8,1;\n" // Increment x8 by 1 + "sw x8,0(x9);\n" // Store x8 back at x9 to check if both the cached version + the main memory version both update correctly + ); + while(1); + /* + End Result: + - x9 should be 0x8 + - x8 should be 0x11 + - addr 0x8000 should be 0x11 + - addr 0x8000 in chace should be 0x11 + */ +} \ No newline at end of file diff --git a/test_programs/merge_sort.c b/tests/src/merge_sort.c similarity index 93% rename from test_programs/merge_sort.c rename to tests/src/merge_sort.c index 551be68..2be48ce 100644 --- a/test_programs/merge_sort.c +++ b/tests/src/merge_sort.c @@ -3,7 +3,7 @@ int merge_sort(uint32_t* numbers, uint32_t* work_array, uint32_t num); int main(void)__attribute__ ((section (".text.start"))); -uint32_t nums[] = {1, 2, 1, 81}; // 21, 9, 98, 43}; // 8, 12, 13, 67, 19, 38, 34, 2}; +uint32_t nums[] = {1, 2, 1, 81}; uint32_t wk_array[4]; uint32_t copy(uint32_t* src, uint32_t* dst, uint32_t size) { diff --git a/tests/src/read_write_to_peripheral_test.c b/tests/src/read_write_to_peripheral_test.c new file mode 100644 index 0000000..0589494 --- /dev/null +++ b/tests/src/read_write_to_peripheral_test.c @@ -0,0 +1,16 @@ +#include + +#define GPIO_REG (volatile uint32_t*) 0x400000 +#define WRITE_ADDR (volatile uint32_t*) 0x100 + +__attribute__((naked)) +int main() { + asm volatile ("lui sp, 0x8;"); + volatile uint32_t* gpio = GPIO_REG; + volatile uint32_t* write_addr = WRITE_ADDR; + uint32_t state = *gpio; + state = state ^ 0x3FF; + *gpio = state; + *write_addr = *gpio; + while (1); +} \ No newline at end of file diff --git a/tests/test_blink.py b/tests/test_blink.py new file mode 100644 index 0000000..694bb41 --- /dev/null +++ b/tests/test_blink.py @@ -0,0 +1,58 @@ +import os +from os import listdir +from os.path import isfile, join +from pathlib import Path + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb_test.simulator import run + +SRC_FILE_DIR = "./src/" + +@cocotb.test() +async def blink_test(dut): + + expected_val_1 = 0x3FF + answer_1_addr = 0x100 + expected_val_2 = 0x0 + answer_2_addr = 0x200 + + # # Create a 10ns period clock + clock = Clock(dut.clk, 5, units="us") + cocotb.start_soon(clock.start()) + + # Reset DUT + dut.rst.value = 1 + await RisingEdge(dut.clk) + dut.rst.value = 0 + + # Wait 800 clock cycles + for i in range(800): + await RisingEdge(dut.clk) + + sram_data_1 = int(dut.sr.ram[answer_1_addr >> 2].value) + sram_data_2 = int(dut.sr.ram[answer_2_addr >> 2].value) + + assert sram_data_1 == expected_val_1 + assert sram_data_2 == expected_val_2 + +def test(): + verilog_sources = [f"{SRC_FILE_DIR}{f}" for f in listdir(SRC_FILE_DIR) if isfile(join(SRC_FILE_DIR, f))] + toplevel = "risc_de10" + module_name = __file__.strip("/").split("/")[-1].removesuffix(".py") + test_file = os.getcwd() + "/tests/hex/blink_test.hex" + + run( + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module_name, + includes=[SRC_FILE_DIR], + waves=True, + simulator="icarus", + parameters={"INIT_PROGRAM" : f"\"{test_file}\""}, + sim_build="build/blink" + ) + +if __name__ == "__main__": + test() \ No newline at end of file diff --git a/tests/test_fib.py b/tests/test_fib.py new file mode 100644 index 0000000..2cafa6a --- /dev/null +++ b/tests/test_fib.py @@ -0,0 +1,64 @@ +import os +from os import listdir +from os.path import isfile, join +from pathlib import Path + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb_test.simulator import run + +SRC_FILE_DIR = "./src/" + +@cocotb.test() +async def fib_test(dut): + + expected_vals = [1, 2] + beginning_addr = 0x100 + + # Create a 10ns period clock + clock = Clock(dut.clk, 5, units="us") + cocotb.start_soon(clock.start()) + + # Reset DUT + dut.rst.value = 1 + await RisingEdge(dut.clk) + dut.rst.value = 0 + + # Wait 800 clock cycles + for i in range(800): + await RisingEdge(dut.clk) + + received_vals = [] + addr = beginning_addr + idx = 0 + for exp_val in expected_vals: + print((addr >> 2) + idx) + sram_data = int(dut.sr.ram[(addr >> 2) + idx].value) + received_vals.append(sram_data) + idx += 1 + + print(received_vals) + + for exp_val, rec_val in zip(expected_vals, received_vals): + assert exp_val == rec_val + +def test(): + verilog_sources = [f"{SRC_FILE_DIR}{f}" for f in listdir(SRC_FILE_DIR) if isfile(join(SRC_FILE_DIR, f))] + toplevel = "risc_de10" + module_name = __file__.strip("/").split("/")[-1].removesuffix(".py") + test_file = os.getcwd() + "/tests/hex/fib_test.hex" + + run( + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module_name, + includes=[SRC_FILE_DIR], + waves=True, + simulator="icarus", + parameters={"INIT_PROGRAM" : f"\"{test_file}\""}, + sim_build="build/fib" + ) + +if __name__ == "__main__": + test() \ No newline at end of file diff --git a/tests/test_jump_instructions.py b/tests/test_jump_instructions.py new file mode 100644 index 0000000..498f693 --- /dev/null +++ b/tests/test_jump_instructions.py @@ -0,0 +1,65 @@ +import os +from os import listdir +from os.path import isfile, join +from pathlib import Path + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb_test.simulator import run + +SRC_FILE_DIR = "./src/" + +@cocotb.test() +async def jump_test(dut): + + register_file = dut.cpu.regs + + # # Create a 10ns period clock + clock = Clock(dut.clk, 5, units="us") + cocotb.start_soon(clock.start()) + + # Reset DUT + dut.rst.value = 1 + await RisingEdge(dut.clk) + dut.rst.value = 0 + + # Wait 100 clock cycles + for i in range(100): + await RisingEdge(dut.clk) + + x31 = int(register_file.qn[30].value) + x30 = int(register_file.qn[29].value) + x29 = int(register_file.qn[28].value) + x28 = int(register_file.qn[27].value) + x8 = int(register_file.qn[7].value) + x4 = int(register_file.qn[3].value) + x5 = int(register_file.qn[4].value) + + assert x31 == 0 + assert x30 == 0 + assert x29 == 0 + assert x28 == 1 + assert x8 == 0x10 + assert x4 == 0xC + assert x5 == 0x18 + +def test(): + verilog_sources = [f"{SRC_FILE_DIR}{f}" for f in listdir(SRC_FILE_DIR) if isfile(join(SRC_FILE_DIR, f))] + toplevel = "risc_de10" + module_name = __file__.strip("/").split("/")[-1].removesuffix(".py") + test_file = os.getcwd() + "/tests/hex/jump_instructions_test.hex" + + run( + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module_name, + includes=[SRC_FILE_DIR], + waves=True, + simulator="icarus", + parameters={"INIT_PROGRAM" : f"\"{test_file}\""}, + sim_build="build/jump_build" + ) + +if __name__ == "__main__": + test() \ No newline at end of file diff --git a/tests/test_load_store_instructions.py b/tests/test_load_store_instructions.py new file mode 100644 index 0000000..3b1c8f4 --- /dev/null +++ b/tests/test_load_store_instructions.py @@ -0,0 +1,72 @@ +import os +from os import listdir +from os.path import isfile, join +from pathlib import Path + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb_test.simulator import run + +SRC_FILE_DIR = "./src/" + +@cocotb.test() +async def store_load_test(dut): + + register_file = dut.cpu.regs + sram_data = dut.sr.ram + cache = dut.cpu.ms.dmem_cache.cch + + # # Create a 10ns period clock + clock = Clock(dut.clk, 5, units="us") + cocotb.start_soon(clock.start()) + + # Reset DUT + dut.rst.value = 1 + await RisingEdge(dut.clk) + dut.rst.value = 0 + + # Wait 200 clock cycles + for i in range(200): + await RisingEdge(dut.clk) + + + # Check the expected values for everything + exp_val = 17 + + x8 = int(register_file.qn[7].value) + x9 = int(register_file.qn[8].value) + + lui_val = 8 + addr = lui_val << 12 + addr_val = int(sram_data[addr >> 2]) + + cache.re.value = 1 + cache.addr.value = addr + await Timer(1, units="us") + cache_addr_val = int(cache.data_out.value) + + assert x8 == exp_val + assert x9 == addr + assert addr_val == exp_val + assert cache_addr_val == exp_val + +def test(): + verilog_sources = [f"{SRC_FILE_DIR}{f}" for f in listdir(SRC_FILE_DIR) if isfile(join(SRC_FILE_DIR, f))] + toplevel = "risc_de10" + module_name = __file__.strip("/").split("/")[-1].removesuffix(".py") + test_file = os.getcwd() + "/tests/hex/load_store_instruction_test.hex" + + run( + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module_name, + includes=[SRC_FILE_DIR], + waves=True, + simulator="icarus", + parameters={"INIT_PROGRAM" : f"\"{test_file}\""}, + sim_build="build/store_load_build" + ) + +if __name__ == "__main__": + test() \ No newline at end of file diff --git a/tests/test_peripheral_read_write.py b/tests/test_peripheral_read_write.py new file mode 100644 index 0000000..3a1fa0d --- /dev/null +++ b/tests/test_peripheral_read_write.py @@ -0,0 +1,56 @@ +import os +from os import listdir +from os.path import isfile, join +from pathlib import Path + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb_test.simulator import run + +SRC_FILE_DIR = "./src/" + +@cocotb.test() +async def write_read_periph_test(dut): + + expected_val = 0x3FF + write_addr = 0x100 + + # # Create a 10ns period clock + clock = Clock(dut.clk, 5, units="us") + cocotb.start_soon(clock.start()) + + # Reset DUT + dut.rst.value = 1 + await RisingEdge(dut.clk) + dut.rst.value = 0 + + # Wait 200 clock cycles + for i in range(200): + await RisingEdge(dut.clk) + + sram_data = int(dut.sr.ram[write_addr >> 2].value) + peripheral_reg_val = int(dut.periph.qn[0].value) + + assert sram_data == expected_val + assert peripheral_reg_val == expected_val + +def test(): + verilog_sources = [f"{SRC_FILE_DIR}{f}" for f in listdir(SRC_FILE_DIR) if isfile(join(SRC_FILE_DIR, f))] + toplevel = "risc_de10" + module_name = __file__.strip("/").split("/")[-1].removesuffix(".py") + test_file = os.getcwd() + "/tests/hex/read_write_to_peripheral_test.hex" + + run( + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module_name, + includes=[SRC_FILE_DIR], + waves=True, + simulator="icarus", + parameters={"INIT_PROGRAM" : f"\"{test_file}\""}, + sim_build="build/write_to_peripheral" + ) + +if __name__ == "__main__": + test() \ No newline at end of file