Optimize bswap.

Author: jacobly0

llvm/include/llvm/IR/RuntimeLibcalls.def

@@ -165,6 +165,9 @@ HANDLE_LIBCALL(BITREV_I24, nullptr)
 HANDLE_LIBCALL(BITREV_I32, nullptr)
 HANDLE_LIBCALL(BITREV_I64, nullptr)
 HANDLE_LIBCALL(BITREV_I128, nullptr)
+HANDLE_LIBCALL(BSWAP_I32, nullptr)
+HANDLE_LIBCALL(BSWAP_I64, nullptr)
+HANDLE_LIBCALL(BSWAP_I128, nullptr)
 
 // Floating-point
 HANDLE_LIBCALL(ADD_F32, "__addsf3")

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -556,6 +556,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
     RTLIBCASE_ALL(UREM_I);
   case TargetOpcode::G_CTPOP:
     RTLIBCASE_ALL(POPCNT_I);
+  case TargetOpcode::G_BSWAP:
+    RTLIBCASE_INT(BSWAP_I);
   case TargetOpcode::G_BITREVERSE:
     RTLIBCASE_ALL(BITREV_I);
   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
@@ -876,6 +878,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
   case TargetOpcode::G_UDIV:
   case TargetOpcode::G_SREM:
   case TargetOpcode::G_UREM:
+  case TargetOpcode::G_BSWAP:
   case TargetOpcode::G_BITREVERSE: {
     Type *HLTy = IntegerType::get(Ctx, Size);
     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);

llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp

@@ -224,10 +224,9 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
       .clampScalar(0, s8, sMax);
 
   getActionDefinitionsBuilder(
-      {G_SDIVREM, G_UDIVREM, G_ABS,     G_DYN_STACKALLOC, G_SEXT_INREG,
-       G_BSWAP,   G_SMULO,   G_SMULH,   G_UMULH,          G_SMIN,
-       G_SMAX,    G_UMIN,    G_UMAX,    G_UADDSAT,        G_SADDSAT,
-       G_USUBSAT, G_SSUBSAT, G_USHLSAT, G_SSHLSAT,        G_FPOWI})
+      {G_SDIVREM, G_UDIVREM, G_ABS, G_DYN_STACKALLOC, G_SEXT_INREG, G_SMULO,
+       G_SMULH, G_UMULH, G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_UADDSAT, G_SADDSAT,
+       G_USUBSAT, G_SSUBSAT, G_USHLSAT, G_SSHLSAT, G_FPOWI})
       .lower();
 
   getActionDefinitionsBuilder({G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ_ZERO_UNDEF})
@@ -242,6 +241,11 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
       .libcallForCartesianProduct({s8}, LegalLibcallScalars)
       .clampScalar(0, s8, s8);
 
+  getActionDefinitionsBuilder(G_BSWAP)
+      .legalFor({s16})
+      .libcallFor({s32, s64})
+      .clampScalar(0, s16, s64);
+
   getActionDefinitionsBuilder(G_BITREVERSE)
       .libcallFor(LegalLibcallScalars)
       .clampScalar(0, s8, s64);
@@ -448,8 +452,8 @@ Z80LegalizerInfo::legalizeVAStart(LegalizerHelper &Helper,
 LegalizerHelper::LegalizeResult
 Z80LegalizerInfo::legalizeShift(LegalizerHelper &Helper, MachineInstr &MI,
                                 LostDebugLocObserver &LocObserver) const {
-  assert((MI.getOpcode() == G_SHL || MI.getOpcode() == G_LSHR ||
-          MI.getOpcode() == G_ASHR) &&
+  unsigned Opc = MI.getOpcode();
+  assert((Opc == G_SHL || Opc == G_LSHR || Opc == G_ASHR) &&
          "Unexpected opcode");
   MachineRegisterInfo &MRI = *Helper.MIRBuilder.getMRI();
   Register DstReg = MI.getOperand(0).getReg();
@@ -458,17 +462,13 @@ Z80LegalizerInfo::legalizeShift(LegalizerHelper &Helper, MachineInstr &MI,
           getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI)) {
     if (Ty == LLT::scalar(8) && Amt->Value == 1)
       return LegalizerHelper::AlreadyLegal;
-    if (MI.getOpcode() == G_SHL && Amt->Value == 1) {
-      Helper.Observer.changingInstr(MI);
-      MI.setDesc(Helper.MIRBuilder.getTII().get(G_ADD));
-      MI.getOperand(2).setReg(MI.getOperand(1).getReg());
-      Helper.Observer.changedInstr(MI);
-      return LegalizerHelper::Legalized;
-    }
+    if ((Opc == G_SHL || Opc == G_LSHR) && Ty == LLT::scalar(16) &&
+        Amt->Value == 8)
+      return LegalizerHelper::AlreadyLegal;
     if (MI.getOpcode() == G_ASHR && Amt->Value == Ty.getSizeInBits() - 1 &&
         (Ty == LLT::scalar(8) || Ty == LLT::scalar(16) ||
          (Subtarget.is24Bit() && Ty == LLT::scalar(24))))
-      return LegalizerHelper::Legalized;
+      return LegalizerHelper::AlreadyLegal;
   }
   return Helper.libcall(MI, LocObserver);
 }

llvm/lib/Target/Z80/Z80ISelLowering.cpp

@@ -148,6 +148,8 @@ Z80TargetLowering::Z80TargetLowering(const Z80TargetMachine &TM,
   setLibcall(RTLIB::BITREV_I24,       "_ibitrev",  CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::BITREV_I32,       "_lbitrev",  CallingConv::Z80_LibCall   );
   setLibcall(RTLIB::BITREV_I64,       "_llbitrev", CallingConv::Z80_LibCall   );
+  setLibcall(RTLIB::BSWAP_I32,        "_lbswap",   CallingConv::Z80_LibCall   );
+  setLibcall(RTLIB::BSWAP_I64,        "_llbswap",  CallingConv::Z80_LibCall   );
 
   setLibcall(RTLIB::ADD_F32,          "_fadd",     CallingConv::Z80_LibCall_L );
   setLibcall(RTLIB::SUB_F32,          "_fsub",     CallingConv::Z80_LibCall_L );

llvm/lib/Target/Z80/Z80InstrInfo.td

@@ -1256,7 +1256,7 @@ def : Pat<(Z80tcret (texternalsym:$dst)), (TCRETURN24 texternalsym:$dst)>,
       Requires<[In24BitMode]>;
 
 //===----------------------------------------------------------------------===//
-// Subsystems.
+// Subreg Twiddling
 //===----------------------------------------------------------------------===//
 
 // anyext
@@ -1279,3 +1279,16 @@ def : Pat<(i24 (zext R16:$src)),
 def : Pat<(i8  (trunc R16:$src)), (EXTRACT_SUBREG R16:$src, sub_low)>;
 def : Pat<(i8  (trunc R24:$src)), (EXTRACT_SUBREG R24:$src, sub_low)>;
 def : Pat<(i16 (trunc R24:$src)), (EXTRACT_SUBREG R24:$src, sub_short)>;
+
+// shift
+def : Pat<(shl R16:$src, (i8 8)),
+          (REG_SEQUENCE R16, (i8 (EXTRACT_SUBREG R16:$src, sub_low)), sub_high,
+                             (LD8r0), sub_low)>;
+def : Pat<(srl R16:$src, (i8 8)),
+          (REG_SEQUENCE R16, (LD8r0), sub_high,
+                             (i8 (EXTRACT_SUBREG R16:$src, sub_high)), sub_low)>;
+
+// bswap
+def : Pat<(bswap R16:$src),
+          (REG_SEQUENCE R16, (i8 (EXTRACT_SUBREG R16:$src, sub_low)), sub_high,
+                             (i8 (EXTRACT_SUBREG R16:$src, sub_high)), sub_low)>;