Fix some interrupt stuff.

Author: jacobly0

clang/include/clang/Basic/DiagnosticSemaKinds.td

@@ -309,7 +309,7 @@ def warn_arm_interrupt_calling_convention : Warning<
    "call to function without interrupt attribute could clobber interruptee's VFP registers">,
    InGroup<Extra>;
 def warn_interrupt_attribute_invalid : Warning<
-   "%select{MIPS|MSP430|RISC-V}0 'interrupt' attribute only applies to "
+   "%select{MIPS|MSP430|RISC-V|Z80}0 'interrupt' attribute only applies to "
    "functions that have %select{no parameters|a 'void' return type}1">,
    InGroup<IgnoredAttributes>;
 def warn_riscv_repeated_interrupt_attribute : Warning<

clang/lib/Sema/SemaDeclAttr.cpp

@@ -7320,10 +7320,35 @@ static void handleZ80InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
     return;
   }
 
-  if (!AL.checkExactlyNumArgs(S, 0))
+  if (hasFunctionProto(D) && getFunctionOrMethodNumParams(D) != 0) {
+    S.Diag(D->getLocation(), diag::warn_interrupt_attribute_invalid)
+        << /*Z80*/ 3 << 0;
+    return;
+  }
+
+  if (!getFunctionOrMethodResultType(D)->isVoidType()) {
+    S.Diag(D->getLocation(), diag::warn_interrupt_attribute_invalid)
+        << /*Z80*/ 3 << 1;
     return;
+  }
+
+  // The attribute takes an optional string argument.
+  if (!AL.checkAtMostNumArgs(S, 1))
+    return;
+
+  StringRef Str;
+  SourceLocation ArgLoc;
+  if (AL.getNumArgs() && !S.checkStringLiteralArgumentAttr(AL, 0, Str, &ArgLoc))
+    return;
+
+  AnyZ80InterruptAttr::InterruptType Kind;
+  if (!AnyZ80InterruptAttr::ConvertStrToInterruptType(Str, Kind)) {
+    S.Diag(AL.getLoc(), diag::warn_attribute_type_not_supported)
+        << AL << ("\"" + Str + "\"").str() << ArgLoc;
+    Kind = AnyZ80InterruptAttr::InterruptType::Generic;
+  }
 
-  handleSimpleAttribute<AnyZ80InterruptAttr>(S, D, AL);
+  D->addAttr(::new (S.Context) AnyZ80InterruptAttr(S.Context, AL, Kind));
 }
 
 static void handleInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {

llvm/include/llvm/IR/CallingConv.h

@@ -252,16 +252,18 @@ namespace CallingConv {
     /// M68k_INTR - Calling convention used for M68k interrupt routines.
     M68k_INTR = 101,
 
+    /// Calling convention for passing an OS-defined constant in the IY register.
+    Z80_TIFlags = 102,
+
     /// Calling conventions used for special Z80 rtlib functions
     /// which pass in registers and save all registers.
-    Z80_LibCall = 102,
-    Z80_LibCall_AB = 103,
-    Z80_LibCall_AC = 104,
-    Z80_LibCall_BC = 105,
-    Z80_LibCall_L = 106,
-    Z80_LibCall_F = 107,
-    Z80_LibCall_16 = 108,
-    Z80_TIFlags = 109,
+    Z80_LibCall = 103,
+    Z80_LibCall_AB = 104,
+    Z80_LibCall_AC = 105,
+    Z80_LibCall_BC = 106,
+    Z80_LibCall_L = 107,
+    Z80_LibCall_F = 108,
+    Z80_LibCall_16 = 189,
 
     /// The highest possible calling convention ID. Must be some 2^k - 1.
     MaxID = 1023

llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp

@@ -19,6 +19,7 @@
 #include "Z80MachineFunctionInfo.h"
 #include "Z80RegisterInfo.h"
 #include "Z80Subtarget.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
@@ -425,12 +426,18 @@ bool Z80CallLowering::isEligibleForTailCallOptimization(
   if (!Info.IsTailCall)
     return false;
 
+  const Function *CalleeF = Info.CB ? Info.CB->getCalledFunction() : nullptr;
   CallingConv::ID CalleeCC = Info.CallConv;
-  MachineFunction &MF = MIRBuilder.getMF();
-  const Function &CallerF = MF.getFunction();
+  MachineFunction &CallerMF = MIRBuilder.getMF();
+  const Function &CallerF = CallerMF.getFunction();
 
   LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
 
+  if (CalleeF && CalleeF->hasFnAttribute("interrupt")) {
+    LLVM_DEBUG(dbgs() << "... Cannot tail call interrupt handlers.\n");
+    return false;
+  }
+
   if (Info.SwiftErrorVReg) {
     // TODO: We should handle this.
     // Note that this is also handled by the check for no outgoing arguments.
@@ -465,7 +472,7 @@ bool Z80CallLowering::isEligibleForTailCallOptimization(
   }
 
   // If we have -tailcallopt, then we're done.
-  if (MF.getTarget().Options.GuaranteedTailCallOpt)
+  if (CallerMF.getTarget().Options.GuaranteedTailCallOpt)
     return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
 
   // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
@@ -478,14 +485,14 @@ bool Z80CallLowering::isEligibleForTailCallOptimization(
 
   // Verify that the incoming and outgoing arguments from the callee are
   // safe to tail call.
-  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
+  if (!doCallerAndCalleePassArgsTheSameWay(Info, CallerMF, InArgs)) {
     LLVM_DEBUG(
         dbgs()
         << "... Caller and callee have incompatible calling conventions.\n");
     return false;
   }
 
-  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
+  if (!areCalleeOutgoingArgsTailCallable(Info, CallerMF, OutArgs))
     return false;
 
   LLVM_DEBUG(dbgs() << "... Call is eligible for tail call optimization.\n");
@@ -506,14 +513,6 @@ bool Z80CallLowering::lowerTailCall(MachineIRBuilder &MIRBuilder,
   // True when we're tail calling, but without -tailcallopt.
   bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
 
-  // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
-  // register class. Until we can do that, we should fall back here.
-  if (F.hasFnAttribute("branch-target-enforcement")) {
-    LLVM_DEBUG(
-        dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
-    return false;
-  }
-
   MachineInstrBuilder CallSeqStart;
   if (!IsSibCall)
     CallSeqStart = MIRBuilder.buildInstr(TII.getCallFrameSetupOpcode());
@@ -779,11 +778,17 @@ bool Z80CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                   FunctionLoweringInfo &FLI) const {
   assert(!Val == VRegs.empty() && "Return value without a vreg");
   MachineFunction &MF = MIRBuilder.getMF();
+  const Function &F = MF.getFunction();
   LLVMContext &Ctx = MF.getFunction().getContext();
   auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
   const auto &STI = MF.getSubtarget<Z80Subtarget>();
-  auto MIB =
-      MIRBuilder.buildInstrNoInsert(STI.is24Bit() ? Z80::RET24 : Z80::RET16);
+
+  bool Is24Bit = STI.is24Bit();
+  auto MIB = MIRBuilder.buildInstrNoInsert(
+      StringSwitch<unsigned>(F.getFnAttribute("interrupt").getValueAsString())
+          .Cases("Generic", "Nested", Is24Bit ? Z80::RETI24 : Z80::RETI16)
+          .Case("NMI", Is24Bit ? Z80::RETN24 : Z80::RETN16)
+          .Default(Is24Bit ? Z80::RET24 : Z80::RET16));
 
   Register SRetReturnReg = FuncInfo.getSRetReturnReg();
   assert((!SRetReturnReg || VRegs.empty()) &&

llvm/lib/Target/Z80/Z80CallingConv.td

@@ -124,7 +124,9 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>;
 def CSR_Z80_C : CalleeSavedRegs<(add IX)>;
 def CSR_EZ80_C : CalleeSavedRegs<(add UIX)>;
 def CSR_Z80_AllRegs : CalleeSavedRegs<(add R16, A)>;
+def CSR_Z80_AllRegsAndFlags : CalleeSavedRegs<(add R16, AF)>;
 def CSR_EZ80_AllRegs : CalleeSavedRegs<(add R24, A)>;
 def CSR_EZ80_AllRegs16 : CalleeSavedRegs<(add (sub R24, UHL, UBC), HL, BC, A)>;
+def CSR_EZ80_AllRegsAndFlags : CalleeSavedRegs<(add R24, AF)>;
 def CSR_Z80_TIFlags : CalleeSavedRegs<(add I16)>;
 def CSR_EZ80_TIFlags : CalleeSavedRegs<(add I24)>;

llvm/lib/Target/Z80/Z80FrameLowering.cpp

@@ -357,6 +357,13 @@ static bool shouldUseShadow(const MachineFunction &MF) {
   return F.getFnAttribute("interrupt").getValueAsString() == "Generic";
 }
 
+static MachineInstr& setImplicitUsesUndef(MachineInstr &MI) {
+  for (MachineOperand &MO : MI.implicit_operands())
+    if (MO.isReg() && MO.isUse())
+      MO.setIsUndef();
+  return MI;
+}
+
 void Z80FrameLowering::shadowCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL,
     MachineInstr::MIFlag Flag, const std::vector<CalleeSavedInfo> &CSI) const {
@@ -370,11 +377,13 @@ void Z80FrameLowering::shadowCalleeSavedRegisters(
     else if (Z80::G24RegClass.contains(Reg) || Z80::G16RegClass.contains(Reg))
       SaveG = true;
   }
-  if (SaveAF)
-    BuildMI(MBB, MI, DL, TII.get(Z80::EXAF)).setMIFlag(Flag);
   if (SaveG)
-    BuildMI(MBB, MI, DL, TII.get(Is24Bit ? Z80::EXX24 : Z80::EXX16))
-        .setMIFlag(Flag);
+    setImplicitUsesUndef(
+        *BuildMI(MBB, MI, DL, TII.get(Is24Bit ? Z80::EXX24 : Z80::EXX16))
+             .setMIFlag(Flag));
+  if (SaveAF)
+    setImplicitUsesUndef(
+        *BuildMI(MBB, MI, DL, TII.get(Z80::EXAF)).setMIFlag(Flag));
 }
 
 static Z80MachineFunctionInfo::AltFPMode
@@ -407,7 +416,21 @@ bool Z80FrameLowering::assignCalleeSavedSpillSlots(
   auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
   FuncInfo.setUsesAltFP(shouldUseAltFP(MF, Is24Bit ? Z80::UIY : Z80::IY, TRI));
   MF.getRegInfo().freezeReservedRegs(MF);
-  FuncInfo.setCalleeSavedFrameSize(CSI.size() * SlotSize);
+
+  bool UseShadow = shouldUseShadow(MF);
+  unsigned CalleeSavedFrameSize = isFPSaved(MF) ? SlotSize : 0;
+  for (unsigned i = CSI.size(); i != 0; --i) {
+    unsigned Reg = CSI[i - 1].getReg();
+
+    // Non-index registers can be spilled to shadow registers.
+    if (UseShadow && !Z80::I24RegClass.contains(Reg) &&
+        !Z80::I16RegClass.contains(Reg))
+      continue;
+
+    CalleeSavedFrameSize += SlotSize;
+  }
+  FuncInfo.setCalleeSavedFrameSize(CalleeSavedFrameSize);
+
   return true;
 }
 

llvm/lib/Target/Z80/Z80RegisterInfo.cpp

@@ -102,11 +102,11 @@ unsigned Z80RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
 const MCPhysReg *
 Z80RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   switch (MF->getFunction().getCallingConv()) {
-  default: llvm_unreachable("Unsupported calling convention");
+  default:
+    llvm_unreachable("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
     return Is24Bit ? CSR_EZ80_C_SaveList : CSR_Z80_C_SaveList;
-  case CallingConv::PreserveAll:
   case CallingConv::Z80_LibCall:
   case CallingConv::Z80_LibCall_AB:
   case CallingConv::Z80_LibCall_AC:
@@ -116,6 +116,9 @@ Z80RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     return Is24Bit ? CSR_EZ80_AllRegs_SaveList : CSR_Z80_AllRegs_SaveList;
   case CallingConv::Z80_LibCall_16:
     return Is24Bit ? CSR_EZ80_AllRegs16_SaveList : CSR_Z80_AllRegs_SaveList;
+  case CallingConv::PreserveAll:
+    return Is24Bit ? CSR_EZ80_AllRegsAndFlags_SaveList
+                   : CSR_Z80_AllRegsAndFlags_SaveList;
   case CallingConv::Z80_TIFlags:
     return Is24Bit ? CSR_EZ80_TIFlags_SaveList : CSR_Z80_TIFlags_SaveList;
   }
@@ -208,12 +211,9 @@ void Z80RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   assert(TFI->hasFP(MF) && "Stack slot use without fp unimplemented");
   auto Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) -
                 TFI->getOffsetOfLocalArea();
-  if (FrameIndex >= 0)
-    // For non-fixed indices, skip over callee save slots.
-    Offset -= MF.getInfo<Z80MachineFunctionInfo>()->getCalleeSavedFrameSize();
-  else if (TFI->isFPSaved(MF))
-    // For fixed indices, skip over FP save slot if it exists.
-    Offset += TFI->getSlotSize();
+  if (FrameIndex < 0)
+    // For fixed indices, skip over callee save slots.
+    Offset += MF.getInfo<Z80MachineFunctionInfo>()->getCalleeSavedFrameSize();
   TII.rewriteFrameIndex(MI, FIOperandNum, BaseReg, Offset, RS, SPAdj);
 }