From 5f461d437845f2e1c12f3dd8456c792f62a19112 Mon Sep 17 00:00:00 2001
From: Jeremiah Leary <jeremiah.c.leary@gmail.com>
Date: Wed, 22 Jan 2025 06:43:20 -0600
Subject: [PATCH] Issue#1399:  external names would end processing of the name
 production.

---
 .../classification_results.txt                | 70 ++++++++++---------
 .../classification_test_input.vhd             |  6 +-
 vsg/vhdlFile/classify/name.py                 |  5 +-
 3 files changed, 41 insertions(+), 40 deletions(-)

diff --git a/tests/vhdlFile/alias_declaration/classification_results.txt b/tests/vhdlFile/alias_declaration/classification_results.txt
index 22a6aa56d..c16489bb1 100644
--- a/tests/vhdlFile/alias_declaration/classification_results.txt
+++ b/tests/vhdlFile/alias_declaration/classification_results.txt
@@ -14,19 +14,7 @@
 3 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-4 |
-<class 'vsg.parser.blank_line'>
---------------------------------------------------------------------------------
-5 |
-<class 'vsg.parser.blank_line'>
---------------------------------------------------------------------------------
-6 |
-<class 'vsg.parser.blank_line'>
---------------------------------------------------------------------------------
-7 |
-<class 'vsg.parser.blank_line'>
---------------------------------------------------------------------------------
-8 |   alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2 return integer];
+4 |   alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2 return integer];
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.colon'>
@@ -47,10 +35,10 @@
 <class 'vsg.token.signature.close_bracket'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-9 |
+5 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-10 |   alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2];
+6 |   alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2];
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.colon'>
@@ -69,10 +57,10 @@
 <class 'vsg.token.signature.close_bracket'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-11 |
+7 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-12 |   alias ident : std_logic_vector(3 downto 0) is write_enable [return integer];
+8 |   alias ident : std_logic_vector(3 downto 0) is write_enable [return integer];
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.colon'>
@@ -90,10 +78,10 @@
 <class 'vsg.token.signature.close_bracket'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-13 |
+9 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-14 |   alias ident : std_logic_vector(3 downto 0) is write_enable(15 downto 0);
+10 |   alias ident : std_logic_vector(3 downto 0) is write_enable(15 downto 0);
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.colon'>
@@ -112,13 +100,13 @@
 <class 'vsg.token.todo.close_parenthesis'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-15 |
+11 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-16 |
+12 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-17 |   alias ident is write_enable [name1, name2 return integer];
+13 |   alias ident is write_enable [name1, name2 return integer];
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.is_keyword'>
@@ -132,10 +120,10 @@
 <class 'vsg.token.signature.close_bracket'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-18 |
+14 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-19 |   alias ident is write_enable [name1, name2];
+15 |   alias ident is write_enable [name1, name2];
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.is_keyword'>
@@ -147,10 +135,10 @@
 <class 'vsg.token.signature.close_bracket'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-20 |
+16 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-21 |   alias ident is write_enable [return integer];
+17 |   alias ident is write_enable [return integer];
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.is_keyword'>
@@ -161,26 +149,44 @@
 <class 'vsg.token.signature.close_bracket'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-22 |
+18 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-23 |   alias ident is write_enable;
+19 |   alias ident is write_enable;
 <class 'vsg.token.alias_declaration.alias_keyword'>
 <class 'vsg.token.alias_declaration.alias_designator'>
 <class 'vsg.token.alias_declaration.is_keyword'>
 <class 'vsg.parser.todo'>
 <class 'vsg.token.alias_declaration.semicolon'>
 --------------------------------------------------------------------------------
-24 |
+20 |
+<class 'vsg.parser.blank_line'>
+--------------------------------------------------------------------------------
+21 |   alias alias_sop : std_logic is << signal .tb_top.submodule.i_rx_data : t_mac_interface >> .sop;
+<class 'vsg.token.alias_declaration.alias_keyword'>
+<class 'vsg.token.alias_declaration.alias_designator'>
+<class 'vsg.token.alias_declaration.colon'>
+<class 'vsg.token.type_mark.name'>
+<class 'vsg.token.alias_declaration.is_keyword'>
+<class 'vsg.token.external_signal_name.double_less_than'>
+<class 'vsg.token.external_signal_name.signal_keyword'>
+<class 'vsg.token.external_signal_name.external_pathname'>
+<class 'vsg.token.external_signal_name.colon'>
+<class 'vsg.token.type_mark.name'>
+<class 'vsg.token.external_signal_name.double_greater_than'>
+<class 'vsg.parser.todo'>
+<class 'vsg.token.alias_declaration.semicolon'>
+--------------------------------------------------------------------------------
+22 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-25 | begin
+23 | begin
 <class 'vsg.token.architecture_body.begin_keyword'>
 --------------------------------------------------------------------------------
-26 |
+24 |
 <class 'vsg.parser.blank_line'>
 --------------------------------------------------------------------------------
-27 | end architecture RTL;
+25 | end architecture RTL;
 <class 'vsg.token.architecture_body.end_keyword'>
 <class 'vsg.token.architecture_body.end_architecture_keyword'>
 <class 'vsg.token.architecture_body.architecture_simple_name'>
diff --git a/tests/vhdlFile/alias_declaration/classification_test_input.vhd b/tests/vhdlFile/alias_declaration/classification_test_input.vhd
index 5025b8fd8..3f10bce69 100644
--- a/tests/vhdlFile/alias_declaration/classification_test_input.vhd
+++ b/tests/vhdlFile/alias_declaration/classification_test_input.vhd
@@ -1,10 +1,6 @@
 
 architecture RTL of FIFO is
 
-
-
-
-
   alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2 return integer];
 
   alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2];
@@ -22,6 +18,8 @@ architecture RTL of FIFO is
 
   alias ident is write_enable;
 
+  alias alias_sop : std_logic is << signal .tb_top.submodule.i_rx_data : t_mac_interface >> .sop;
+
 begin
 
 end architecture RTL;
diff --git a/vsg/vhdlFile/classify/name.py b/vsg/vhdlFile/classify/name.py
index 0eb176cb7..dbc918cca 100644
--- a/vsg/vhdlFile/classify/name.py
+++ b/vsg/vhdlFile/classify/name.py
@@ -21,11 +21,8 @@ def classify_until(lUntils, iToken, lObjects, oType=parser.todo):
     NOTE: At the moment, everything will be set to parser.todo.
     """
 
-    iReturn = external_name.detect(iToken, lObjects)
-    if iReturn != iToken:
-        return iReturn
+    iCurrent = external_name.detect(iToken, lObjects)
 
-    iCurrent = iToken
     iStop = len(lObjects) - 1
     iOpenParenthesis = 0
     iCloseParenthesis = 0