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Steve Muckle
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Merge commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126' into msm-3.4
AU_LINUX_ANDROID_ICS.04.00.04.00.126 from msm-3.0. First parent is from google/android-3.4. * commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126': (8712 commits) PRNG: Device tree entry for qrng device. vidc:1080p: Set video core timeout value for Thumbnail mode msm: sps: improve the debugging support in SPS driver board-8064 msm: Overlap secure and non secure video firmware heaps. msm: clock: Add handoff ops for 7x30 and copper XO clocks msm_fb: display: Wait for external vsync before DTV IOMMU unmap msm: Fix ciruclar dependency in debug UART settings msm: gdsc: Add GDSC regulator driver for msm-copper defconfig: Enable Mobicore Driver. mobicore: Add mobicore driver. mobicore: rename variable to lower case. mobicore: rename folder. mobicore: add makefiles mobicore: initial import of kernel driver ASoC: msm: Add SLIMBUS_2_RX CPU DAI board-8064-gpio: Update FUNC for EPM SPI CS msm_fb: display: Remove chicken bit config during video playback mmc: msm_sdcc: enable the sanitize capability msm-fb: display: lm2 writeback support on mpq platfroms msm_fb: display: Disable LVDS phy & pll during panel off ... Signed-off-by: Steve Muckle <[email protected]>
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‎AndroidKernel.mk

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#Android makefile to build kernel as a part of Android Build
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PERL = perl
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ifeq ($(TARGET_PREBUILT_KERNEL),)
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KERNEL_OUT := $(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ
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KERNEL_CONFIG := $(KERNEL_OUT)/.config
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TARGET_PREBUILT_INT_KERNEL := $(KERNEL_OUT)/arch/arm/boot/zImage
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KERNEL_HEADERS_INSTALL := $(KERNEL_OUT)/usr
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KERNEL_MODULES_INSTALL := system
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KERNEL_MODULES_OUT := $(TARGET_OUT)/lib/modules
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KERNEL_IMG=$(KERNEL_OUT)/arch/arm/boot/Image
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MSM_ARCH ?= $(shell $(PERL) -e 'while (<>) {$$a = $$1 if /CONFIG_ARCH_((?:MSM|QSD)[a-zA-Z0-9]+)=y/; $$r = $$1 if /CONFIG_MSM_SOC_REV_(?!NONE)(\w+)=y/;} print lc("$$a$$r\n");' $(KERNEL_CONFIG))
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KERNEL_USE_OF ?= $(shell $(PERL) -e '$$of = "n"; while (<>) { if (/CONFIG_USE_OF=y/) { $$of = "y"; break; } } print $$of;' kernel/arch/arm/configs/$(KERNEL_DEFCONFIG))
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ifeq "$(KERNEL_USE_OF)" "y"
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DTS_NAME ?= $(MSM_ARCH)
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DTS_FILES = $(wildcard $(TOP)/kernel/arch/arm/boot/dts/$(DTS_NAME)*.dts)
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DTS_FILE = $(lastword $(subst /, ,$(1)))
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DTB_FILE = $(addprefix $(KERNEL_OUT)/arch/arm/boot/,$(patsubst %.dts,%.dtb,$(call DTS_FILE,$(1))))
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ZIMG_FILE = $(addprefix $(KERNEL_OUT)/arch/arm/boot/,$(patsubst %.dts,%-zImage,$(call DTS_FILE,$(1))))
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KERNEL_ZIMG = $(KERNEL_OUT)/arch/arm/boot/zImage
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DTC = $(KERNEL_OUT)/scripts/dtc/dtc
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define append-dtb
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mkdir -p $(KERNEL_OUT)/arch/arm/boot;\
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$(foreach d, $(DTS_FILES), \
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$(DTC) -p 1024 -O dtb -o $(call DTB_FILE,$(d)) $(d); \
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cat $(KERNEL_ZIMG) $(call DTB_FILE,$(d)) > $(call ZIMG_FILE,$(d));)
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endef
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else
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define append-dtb
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endef
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endif
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ifeq ($(TARGET_USES_UNCOMPRESSED_KERNEL),true)
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$(info Using uncompressed kernel)
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TARGET_PREBUILT_KERNEL := $(KERNEL_OUT)/piggy
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else
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TARGET_PREBUILT_KERNEL := $(TARGET_PREBUILT_INT_KERNEL)
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endif
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define mv-modules
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mdpath=`find $(KERNEL_MODULES_OUT) -type f -name modules.dep`;\
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if [ "$$mdpath" != "" ];then\
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mpath=`dirname $$mdpath`;\
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ko=`find $$mpath/kernel -type f -name *.ko`;\
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for i in $$ko; do mv $$i $(KERNEL_MODULES_OUT)/; done;\
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fi
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endef
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define clean-module-folder
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mdpath=`find $(KERNEL_MODULES_OUT) -type f -name modules.dep`;\
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if [ "$$mdpath" != "" ];then\
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mpath=`dirname $$mdpath`; rm -rf $$mpath;\
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fi
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endef
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$(KERNEL_OUT):
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mkdir -p $(KERNEL_OUT)
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$(KERNEL_CONFIG): $(KERNEL_OUT)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- $(KERNEL_DEFCONFIG)
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$(KERNEL_OUT)/piggy : $(TARGET_PREBUILT_INT_KERNEL)
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$(hide) gunzip -c $(KERNEL_OUT)/arch/arm/boot/compressed/piggy.gzip > $(KERNEL_OUT)/piggy
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$(TARGET_PREBUILT_INT_KERNEL): $(KERNEL_OUT) $(KERNEL_CONFIG) $(KERNEL_HEADERS_INSTALL)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi-
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- modules
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$(MAKE) -C kernel O=../$(KERNEL_OUT) INSTALL_MOD_PATH=../../$(KERNEL_MODULES_INSTALL) ARCH=arm CROSS_COMPILE=arm-eabi- modules_install
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$(mv-modules)
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$(clean-module-folder)
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$(append-dtb)
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$(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT) $(KERNEL_CONFIG)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- headers_install
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kerneltags: $(KERNEL_OUT) $(KERNEL_CONFIG)
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- tags
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kernelconfig: $(KERNEL_OUT) $(KERNEL_CONFIG)
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env KCONFIG_NOTIMESTAMP=true \
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- menuconfig
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env KCONFIG_NOTIMESTAMP=true \
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$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- savedefconfig
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cp $(KERNEL_OUT)/defconfig kernel/arch/arm/configs/$(KERNEL_DEFCONFIG)
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endif

‎Documentation/ABI/testing/sysfs-bus-pil

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What: /sys/bus/pil/devices/.../name
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Date: March 2012
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Contact: Stephen Boyd <[email protected]>
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Description:
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Shows the name of the peripheral used in pil_get().
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What: /sys/bus/pil/devices/.../state
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Date: March 2012
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Contact: Stephen Boyd <[email protected]>
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Description:
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Shows the state state of a peripheral. Current states
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supported are:
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OFFLINE - peripheral is offline
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ONLINE - peripheral is online
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This file supports poll() to detect when a peripheral changes
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state.

‎Documentation/arm/msm/boot.txt

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Introduction
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=============
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The power management integrated circuit (PMIC) records the reason the
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Application processor was powered on in Shared Memory.
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The hardware and software used is the shared memory interface. This document
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is not for the purpose of describing this interface, but to identify the
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possible values for this data item.
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Description
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===========
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Shared memory item (SMEM_POWER_ON_STATUS_INFO) is read to get access to
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this data. The table below identifies the possible values stored.
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power_on_status values set by the PMIC for power on event:
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----------------------------------------------------------
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0x01 -- keyboard power on
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0x02 -- RTC alarm
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0x04 -- cable power on
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0x08 -- SMPL
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0x10 -- Watch Dog timeout
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0x20 -- USB charger
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0x40 -- Wall charger
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0xFF -- error reading power_on_status value

‎Documentation/arm/msm/emulate_domain_manager.txt

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Introduction
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============
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8x50 chipset requires the ability to disable HW domain manager function.
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The ARM MMU architecture has a feature known as domain manager mode.
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Briefly each page table, section, or supersection is assigned a domain.
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Each domain can be globally configured to NoAccess, Client, or Manager
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mode. These global configurations allow the access permissions of the
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entire domain to be changed simultaneously.
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The domain manger emulation is required to fix a HW problem on the 8x50
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chipset. The problem is simple to repair except when domain manager mode
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is enabled. The emulation allows the problem to be completely resolved.
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Hardware description
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====================
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When domain manager mode is enabled on a specific domain, the MMU
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hardware ignores the access permission bits and the execute never bit. All
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accesses, to memory in the domain, are granted full read, write,
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execute permissions.
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The mode of each domain is controlled by a field in the cp15 dacr register.
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Each domain can be globally configured to NoAccess, Client, or Manager mode.
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See: ARMv7 Architecture Reference Manual
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Software description
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====================
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In order to disable domain manager mode the equivalent HW functionality must
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be emulated in SW. Any attempts to enable domain manager mode, must be
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intercepted.
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Because domain manager mode is not enabled, permissions for the
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associated domain will remain restricted. Permission faults will be generated.
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The permission faults will be intercepted. The faulted pages/sections will
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be modified to grant full access and execute permissions.
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The modified page tables must be restored when exiting domain manager mode.
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Design
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======
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Design Goals:
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Disable Domain Manager Mode
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Exact SW emulation of Domain Manager Mode
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Minimal Kernel changes
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Minimal Security Risk
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Design Decisions:
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Detect kernel page table modifications on restore
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Direct ARMv7 HW MMU table manipulation
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Restore emulation modified MMU entries on context switch
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No need to restore MMU entries for MMU entry copy operations
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Invalidate TLB entries on modification
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Store Domain Manager bits in memory
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8 entry MMU entry cache
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Use spin_lock_irqsave to protect domain manipulation
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Assume no split MMU table
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Design Discussion:
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Detect kernel page table modifications on restore -
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When restoring original page/section permission faults, the submitted design
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verifies the MMU entry has not been modified. The kernel modifies MMU
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entries for the following purposes : create a memory mapping, release a
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memory mapping, add permissions during a permission fault, and map a page
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during a translation fault. The submitted design works with the listed
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scenarios. The translation fault and permission faults simply do not happen on
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relevant entries (valid entries with full access permissions). The alternative
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would be to hook every MMU table modification. The alternative greatly
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increases complexity and code maintenance issues.
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Direct ARMv7 HW MMU table manipulation -
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The natural choice would be to use the kernel provided mechanism to manipulate
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MMU page table entries. The ARM MMU interface is described in pgtable.h.
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This interface is complicated by the Linux implementation. The level 1 pgd
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entries are treated and manipulated as entry pairs. The level 2 entries are
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shadowed and cloned. The compromise was chosen to actually use the ARMv7 HW
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registers to walk and modify the MMU table entries. The choice limits the
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usage of this implementation to ARMv7 and similar ARM MMU architectures. Since
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this implementation is targeted at fixing an issue in 8x50 ARMv7, the choice is
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logical. The HW manipulation is in distinct low level functions. These could
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easily be replaced or generalized to support other architectures as necessary.
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Restore emulation modified MMU entries on context switch -
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This additional hook was added to minimize performance impact. By guaranteeing
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the ASID will not change during the emulation, the emulation may invalidate each
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entry by MVA & ASID. Only the affected page table entries will be removed from
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the TLB cache. The performance cost of the invalidate on context switch is near
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zero. Typically on context switch the domain mode would also change, forcing a
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complete restore of all modified MMU entries. The alternative would be to
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invalidate the entire TLB every time a table entry is restored.
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No need to restore MMU entries for copy operations -
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Operations which copy MMU entries are relatively rare in the kernel. Because
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we modify the level 2 pte entries directly in hardware, the Linux shadow copies
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are left untouched. The kernel treats the shadow copies as the primary pte
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entry. Any pte copy operations would be unaffected by the HW modification.
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On translation section fault, pgd entries are copied from the kernel master
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page table to the current thread page table. Since we restore MMU entries on
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context switch, we guarantee the master table will not contain modifications,
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while faulting on a process local entry. Other read, modify write operations
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occur during permission fault handling. Since we open permission on modified
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entries, these do not need to be restored, because we guarantee these
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permission fault operations will not happen.
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Invalidate TLB entries on modification -
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No real choice here. This is more of a design requirement. On permission
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fault, the MMU entry with restricted permissions will be in the TLB. To open
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access permissions, the TLB entry must be invalidated. Otherwise the access
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will permission fault again. Upon restoring original MMU entries, the TLB
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must be invalidated to restrict memory access.
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Store Domain Manager bits in memory -
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There was only one alternative here. 2.6.29 kernel only uses 3 of 16
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possible domains. Additional bits in dacr could be used to store the
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manager bits. This would allow faster access to the manager bits.
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Overall this would reduce any performance impact. The performance
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needs did not seem to justify the added weirdness.
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8 entry MMU entry cache-
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The size of the modified MMU entry cache is somewhat arbitrary. The thought
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process is that typically, a thread is using two pointers to perform a copy
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operation. In this case only 2 entries would be required. One could imagine
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a more complicated operation, a masked copy for instance, which would require
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more pointers. 8 pointer seemed to be large enough to minimize risk of
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permission fault thrashing. The disadvantage of a larger cache would simply
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be a longer list of entries to restore.
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Use spin_lock_irqsave to protect domain manipulation -
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The obvious choice.
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Assume no split MMU table -
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This same assumption is documented in cpu_v7_switch_mm.
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Power Management
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================
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Not affected.
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SMP/multi-core
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==============
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SMP/multicore not supported. This is intended as a 8x50 workaround.
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Security
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========
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MMU page/section permissions must be manipulated correctly to emulate domain
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manager mode. If page permission are left in full access mode, any process
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can read associated memory.
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Performance
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===========
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Performance should be impacted only minimally. When emulating domain manager
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mode, there is overhead added to MMU table/context switches, set_domain()
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calls, data aborts, and prefetch aborts.
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Normally the kernel operates with domain != DOMAIN_MANAGER. In this case the
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overhead is minimal. An additional check is required to see if domain manager
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mode is on. This minimal code is added to each of emulation entry points :
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set, data abort, prefetch abort, and MMU table/context switch.
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Initial accesses to a MMU protected page/section will generate a permission
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fault. The page will be manipulated to grant full access permissions and
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the access will be retried. This will typically require 2-3 page table
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walks.
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On a context switch, all modified MMU entries will be restored. On thread
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resume, additional accesses will be treated as initial accesses.
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Interface
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=========
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The emulation does not have clients. It is hooked to the kernel through a
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small list of functions.
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void emulate_domain_manager_set(u32 domain);
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int emulate_domain_manager_data_abort(u32 dfsr, u32 dfar);
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int emulate_domain_manager_prefetch_abort(u32 ifsr, u32 ifar);
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void emulate_domain_manager_switch_mm(
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unsigned long pgd_phys,
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struct mm_struct *mm,
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void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *));
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emulate_domain_manager_set() is the set_domain handler. This replaces the
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direct manipulation of CP15 dacr with a function call. This allows emulation
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to prevent setting dacr manager bits. It also allows emulation to restore
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page/section permissions when domain manger is disabled.
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emulate_domain_manager_data_abort() handles data aborts caused by domain
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not being set in HW, and handles section/page manipulation.
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emulate_domain_manager_prefetch_abort() is the similar prefetch abort handler.
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emulate_domain_manager_switch_mm() handles MMU table and context switches.
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This notifies the emulation that the MMU context is changing. Allowing the
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emulation to restore page table entry permission before switching contexts.
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Config options
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==============
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This option is enable/disable by the EMULATE_DOMAIN_MANAGER_V7 option.
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Dependencies
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============
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Implementation is for ARMv7, MMU, and !SMP. Targets solving issue for 8x50
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chipset.
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User space utilities
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====================
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None
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Other
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=====
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Code is implemented in kernel/arch/arm/mm.
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arch/arm/mm/emulate_domain_manager.c contains comments. No additional public
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documentation available or planned.
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Known issues
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============
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No intent to support SMP or non ARMv7 architectures
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To do
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=====
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None
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