Skip to content

Commit fd1b2de

Browse files
Jiri Pirkovvfedorenko
authored andcommitted
mlx5: Implement SyncE support using DPLL infrastructure
Implement SyncE support using newly introduced DPLL support. Make sure that each PFs/VFs/SFs probed with appropriate capability will spawn a dpll auxiliary device and register appropriate dpll device and pin instances. Signed-off-by: Jiri Pirko <[email protected]>
1 parent 9dd4c99 commit fd1b2de

File tree

6 files changed

+526
-1
lines changed

6 files changed

+526
-1
lines changed

drivers/net/ethernet/mellanox/mlx5/core/Kconfig

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,3 +188,11 @@ config MLX5_SF_MANAGER
188188
port is managed through devlink. A subfunction supports RDMA, netdevice
189189
and vdpa device. It is similar to a SRIOV VF but it doesn't require
190190
SRIOV support.
191+
192+
config MLX5_DPLL
193+
tristate "Mellanox 5th generation network adapters (ConnectX series) DPLL support"
194+
depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE
195+
select DPLL
196+
help
197+
DPLL support in Mellanox Technologies ConnectX NICs.
198+

drivers/net/ethernet/mellanox/mlx5/core/Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,3 +123,6 @@ mlx5_core-$(CONFIG_MLX5_SF) += sf/vhca_event.o sf/dev/dev.o sf/dev/driver.o irq_
123123
# SF manager
124124
#
125125
mlx5_core-$(CONFIG_MLX5_SF_MANAGER) += sf/cmd.o sf/hw_table.o sf/devlink.o
126+
127+
obj-$(CONFIG_MLX5_DPLL) += mlx5_dpll.o
128+
mlx5_dpll-y := dpll.o

drivers/net/ethernet/mellanox/mlx5/core/dev.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,19 @@ static bool is_ib_enabled(struct mlx5_core_dev *dev)
211211
return err ? false : val.vbool;
212212
}
213213

214+
static bool is_dpll_supported(struct mlx5_core_dev *dev)
215+
{
216+
if (!IS_ENABLED(CONFIG_MLX5_DPLL))
217+
return false;
218+
219+
if (!MLX5_CAP_MCAM_REG2(dev, synce_registers)) {
220+
mlx5_core_warn(dev, "Missing SyncE capability\n");
221+
return false;
222+
}
223+
224+
return true;
225+
}
226+
214227
enum {
215228
MLX5_INTERFACE_PROTOCOL_ETH,
216229
MLX5_INTERFACE_PROTOCOL_ETH_REP,
@@ -220,6 +233,8 @@ enum {
220233
MLX5_INTERFACE_PROTOCOL_MPIB,
221234

222235
MLX5_INTERFACE_PROTOCOL_VNET,
236+
237+
MLX5_INTERFACE_PROTOCOL_DPLL,
223238
};
224239

225240
static const struct mlx5_adev_device {
@@ -242,6 +257,8 @@ static const struct mlx5_adev_device {
242257
.is_supported = &is_ib_rep_supported },
243258
[MLX5_INTERFACE_PROTOCOL_MPIB] = { .suffix = "multiport",
244259
.is_supported = &is_mp_supported },
260+
[MLX5_INTERFACE_PROTOCOL_DPLL] = { .suffix = "dpll",
261+
.is_supported = &is_dpll_supported },
245262
};
246263

247264
int mlx5_adev_idx_alloc(void)

0 commit comments

Comments
 (0)