Restrict use of classes and function definitions in assignments or expressions

[luizademelo]

Currently, the fuzzer may generate code where class or function names appear as part of an assignment or expression, such as:

// Seed: 4060241486
module module_1 #(
    parameter id_1 = 32'd62,
    parameter id_2 = 32'd27
) (
    _id_1,
    _id_2
);
  output wire _id_2;
  output wire _id_1;
  always #1;
  class id_3;
    static function void id_4;
      logic id_5;
      id_3 = 1;
    endfunction
  endclass
  module_0 modCall_1 ();
  assign id_2 = id_3;
  always @* id_3::id_4();
endmodule

In this example:

• id_3 (a class) is assigned a value inside the function id_4, which is invalid.

• id_3 is also used in the expression assign id_2 = id_3;, which is not legal.

These usages are syntactically incorrect in SystemVerilog. We should restrict classes and functions to appear only in their valid contexts (e.g., class definitions, function calls) and not as assignable or evaluatable expressions. This might require to change the type inference.